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The main goal of the present study was to investigate how individual differences in working-memory capacity influence the participants' performance and brain networks in a dual-task paradigm. An important function of working memory is to integrate incoming information into an appropriate cognitive model by using two executive functions — updating and inhibition. We hypothesized that individual variability in working-memory function (estimated using operation-span measure) may affect to differential reactivity to both performance and brain connectivity. EEG signals and reaction times were recorded during a dual task that combined n-back and flanker tasks. In these tasks, participants with high working-memory span scores showed a better performance than those with low span scores. This finding suggests that a group with high working memory capacity is more affected by the cognitive control network than a low capacity group, possibly because people with high span utilize more efficient brain network during dual or multitasking situations. These findings contribute to perceiving cognitive control network as an individual trait, which can reflect neural efficiency to allow augmented human cognition, as well as a significant predictor of brain-computer interface performance.

This study investigates the three (motivational, cognitive, behavioral strategy) factors and ten sub factors of self-regulated learning (SRL) ability in terms of the relative importance and contributions to engineering college students' learning outcomes, using the Importance-Performance Analysis (IPA) Matrix, which is a useful tool for identifying improvement priorities and guiding strategic planning efforts. The study procedure comprised two steps: (1) surveying and analyzing of engineering students' perception about the importance and performance of SRL, and (2) determining the priority of SRL ability development for engineering college students. The research results suggest that motivational strategy should be improved to increase engineering college students' learning outcome.

Exciton-polariton lasers are operated in the strong light matter coupling regime. They promise low threshold operation since population inversion is not inherently necessary. Hence they are of great interest for next generation coherent light sources.

In this paper, we present a low-complexity joint estimation algorithm of the direction of arrival (DOA) and time of arrival (TOA) for mobile location system, which is based on a multiple signal classification (MUSIC) algorithm. To reduce the computational overhead of conventional joint DOA/TOA estimation algorithms, the proposed approach employs two complexity reduction schemes: separation of the signal vector for individually extracting DOA/TOA and pseudo-spectrum computation with discrete Fourier transform (DFT). In addition, the loss of accuracy caused by the separation process is compensated by summing multiple pseudo-spectrums. Compared with the conventional two-dimensional (2-D) MUSIC algorithm, the proposed low-complexity algorithm not only substantially reduces the computational complexity but also provides better performance, especially in a low signal-to-noise ratio (SNR). The effectiveness of the proposed algorithm is verified by simulation results.

Exciton-polariton laser diodes are realized by integrating four InGaAs quantum wells in high quality factor doped distributed Bragg reflector microcavities. Efficient current injection into the active region allow to preserve the strong coupling regime between excitons and photons across the threshold of polariton lasing.

We propose a novel location finding system exploiting the downlink reference signal of the Long Term Evolution (LTE) because of the absence of an efficient location finding system for the LTE. The proposed system is based on the correlation method and Chan's method for location sensing and positioning process, respectively. The conventional correlation method, however, is not matched to the LTE since the orthogonal gold sequence used for reference signal is assigned in frequency domain. Therefore, we estimate Time Difference Of Arrival (TDOA) data by cross-correlating the transmitted signal and received signal in the frequency domain. Simulation results show that the proposed system meets the Federal Communication Commission (FCC) requirement for typical Signal-to-Noise Ratio (SNR) region, and the performance can be further improved as more antennas are implemented in transmitter or receiver.

In this paper, we propose a 2-dimensional multi-user location system based on local tactical military communication network for one mobile base-station (BS). The proposed system estimate a location with joint use of angle of arrival (AOA) and received signal strength indication (RSSI) ranging. The locations of multi-user can be estimated with uplink orthogonal frequency division multiple access (OFDMA) signal. Simulations are performed with IEEE 802.16e mobile WiMAX (WiBro) environment. Simulation results demonstrate that the effectiveness of the proposed location system.

A computationally efficient ranging scheme that estimates time of arrival (TOA) by a low complexity minimum mean square error (MMSE) and a matrix pencil techniques is proposed for IEEE 802.15.4a chirp spread spectrum system. In TOA estimation, it is known that accurate channel delay can be estimated by the MMSE technique. However, the major drawback of the MMSE is its high computational complexity, which grows with number of signal samples. In this paper, thus, a computational efficient MMSE technique based on the chirp spectrum characteristic is proposed for a low complexity ranging algorithm. The proposed TOA estimation method consists of two-step signal processing: proposed low complexity MMSE-based channel impulse response (CIR) estimation and the channel delay tracking by matrix pencil algorithm. The proposed TOA estimation method not only has low computational complexity, but also achieves small ranging error. The effectiveness of the proposed algorithm is demonstrated by simulation results.

In this paper, we propose an efficient ranging technique using chirp signal, which employs a matrix pencil method to estimate time of arrival (TOA). The proposed TOA estimation method consists of a two-step signal processing: minimum mean square error (MMSE)-based channel impulse response estimation and the channel delay tracking by matrix pencil algorithm. At the first step, the transmitted known chirp signals are cancelled out using the MMSE criterion. Then, the delay components are extracted by matrix pencil method using the estimated frequency channel impulse response. Simulation results show that the proposed scheme achieves small ranging error with low complexity.

The regenerative properties are investigated for a wavelength converter designed for practical pulse widths. It is better able to cope with a reduction in the optical signal-to-noise ratio than waveform distortion due to residual dispersion.

In this study, we compared sensing margin according to the back gate bias and body doping concentration. We achieved large sensing margin of 62 uA/um at LG = 87 run and demonstrated sensing margin of 45 uA/um with LG = 47 nm that is the smallest device ever reported for the floating body RAM. For the scaling down to the sub 50 nm gate length, we should reduce the body thickness for the SCE with optimum body doping condition . Possibility of scaling down with the capacitor-less RAM is shown to the sub 50 nm from this result.

A theoretical model is presented to analyze the noise transfer characteristics of a semiconductor optical amplifier (SOA) under excitation of a noisy data signal and a noise-free probe signal.

We completed the demonstration of three key functions of SOONO devices by demonstrating the DRAM characteristics of FD and PD SOONO devices successfully, together with the previously reported logic transistor and flash memory characteristics. Floating body SOONO DRAM cells implemented on electrically thin buried insulator shows the large sensing margins more than 5muA in FD device with long data retention and nondestructive read even at the W/L of 60/55nm which is the smallest IT DRAM ever reported.

The influence of phase response ripple on the performance of a tunable dispersion compensator using fiber Bragg grating-based distributed Gires-Tournois etalons is investigated experimentally for 10 Gb/s NRZ transmission. The results reveal the implications of the phase ripple profile on the dispersion compensating performance.

In this article, we proposed and successfully demonstrated 25 nm TiN metal gate nanorod transistors with laterally and vertically scaled actives without process burdens. They showed the excellent short channel effect immunity and high current drivability DIBLs are below 40 mV/V and subthreshold swings are nearly ideal values showing no temperature dependency. The driving currents of 1.4 mA/mum for nMOS and 1.0 mA/mum for pMOS are achieved at Ioff=100 nA/mum and VD =1.0 V. Thus, it is proven that laterally and vertically scaled nanorod transistors can be a promising solution for ultimate scaling

The effect of the SOA phase recovery time, and the DI delay and power splitting ratio on the performance of an SOA-DI all-optical wavelength converter in terms of extinction ratio and Q-factor is investigated. For input signals with practical duty cycles, the DI must be carefully designed to match the characteristics of the SOA

Initial light induced degradation (ILID) has been observed in p-type crystalline and multicrystalline solar cells. Since ILID is strongly correlated with high boron and oxygen content in the solar cell, recent theories suggest that n-type solar cells should be much less susceptible to ILID. Using indoor solar simulation, PV modules containing n-type dendritic web silicon solar cells were studied to observe the presence of ILID. I-V curve measurements were made as the modules received their first light exposure. No degradation in Voc was observed, but a small amount of degradation did appear in I sc and Pmax. The mechanism behind this very low level of degradation is unclear

In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher VTH shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition, we also propose and demonstrate a highly scaled 4-bit DSM using multi-level technology. The VTH shifts above 4V splitting into 4 levels without noticeable interferences are achieved. Each nodes show clear 4 levels with good retention

For the first time, titanium-nitride (TiN) single metal gate and high-k hafnium-silicate (HfSiOx) gate dielectric have been successfully integrated in 55nm McFET SRAM cell. The use of HfSiOx gate dielectric, not only reduces gate leakage current but also improves ION/IOFF ratio of PFET to 108. Using local fin implantation (LFI) scheme, junction capacitance is reduced by 13% and junction breakdown voltage is increased by 1.4V

We proposed a 4-bit double SONOS memory with two ONO layers, 4 storage nodes, for ultimate multi-bit operation and firstly demonstrate 4-bit operation using the physically separated 4 storage nodes. By using CHEI/HHI program/erase, each node was easily programmed and erased without any detrimental interference among the nodes. In the gate length of 120nm, the read/write margins of ~0.8V for front side (FS) and ~1.1V for back side (BS) at VDS=1.2V was obtained. The VTH shifts of ~1.5V for both program/erase (P/E) were observed with the P/E conditions, VD/VFG=3/5V, 3/-4V for FS and VD/VBG=3.2/7V, 3.2/-5V for BS, respectively, with the duration of 1 ms. The VTH windows of ~0.9V for FS and ~1.1V for BS were achieved even after 104 P/E cycles

We proposed and successfully demonstrated Si-on-ONO (SOONO) devices for fully depleted SOI transistor and 4 bit flash memory applications. In terms of HP transistor, SOONO MOSFETs showed good SCE immunity and high driving currents. In terms of a 4-bit flash memory, SOONO MOSFETs with ONO layers as their gate dielectrics showed clear 4-bit operation using the physically separated 4 storage nodes of double ONO layers

We demonstrate SNR improvement of OTDR using simplex codes by experiment, for the first time. For this, we proposed a practical algorithm and derived detailed equations. An in-house OTDR board was developed to verify the proposed algorithm, and the experimental results showed excellent agreement with theory. In addition, we analyzed the SNR variation of the simplex code OTDR, caused by band-limited receiver characteristics.

The work presents a novel positioning system for home service robots. The positioning system uses the difference of flight time between radio frequency and ultrasonic waves to estimate the distance. Especially, the proposed system employs multiple ultrasonic sensors to improve accuracy and position update rate. The experimental result of the proposed system is presented.