166 results on '"Martins R"'
Search Results
2. A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC
3. 22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer
4. A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors
5. A Double-Mode Sparse Compute-In-Memory Macro with Reconfigurable Single and Dual Layer Computation
6. 10.3 A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer
7. 10.5 A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-Prediction-Unrolled Scheme
8. 10.2 A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness
9. 10.7 A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping
10. 17.1 A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input
11. Machine Learning Approaches for Transformer Modeling
12. Systematic Analysis of Microwave Breast Imaging Detection of Different-Sized Malignant and Benign Tumors
13. 27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration
14. RESCCUE RAF App – Using Technology to Mitigate Climate Change Urban Impacts
15. A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS
16. A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS
17. Towards natural interaction in immersive reality with a cyber-glove
18. A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing
19. A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration
20. An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery
21. Positioning. Navigation and Awareness of the !VAMOS! Underwater Robotic Mining System
22. Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs
23. A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS
24. Fields and current densities induced in the human body by low-frequency electromagnetic fields
25. A 0.4 V 6.4 μW 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over −30 to 100 °C for Wearable and Sensing Applications
26. A 5-bit 2 GS/s binary-search ADC with charge-steering comparators
27. Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks
28. Split-based time-interleaved ADC with digital background timing-skew calibration
29. Systematic design of a voltage controlled oscillator using a layout-aware approach
30. A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits
31. New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization
32. A 0.4V 4.8μW 16MHz CMOS crystal oscillator achieving 74-fold startup-time reduction using momentary detuning
33. Background Offset Calibration for Comparator Based on Temperature Drift Profile.
34. Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector.
35. A modified metamaterial antenna for the new wireless communications network
36. Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving.
37. Renewable energy sources insertion in a timber industry — Case study
38. 26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS
39. Metastablility in SAR ADCs.
40. Unified power flow controller performance
41. An all-factor modulation bandwidth extension technique for delta-sigma PLL transmitter.
42. A review and design of the on-chip rectifiers for RF energy harvesting.
43. A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration
44. A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS
45. A 2.93μW 8-bit capacitance-to-RF converter for movable laboratory mice blood pressure monitoring
46. A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis
47. Coordinated control of ocean going vehicles
48. Multi-objective multi-constraint routing of analog ICs using a Modified NSGA-II Approach
49. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC
50. AIDA: Automated analog IC design flow from circuit level to layout
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.