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DArk Matter Particle Explorer (DAMPE), a satel- lite-based cosmic-ray (CR) and gamma-ray measurement experiment, relies on its calorimeter to measure the energy of incident particles. The calorimeter adopts crystals of bismuth germanium oxide (BGO) as scintillating material, and it is designed to aim for measurements of energy ranging from 50 GeV to 100 TeV in the case of a CR nucleus. This article concerns the response of the BGO calorimeter to nucleus-type CRs. CRs with very low energy can rarely reach the detector due to the Earth’s magnetic field. A cutoff on lower energy can be observed in the energy spectrum. In this article, the cutoff is used to study the response of the calorimeter. Carbon, neon, silicon, and iron are analyzed separately in comparison with Monte Carlo simulations by Geant4. [ABSTRACT FROM AUTHOR]

In this paper, early-stage hot-electron generation is shown to inject electrons into the shallow trench isolation (STI) edge above the drift region that causes the linear-region drain current to increase abruptly in the first moment of the stress for P-LDMOS transistors. After this early-stage carrier trapping, the transistor exhibits normal hot-carrier degradation during the following stress period. To further study this phenomenon, the geometry and the doping profile of the drift region near the STI edge and the polysilicon gate doping area are changed to investigate the initial IDLIN increase. Two-dimensional device simulator is used to analyze the experimental results. It is proven that the amount of current increase strongly depends on the distance from the maximum impact ionization generation rate point to the STI. [ABSTRACT FROM AUTHOR]

On-resistance (Ron) degradation induced by avalanche breakdown is investigated in lateral double-diffused MOS transistors with different dosages of n-type drain drift (NDD) region. Ron degradation is caused by interface state and positive oxide-trapped charge created near the drain-side polygate edge. The device with a higher NDD dosage generates less interface state but more positive oxide-trapped charge, leading to a reduction in Ron degradation. Such a result reveals that increasing NDD dosage reduces avalanche-breakdown-induced Ron degradation. [ABSTRACT FROM AUTHOR]

In this letter, hot-carrier-induced on-resistance (Ron) degradation in lateral DMOS transistors with different n-type drift-drain (NDD) region concentration is investigated. Increasing NDD concentration results in greater bulk (Ib) and gate currents (Ig), but Ron degradation is improved. Technology computer-aided design simulations reveal that high NDD concen- tration increases impact-ionization rate in accumulation (related to Ib increase) and channel regions (related to Ig increase) but reduces impact-ionization rate in spacer region. Charge-pumping data confirm that hot-carrier-induced interface state created in the spacer region is reduced, leading to improved Ron degradation in high-NDD-concentration device. [ABSTRACT FROM AUTHOR]

Anomalous increase in saturation-region drain current Id(sat) but serious on-resistance degradation (decrease in linear-region drain current) is observed in n-type high-voltage lateral diffused MOS transistors stressed under medium gate voltage Vg. However, Id(sat) is degraded for the devices stressed under low and high Vg. Experimental data reveal that two competing mechanisms are responsible for the shift of Id(sat). One is the interface state Nit formation in the N- drift region. The other is the Nit formation in the channel region. The former mechanism leads to the anomalous increase in Id(sat), whereas the latter mechanism causes the Id(sat) to decrease. Experimental data and technology computer-aided-design simulations confirm that the impact ionization rate of the device is enhanced if significant Nit formation in the N- drift region is present. According to the results presented in this paper, significant Nit formation in the N- drift region is identified to be the main mechanism responsible for the anomalous increase in Id(sat). [ABSTRACT FROM AUTHOR]

This letter demonstrates a successful method for ON-state resistance reduction up to 20% by Shallow Trench Isolation (STI) fingers and with extra NLDD implant in the fingered region simultaneously for medium power devices. This fingered region provides a multidimensional electric field that avoids MOSFET breakdown voltage decrease, and it also shortens the drain-current conduction path. Therefore, low ON-state resistance and high drain driving current is obtained in our proposed device. Careful design for structural parameters of this STI finger is needed to achieve the optimum RON performance without hurting breakdown voltage. [ABSTRACT FROM AUTHOR]

In this letter, on-resistance (Ron) degradation induced by hot-carrier injection in n-type lateral DMOS transistors with shallow-trench isolation (STI) in the drift region is investigated. Ron decreases at the beginning of stress, but Ron increases as the stress time is increased. Experimental data and technology computer-aided-design simulation results reveal that hot-hole injection and trapping at the STI corner closest to the channel are responsible for the Ron reduction. The damage caused by hot-electron injection at the STI edge closest to the drain is responsible for the Ron increase. [ABSTRACT FROM AUTHOR]

In this letter, ON-resistance RON degradation in lateral double-diffused MOS transistors is observed when the device is operated under OFF-state avalanche-breakdown condition. Although interface states and positive oxide-trapped charges are created near the drain, interface-state generation is identified to be the main degradation mechanism. Technology computer-aided design simulation suggests that the driving force of damage is breakdown-induced hole injection. Experimental data show that RON degradation has the tendency to saturate, in agreement with the saturation of interface-state generation and oxide-trapped charges data extracted by charge-pumping measurement. [ABSTRACT FROM AUTHOR]