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An important issue in wireline receivers (RX) is minimizing the area and power consumption while overcoming the channel attenuation with an equalizer. The greater the compensation for channel loss at the analog front end (AFE) of the RX, the lower the number of decision feedback equalizer (DFE) taps. Power dissipation and area can be reduced by reducing the number of DFE taps. This brief presents a technology that compensates for the channel loss with the proposed AFE based on a two-stage continuous-time linear equalizer (CTLE), low and high bandwidth amplifiers, and a gain controller. It sufficiently reduces the DC gain and increases the peak gain of the AFE by using a feedforward equalizer (FFEQ) and feedback equalizer (FBEQ). These equalizers result in an increase in the difference between the peak and DC gains and the gain difference at the fundamental frequency (f0) and 2nd subharmonic frequency (f1/2). The IC is fabricated in a 28 nm CMOS process, and the proposed architecture yields a BER less than 10−12 at 25.8 dB channel attenuation. At 25 Gb/s, the area and power efficiency of the proposed AFE are 1.19 pJ/bit and 0.01 mm2, respectively. [ABSTRACT FROM AUTHOR]

This brief presents a low-power counter-based adaptive equalizer that does not require additional power-hungry comparators for an equalizer adaptation loop. A pulse generator in the proposed equalizer obviates the need for additional error sampling comparators. Instead, it allows the receiver to utilize an output of a data decision comparator for the equalizer adaptation by generating a pulse that indicates whether the comparator makes a firm decision for the incoming data. A single comparator is shared by the data recovery path and equalizer adaptation loop. Consequently, the proposed counter-based equalizer achieves a low power dissipation owing to the reduced number of comparators. Fabricated in a 28-nm CMOS technology, the prototype receiver occupies an active area of 0.004 mm2 and consumes only 0.99-pJ/b at 15-Gb/s. [ABSTRACT FROM AUTHOR]

This paper presents a new pin/energy-efficient data and clock signaling scheme, named braid clock signaling (BCS). This signaling scheme efficiently embeds clock information into the data stream without data overhead, unnecessary pins, and channels for clock. To remove the data overhead, the clock information is embedded in every other data period. This high transition density (TD) leads to the enhanced jitter tracking performance of a receiver and increased stability. Furthermore, a spread transition scheme (STS) removes the additional power consumption for the embedded clock with little electromagnetic interference (EMI). As non-return-to-zero (NRZ) signaling uses only two voltage levels, the NRZ BCS secures a large input voltage margin at the receiver side, unlike other pin-efficient multi-level signaling schemes. An analysis of the secured voltage margin shows improved energy efficiency over conventional pin-efficient multi-level signaling schemes, even without consideration of their clocking power dissipation. The prototype transceiver is fabricated in a 28-nm CMOS process with a 12-Gb/s delay-locked loop (DLL)-based receiver over four lines. [ABSTRACT FROM AUTHOR]

A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a ${\Delta } {\Sigma }$ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth ($ {f}_{{\text {LBW}}}$). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of $ {f}_{\text {LBW}}$ variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest $ {f}_{\text {LBW}}$. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2. [ABSTRACT FROM AUTHOR]

A spread-spectrum clock generator is implemented using a nested modulation profile to reduce the peak power levels of radiated electro-magnetic emissions in display products. The display data interface is a potential source of interference, and the spread spectrum technique has been extensively used for display interfaces. The proposed nested profile can further reduce electro-magnetic interference without any degradation in the other characteristics. A test chip was fabricated using a 55-nm CMOS process, and the test results indicate a 41-dB reduction. The sensitivity of a wireless receiver to interference is tested, and the EVM results for the proposed nested profile exhibits an improvement of 1.4 dB compared to those of the triangular profile. [ABSTRACT FROM AUTHOR]

A power reduction scheme that uses ac termination at receiver (RX) and a transmitter (TX) output driver with an active inductor part (AIP) is proposed for a point-to-point post-low-power mobile DRAM4 interface at 8 Gb/s. AC termination at the RX I/O can reduce the power consumption by preventing dc power loss. However, this causes inter symbol interference (ISI), owing to the difference in gain depending on the frequency. Thus, ac termination generates more jitter, which results in a smaller eye-opening than the conventional on-die termination. The AIP in the TX output driver reduces the low-frequency gain and the ISI caused by the ac termination. This reduces the jitter and improves the eye-opening. The proposed AIP allows changing the frequency range by adjusting the resistance ( R\mathrm{AI} ), capacitance ( C \mathrm{AI} ), and the size of the MOSFET according to the resistance ( R \mathrm{ac} ) and capacitance ( C \mathrm{ac} ) used in the ac termination at the RX. In this brief, the ac termination at the RX and the AIP in the TX were implemented in a 28-nm CMOS process and operated at 8 Gb/s with a 3-inch FR4 microstrip line including a board and a socket model. The proposed transceiver chip achieves a peak-to-peak jitterof 43.6 ps and power reduction of 31% compared with chips without ac termination and AIP. [ABSTRACT FROM PUBLISHER]

An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UI \mathrm { {pp}} at 100 MHz with < 10^\mathrm -12 BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UI \mathrm { {pp}} at 300 MHz with < 10^\mathrm -12 BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm ^\mathrm 2 in a 0.13- \mu \textm CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW. [ABSTRACT FROM PUBLISHER]