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E-beam voltage contrast inspection is a very common method for in-line detection of many key defect types for rapid yield learning during technology development. Generally, the wafer surface is charged positive, but sometimes charging the wafer surface negative makes more sense. This paper reviews four advantages that negative charging may provide. Switching from positive to negative charging is typically achieved using landing energy and/or extraction voltage. A third control knob is introduced and demonstrated using three common inspection layers, contact chemical mechanical polish (CMP), 3D NAND wordline shorts and 3D NAND wordline opens. [ABSTRACT FROM AUTHOR]

In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through compact design.

To maximize national investments in science gateways (SGs) and cyberinfrastructure (CI), understanding and harnessing the factors that enable user adoption are critically valuable. In this article, we discuss how the social science concepts of influencers and opinion leaders apply in SG/CI domains and help drive user adoption. We identify three key aspects of influencers based on a systematic analysis of 132 interviews with SG/CI users and experts from 2016–2019: who they are, what qualities they possess, and how they communicate. We find that SG/CI influencers will be most effective if they possess mentoring roles, are active and visible members of an academic or professional community, and facilitate growth within SG/CI at the individual and community levels. We also outline 12 techniques organized under four methodological approaches that SG/CI staff can employ to recruit influencers to help promote adoption. [ABSTRACT FROM AUTHOR]

Effective communication is vital for academic project success, particularly in multidisciplinary teams with diverse backgrounds and disciplines. Misunderstandings can arise from differing interpretations of terms, which may go unnoticed. VisDict aims to bridge this gap by creating a visual dictionary within a science gateway to facilitate clear communication between workflow providers and domain researchers. This innovative approach translates computational science concepts into fields like physics and biology. This article delves into our method for building the visual dictionary, the insights gained from curating initial entries, and future plans for automated expansion and illustration of relevant terms. [ABSTRACT FROM AUTHOR]

Two-mode low-voltage dc–dc converter (LDC) has been proposed for high and wide input voltage range in order to overcome the drawbacks of the conventional converters. With two operational modes, the two-mode LDC reduce the voltage stresses on the switches and dc offset current. However, it has large differences of capacitor voltage resulting in voltage spike on the switch at the mode transient. Moreover, the dc offset current has large variation between two modes. In this article, a variable control for two-mode LDC is proposed for changing the operational mode softly. The two mode LDC employing the proposed control is shown to minimize the difference of capacitor voltage and dc offset current over the entire input voltage range. The proposed control is verified by a 350–800 V input and 13.9 V/600 W output laboratory prototype. [ABSTRACT FROM AUTHOR]

Researchers and educators in humanities such as computational linguists, digital humanists, and those doing historical reconstructions are increasingly heavy users of computational and/or data resources. Many know about activities, working groups, and initiatives around the findable, accessible, interoperable, reusable (FAIR) principles and are a driving force for improving the sharing of data and software. However, it seems humanities researchers are less aware of the science gateways community and the end-to-end solutions that science gateways could provide, therefore lacking a driving force for adoption of this technology. This small-scale exploratory study will clarify some of the challenges and needs faced by computational researchers in the humanities that may explain their relatively low participation in the science gateways community. For this paper, we present the results of 19 interviews with seven women, 11 men, and one nonbinary individual from seven states and DC in the United States with a range of professional backgrounds and roles. [ABSTRACT FROM AUTHOR]

Transforming into an agile organization is challenging because it involves complex changes across the organization including changes to strategy, structure, culture, operations, and technology. Although much has been written about organizational agility, practitioners still call for authentic accounts and concrete experiences to help them understand how to transform. This article is based on three case studies of diverse organizations transforming to agility and provides an account of each transformation. Each organization chose a different focus for their transformation: culture change, strategic change, and operational change. Each organization faced challenges that resulted in tensions. We present 13 tensions from three cases, which illustrate the kinds of tension that organizations face in agile transformations. We consider these 13 tensions through the lens of paradox theory and thereby produce both practical guidance and theoretical contributions. We show how questions generated from this perspective may be used to guide transformation leaders and managers in addressing the tensions they will meet. Our findings provide empirical evidence for the tension categories in paradox theory and show that tensions occur during transformations to agility and not just in fully agile organizations. [ABSTRACT FROM AUTHOR]

For the 7-nm technology node, cell placement with a drain-to-drain abutment (DDA) requires additional filler cells, increasing the placement area. This is the first work to fully automatically synthesize a DDA-aware cell library with the optimized number of drains on cell boundary based on ASAP 7-nm PDK. We propose a DDA-aware dynamic programming-based transistor placement. Previous works ignore the use of the M0 layer in cell routing. We first propose an ILP-based M0 routing planning. With M0 routing, the congestion of M1 routing can be reduced and the pin accessibility (PA) can be improved due to the diminished use of M2 routing. We also present a quadratic-programming based-coupling-capacitance-aware initial routing to optimize cell delay, cell area, and M2 usage. To improve the routing resource utilization, we propose an implicitly adjustable grid map, making the maze routing able to explore more routing solutions. The experimental results show that block placement using the DDA-aware cell library requires fewer filler cells than that using the traditional cell library by 25.1%, which achieves a block area reduction rate of 0.97%. [ABSTRACT FROM AUTHOR]

Undetectable faults result from logic redundancies and constraints on applicable tests. The presence of an undetected (undetectable or aborted) fault implies that a test, which would have covered its site, is missing from the test set. When undetected transition faults form a path, the missing tests imply that (small) delay defects along the path may not be detected even if they are detectable. The goal of this article is to provide additional coverage for paths of undetected transition faults by using two-cycle gate-exhaustive faults for subcircuits (gates) that wrap the paths. The use of gate-exhaustive faults alleviates the need to model delay defects along the paths, or use path delay faults that may also be undetectable. The article defines the target paths, and gates that wrap them, for which two-cycle gate-exhaustive faults can be defined. Experimental results for benchmark circuits demonstrate the discussion. [ABSTRACT FROM AUTHOR]

With the emergence of the multicore architecture and the increase of chip operating frequency, power optimization has become a key step of circuit logic synthesis. Aiming at the XNOR/OR circuits, with the goal of minimizing power, construct the optimal polarity fixed-polarity Reed–Muller (FPRM) circuits power optimization scheme. However, the power optimization for FPRM circuits is a multipeak combinatorial optimization problem, we first propose a metaheuristic optimization algorithm (MOA), which includes the global exploration optimizer, local deep exploitation optimizer, and initial population and uses the proposed differential evolution optimization, fierce wolf siege algorithm-based tabu search, and improved skew tent map to make the population evolve. Based on the proposed Huffman tree construction algorithm and MOA, we propose an efficient power optimization approach (EPOA) to find the minimum power FPRM circuit. Experimental results on the benchmark circuits confirm the effectiveness of EPOA. [ABSTRACT FROM AUTHOR]

The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads. Finding a feasible worst case workload is difficult due to logical correlation within the logic circuit under consideration. In this article, we propose an NBTI-aware subset simulation (SS) framework that efficiently and accurately finds the failure probability covering various input duty cycles determined by different workloads. In addition, the proposed method is incorporated with the NBTI mitigation technique to facilitate workload-aware mitigation. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to a naive Monte Carlo method. The NBTI mitigation based on SS demonstrates $1.78\times $ better mitigation for multiple input duty cycles compared to the conventional method. [ABSTRACT FROM AUTHOR]

In recent years, very high frequency (VHF) converter has attracted much attention. However, with rich parasitic parameters and complex resonance links, there are some great difficulties to the modeling of such systems. Taking the on-off controlled VHF resonant boost converter as an example, this paper presents an accurate modeling and analysis method that considers multiple parasitic parameters. First, the closed-loop VHF converter system is divided into a main network and a parasitic oscillation network. Then, based on the operation analysis, an equivalent circuit model characterized by a time-varying input voltage source and two variable duty-cycle controlled switches is proposed. It worth noting that both the time-varying input and the controlled switches take into account the influences of the parameters. Furthermore, the periodic approximate analytical solution of the output voltage in the on stage is obtained by using the equivalent small parameter method to the proposed circuit model. And then combining the solution of the parasitic oscillation network and on-off state switching conditions, the steady-state waveform of output voltage can be obtained quickly. Finally, a prototype with operating frequency of 21.44 MHz is built to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

In this work, we study experimentally the impact of different gate dielectric stacks on the subthreshold behavior of cryogenic MOSFETs. While in room temperature devices, silicon nitride deteriorates the off-state of MOSFETs it turns out that at cryogenic temperatures an appropriately thin, grown silicon nitride layer in combination with a high-k gate dielectric counteracts the saturation of the inverse subthreshold slope and inflection phenomena. As a result, steep slope cryogenic MOSFETs with strongly improved subthreshold behavior are demonstrated. [ABSTRACT FROM AUTHOR]

In this letter, the word line (WL) interference behavior in 3D NAND cell and the impact on program sequence of 3D NAND array operation are discussed. The WL interference induced by source-side neighboring cell is always smaller than that induced by drain-side neighboring cell. Due to this asymmetric characteristic, program sequence from top to bottom will have the advantage of suffering less operation window loss resulting from WL interference, over the traditional program sequence from bottom to top. This advantage can be clearly validated by the experimental results. However, at some specific WL’s of the array, the trend is reversed. The root cause of the reverse trend is then clarified to result from the unexpected undercut of sacrificial nitride film occurring during the imperfect vertical channel etching process for 3D NAND array formation. [ABSTRACT FROM AUTHOR]

HfO2 based ferroelectric field-effect transistors (FeFETs) are promising for low-power and high-speed non-volatile memories. However, FeFETs can be susceptible to write disturbs due to their accumulative switching behavior, which limits their application in large scale memory arrays. Here we show that FeFETs with a thin HfO2 based ferroelectric and SiNx interfacial layer are immune to pulsed write disturbs under both ${V}_{\textit {dd}}$ /2 and ${V}_{\textit {dd}}$ /3 inhibit schemes, but not to continuous write disturb. This contrasts with previous reports which found no difference between pulsed and continuous write disturbs. Our findings suggest that accumulative polarization switching is not an intrinsic property of HfO2 based FeFETs, but might be related to charge trapping dynamics instead. [ABSTRACT FROM AUTHOR]

In this paper, a novel superjunction MOSFET with ohm contact in the termination region and dual Schottky contacts in the cell region is proposed and experimentally demonstrated. The dual Schottky contacts consisting of the N-type Schottky contact and the P-type Schottky contact suppress the hole injection in the cell region, thereby reducing the reverse recovery charge and enhancing the current density in the termination region. The high current density and the ohm contact in the termination region provide sufficient slowly extracted non-equilibrium holes during the reverse reduction period, which contributes to a significantly improved softness. Experimental results show that, in comparison with the conventional superjunction MOSFET, 66.2% reduction in reverse recovery charge and 137.5% improvement in softness factor can be obtained in the proposed superjunction MOSFET. [ABSTRACT FROM AUTHOR]

In this article, the proposed monolithic gallium nitride (GaN)-based driver uses the diode-emulated technique to reduce reverse conduction through a meta-stable fast (MSF) comparator with sub-0.2-ns deadtime. In addition, an active bootstrap controller with a fast discharge loop is used to reduce parasitic effects to improve the driving capability, thereby increasing the switching frequency. Furthermore, the proposed gate driver with dual $dv/dt$ control can reduce the gate-ringing during turn-on/turn-off. Experimental results show that the GaN-based monolithic driver can achieve an operating frequency of 50 MHz and a slew rate of 120 V/ns. At 50 MHz, the conversion of 48-to-5 V can achieve a peak efficiency of 95.4% at the load current of 3.5 A. [ABSTRACT FROM AUTHOR]

XOR-AND Graphs (XAGs) are an enrichment of the classical AND-Inverter Graphs (AIGs) with XOR nodes. In particular, XAGs are networks composed by ANDs, XORs, and inverters. Besides several emerging technologies applications, XAGs are often exploited in cryptography-related applications based on the multiplicative complexity of a Boolean function. The multiplicative complexity of a function is the minimum number of AND gates (i.e., multiplications) that are sufficient to represent the function over the basis {AND, XOR, NOT}. In fact, the minimization of the number of AND gates is important for high-level cryptography protocols such as secure multiparty computation, where processing AND gates is more expensive than processing XOR gates. Moreover, it is an indicator of the degree of vulnerability of the circuit, as a small number of AND gates corresponds to a high vulnerability to algebraic attacks. In this paper we study the multiplicative complexity of Boolean functions characterized by two particular regularities, called autosymmetry and D-reducibility. Moreover, we exploit these regularities for decreasing the number of AND nodes in XAGs. The experimental results validate the proposed approaches. [ABSTRACT FROM AUTHOR]

A quantum phase slip junction (QPSJ) based direct inverter gate is proposed in this article for the first time. The proposed inverter is simpler than the QPSJ-based inverter designed indirectly by using a two-input xor gate with specific input conditions. In the indirect inverter, one of the two inputs of the xor gate must be set to the clock pulse in order to perform the true inverter operation. However, the proposed direct inverter has only one input to which the input voltage can be applied directly, and therefore, it has a simpler structure with fewer elements that occupies less area on the chip. The true operation of the proposed inverter is verified by feeding its input with the standard pseudorandom binary sequence 3 and connecting its output to the next gate to test its ability for driving the next gate. [ABSTRACT FROM AUTHOR]

Advanced field-effect transistors (FETs), such as gate-all-around (GAA) nanowire (NW) and nanosheet (NS) devices, have been highly scaled; therefore, they are critically affected even by a microscopic fluctuation. As the GAA NS device is considered a promising candidate beyond 5-nm technology, it is essential to analyze the effects of these fluctuations on dc and analog/radio frequency (RF) characteristics for future applications. In this article, we for the first time demonstrate that the machine learning (ML)-aided numerical device simulation approach can be used to model the effects of various fluctuations on the characteristics of GAA NS FETs (NSFETs). Among various fluctuations, we mainly focus on work function fluctuation (WKF), random dopant fluctuation (RDF), and interface trap fluctuation (ITF). The independent and combined effects of these fluctuations on the characteristics of NSFETs are studied. Except for transfer and output characteristics, analog and RF parameters, such as gate capacitance, transconductance, cutoff frequency, 3-dB frequency, and transconductance efficiency, are analyzed in detail. The main aim of this work is to show the capability and generality of ML in modeling various electrical characteristics of the explored NSFETs. The results show that the ML-based technique is fast and efficient, which accelerates the overall process and gives engineering acceptable accurate results. [ABSTRACT FROM AUTHOR]

Physical unclonable functions (PUFs) have been adopted in many resource-constrained Internet of Things (IoT) applications to provide effective and lightweight solutions for device authentication. However, an attacker can collect challenge–response pairs (CRPs) of a strong PUF, to build a machine learning (ML) model and mimic its behavior, i.e., predicting the responses of unseen challenges with high accuracy. Although several PUFs have been proposed to resist such modeling attacks, they incur high hardware overhead. Developing a PUF primitive with low hardware cost and high resistance to ML attacks is thus a crucial task. In this article, we propose the first response–feedback-based lightweight anti-ML-attack PUF (FLAM-PUF). It is only composed of one arbiter PUF (APUF) and one Galois linear-feedback shift register (LFSR), with some basic logic gates, reducing more than 62% hardware cost compared with the state-of-the-art robust strong PUFs. Specifically, FLAM-PUF leverages a cost-effective feedback loop structure to dynamically control and update the LFSR configuration. FLAM-PUF has two main characteristics: 1) it feeds back a 1-bit response in every cycle to intentionally poison the data of the CRP set for training. To resist ML-based modeling attacks, the 1-bit response can randomly update one coefficient of the feedback polynomial to implant more complex correlations into the model built by attackers and 2) it takes advantage of an $n-$ bit response feedback-controlled reconfigurable Galois LFSR to enlarge the original challenge space of the APUF. Extensive experimental results show that the proposed FLAM-PUF achieves near-optimal uniformity, uniqueness, and reliability. Our scheme works well under standard attack models with public crucial initial information. In particular, the prediction accuracy of modeling attacks against FLAM-PUF is nearly 50% under the four widely used ML algorithms, i.e., support vector machines (SVMs), logistic regression (LR), covariance matrix adaptation evolution strategy (CMA-ES), and deep neural networks (DNNs), indicating excellent resistance against these ML attacks. [ABSTRACT FROM AUTHOR]

This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows $>5\times $ reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself. [ABSTRACT FROM AUTHOR]

Reducing the number of AND gates in logic networks benefits the applications in cryptography, security, and quantum computing. This work proposes a don’t-care-based (DC-based) approach to reduce the number of AND gates further in the well-optimized network. Furthermore, this work also proposes an enhanced synthesis flow by integrating our approach with the state-of-the-art. The experimental results show that our approach can further reduce up to 25% of the number of AND gates in the network. For the experiments about the enhanced synthesis flow, we achieve a speedup of almost $10\times $ on average for the cryptography benchmarks while having competitive results as compared to the flow in the state-of-the-art. [ABSTRACT FROM AUTHOR]

Logic obfuscation is introduced as a pivotal defense against multiple hardware threats on integrated circuits (ICs), including reverse engineering (RE) and intellectual property (IP) theft. The effectiveness of logic obfuscation is challenged by recently introduced Boolean satisfiability (SAT) attack and its variants. A plethora of counter measures have also been proposed to thwart the SAT attack. Irrespective of the implemented defense against SAT attacks, large power, performance, and area overheads are seen to be indispensable. In contrast, we propose a cognitive solution, which is a neural network (NN)-based SAT-hard clause translator, SATConda, that incurs a minimal area and power overhead while preserving the original functionality with enhanced security. SATConda is incubated with a SAT-hard clause generator that translates the existing conjunctive normal form (CNF) through minimal perturbations, such as the inclusion of pair of inverters or buffers or adding new lightweight SAT-hard block depending on the provided CNF. For efficient SAT-hard clause generation, SATConda is equipped with a multilayer NN that first learns the dependencies of features (literals and clauses), followed by a long short-term memory (LSTM) network to validate and backpropagate the SAT-hardness for better learning and translation. Our proposed SATConda is evaluated on ISCAS’85 and ISCAS’89 benchmarks and is seen to successfully defend against multiple state-of-the-art SAT attacks devised for hardware RE. In addition, we also evaluate our proposed SATConda’s empirical performance against MiniSAT, Lingeling, and Glucose SAT solvers that form the base for numerous existing deobfuscation SAT attacks. [ABSTRACT FROM AUTHOR]

The identification of reliability-critical primary input leads (RCPIs) plays an important role in the testing and prediction of reliability boundaries of logic circuits. This article presents a gate-sensitive-attributes-based approach to estimate the criticality of the primary input leads in combinational circuits to their reliability. Oriented to the input vector, a subcircuit-based traversal method marks the critical input leads of each gate in a circuit. Gate-sensitive attributes and a reverse recursive algorithm quantify the effect of each RCPI on circuit reliability under the input vector. A parallel calculation method based on subcircuits with only one primary output reduces the computational complexity to accelerate the calculation process. Similarity-based clustering avoids unnecessary calculations, and a self-adaptive strategy is used to check convergence. Experimental results on benchmark circuits show that the average accuracy of this approach is 0.9634 with Monte Carlo (MC) as the reference and it is 3445 times faster than the MC on average while its average memory cost is 1.67 greater than the MC model. Although the fitness of the worst input vector obtained by other reference methods is 1.09 times better than that of this approach on average, this approach is approximately 21 times faster than that reference method on average. [ABSTRACT FROM AUTHOR]

Conventional digital LLC synchronous rectifier (SR) control typically uses detection circuits to sense the drain-source voltage of SR MOSFET in low output voltage applications, or gives SR duty cycle only considering the switching frequency in the microcontroller. They are difficult to be applied to the applications of 700-V high voltage and 6.6-kW high power directly due to the high dv/dt and large SR duty cycle variations, which poses serious challenge for SRs control. A bidirectional impedance-based SR driving scheme is presented for high-voltage SiC LLC converter. Based on the LLC equivalent impedance, mathematical models are built to calculate the SR on-time in the forward and reverse modes, which can be tuned timely when the switching frequency and load vary. Thus, both bidirectional LLC performance with high efficiency and high immunity to the switching noise can be achieved without adding auxiliary circuits. A prototype of 300-kHz 6.6-kW SiC bidirectional LLC charger was built. Compared to the conventional SR method, the LLC efficiencies improve 0.3% in the forward and reverse modes at full load by using the proposed SR driving scheme. [ABSTRACT FROM AUTHOR]

Like conventional two-switch leg converters, the three-switch leg converters also have short-circuit risks and a dangerous shoot-through current is generated if switches of the same leg are turned on simultaneously. In this article, a new dual-buck structure is proposed for three-switch leg converters. The proposed structure is reliable because of no shoot-through concerns and high quality of output waveforms can be obtained due to the reduction in pulsewidth modulation deadtime. Unlike the conventional dual-buck three-switch leg that uses many passive components such as four current limiting inductors and three external diodes, the new dual-buck three-switch leg uses only one current limiting inductor with two external diodes. To verify the performance, the proposed three-switch legs are used in single-phase dual-output inverter and detailed theoretical analysis, simulation, and experiments are performed. Both continuous and discontinuous modulation schemes are applied and it has been figured out that discontinuous modulation scheme can improve the dc-link voltage utilization in the common-frequency mode of operation. [ABSTRACT FROM AUTHOR]

The single gate driven series connected power device stack possesses the advantages of high compactness and low cost. However, research of its short circuit (SC) characteristic remains uncovered. This article fills this gap and points out that, with the single gate driver it has the potential of over-current limitation. Furthermore, based on it, an improved single gate driven silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (mosfet) stack with strong antishort circuit fault capabilities is proposed. By adding auxiliary circuits to adjust the driving process of the single gate driver, the SiC mosfet stack can be automatically turned off in both SC conditions of fault under load and hard switch fault, while the normal working principle of the stack is not influenced. Neither active control nor overcurrent detection is required, which is the biggest merit of the proposed topology. Its design and analysis are presented in detail, followed by the validation by conducting simulations and experiments. [ABSTRACT FROM AUTHOR]

A novel methodology for total ionizing dose (TID) hardening of Silicon-on-insulator (SOI) MOSFET is demonstrated by employing a superior type of void embedded SOI (VESOI) substrate. With the successful removal of most of the radiation sensitive area in buried oxide, the TID tolerance of VESOI MOSFET is significantly enhanced in comparison to its conventional SOI counterpart. In particular, the shift of threshold voltage (${V}_{\text {th}}$) and subthreshold swing is only −38.9mV and 11.6mV/dec at radiation doses up to 2Mrad(Si). Further device simulation shows that the radiation immunity can withstand misalignment between the gate and embedded void in a wide range. Our VESOI substrates, offering both high compatibility with planar CMOS process and versatile void embedded device design, exhibit great potential in the development of anti-radiation SOI devices. [ABSTRACT FROM AUTHOR]

A novel 3D NOR memory array with single-crystal silicon channel, high-density and fast-read was proposed and fabricated. The proposed 3D NOR memory is investigated in terms of device structure, integration scheme, and circuit architecture. To obtain single-crystal silicon channel for 3D NOR, 1) vertical flash devices were presented, 2) a stack with multiple doped epitaxial Si layers was used for making the vertical devices, and 3) unlike 3D NAND, bit-line planes, source-line planes and vertical word-lines were utilized. Due to the use of single-crystal silicon channels, our memory devices have large read currents of $110 ~\mu \text{A}/\mu \text{m}$. Through programming/erasing tests, the programming speed of $10 ~\mu \text{s}$ and erasing speed of 100 ms were obtained, which are comparable to that of the 2D NOR Flash with single-crystal silicon channels. [ABSTRACT FROM AUTHOR]

Developing the multi-valued logic circuits, that can handle more data than the conventional binary logic circuits, is a promising strategy to break through the well-known Moore’s law. In this letter, we demonstrate quaternary logic circuits, for the first time, based on the four-level organic thin-film transistor nonvolatile memories (OTFT-NVMs) as the core components. High-performance four-level OTFT-NVMs are achieved, with the low programming/erasing voltages of ±15 V, high mobility up to 7.4 cm2/Vs, reliable endurance, and stable retention capabilities. By connecting the four-level OTFT-NVMs with a load resistance in the reasonable ways, we build the logic circuits to reliably perform quaternary logic operations of NOT, NAND and NOR, respectively. Our works lay the foundation to develop the novel quaternary integrated circuits in hardware. [ABSTRACT FROM AUTHOR]

This letter studies the impact of multi-domain dynamics on the memory window (MW) of a Ferroelectric FET (FeFET). The memory window primarily depends on the density of domains in the ferroelectric region. We show that a maximum MW is possible if one domain wall is present in the ferroelectric layer. Furthermore, enhancing the ferroelectric layer thickness decreases the gradient energy leading to an expansion in the domain period. This increased domain period reduces the domain density and improves the MW. On the other hand, domain density increases with the increase in dielectric layer thickness, which reduces the MW. Additionally, the nature of the domain wall also alters the MW remarkably, causing a reduction in the MW when the domain wall gradually switches from hard to soft. The optimum range of the device’s physical parameters is obtained by minimizing the net ferroelectric thermodynamic energy corresponding to the maximum MW and serves as a device design guideline. [ABSTRACT FROM AUTHOR]

${p}$ -channel GaN field-effect transistors (FETs) with a SiNx/GaON gate stack have been demonstrated with enhanced stability within a wide range of voltage bias and temperature. In this letter, the gate leakage characteristics and reliability of this unconventional staggered gate stack are investigated. At relatively low gate voltages, the gate current is suppressed owing to the buried-channel structure and the presence of GaON that presents an effective hole barrier. With more negative gate biases, the gate leakage was found to be dominated by the transport of holes that spillover from the ${p}$ -channel through the SiNx via Poole-Frenkel emission. Based on this gate leakage mechanism at large gate bias, $\sqrt {{\mathrm {E}}} $ model was used for gate lifetime prediction. The maximum applicable ON-state gate voltage of −7.3 V is obtained for a 10-year lifetime with a 1% gate failure rate. [ABSTRACT FROM AUTHOR]

In this study, the channel length dependence of hot carrier degradation (HCD) in ultra-scaled nFinFETs is experimentally investigated with the self-heating correction. By electrical characterizations of nFinFETs with different channel lengths, the novel insight into the HCD mechanism is proposed upon considering the trap behaviors, including both interface traps and oxide traps. Our experimental results show that the proportion of interface traps in total traps is strongly dependent on the channel length. Furthermore, the interface traps induced by HCD are located near the source side in ultra-scaled nFinFETs, which is different from the phenomena in long channel devices. [ABSTRACT FROM AUTHOR]

This article presents the first keyword spotting (KWS) IC that uses a ring-oscillator-based time-domain processing technique for its analog feature extractor (FEx). Its extensive usage of time-encoding schemes allows the analog audio signal to be processed in a fully time-domain manner except for the voltage-to-time conversion stage of the analog front end. Benefiting from fundamental building blocks based on digital logic gates, it offers better technology scalability compared to conventional voltage-domain designs. Fabricated in a 65-nm CMOS process, the prototyped KWS IC occupies 2.03 mm 2 and dissipates 23- $\mu \text{W}$ power consumption, including analog FEx and digital neural network classifier. The 16-channel time-domain FEx achieves a 54.89-dB dynamic range for 16-ms frame shift size while consuming 9.3 $\mu \text{W}$. The measurement result verifies that the proposed IC performs a 12-class KWS task on the Google Speech Command dataset (GSCD) with >86% accuracy and 12.4-ms latency. [ABSTRACT FROM AUTHOR]

This article presents a bounded model checking (BMC)-based temperature-aware software-based self-testing (SBST) technique to test worst case delay faults within the highest temperature range. The BMC-based SBST method first defines the sequential constraint. It develops a sequentially constrained automatic test pattern generation (ATPG) to ensure that the generated delay test patterns can emerge in functional mode. It then uses the processor’s multiple-level information to reduce the model complexity, avoid aborts due to time-outs during the BMC process, and generate test programs automatically. A temperature-aware SBST method has then been developed to ensure that the test temperature is within the specified range and test the worst case delays under high temperature. Experimental results demonstrate that the proposed technique achieves an extremely high coverage for delay faults and effectively avoids yield loss caused by the overtesting problem. Its test quality also outperforms that of the existing methods. The generated SBST programs are successful and efficient in testing worst case delay faults under high temperature. [ABSTRACT FROM AUTHOR]

In this paper, a simple yet effective network pruning framework is proposed to simultaneously address the problems of pruning indicator, pruning ratio, and efficiency constraint. This paper argues that the pruning decision should depend on the convolutional weights, and thus proposes novel weight-dependent gates (W-Gates) to learn the information from filter weights and obtain binary gates to prune or keep the filters automatically. To prune the network under efficiency constraints, a switchable Efficiency Module is constructed to predict the hardware latency or FLOPs of candidate pruned networks. Combined with the proposed Efficiency Module, W-Gates can perform filter pruning in an efficiency-aware manner and achieve a compact network with a better accuracy-efficiency trade-off. We have demonstrated the effectiveness of the proposed method on ResNet34, ResNet50, and MobileNet V2, respectively achieving up to 1.33/1.28/1.1 higher Top-1 accuracy with lower hardware latency on ImageNet. Compared with state-of-the-art methods, W-Gates also achieves superior performance. [ABSTRACT FROM AUTHOR]

Grover’s search algorithm allows a quantum adversary to find a $k$ k -bit secret key of a block cipher by making O($2^{k/2}$ 2 k / 2 ) block cipher queries. Resistance of a block cipher to such an attack is evaluated by quantum resources required to implement Grover’s oracle for the target cipher. The quantum resources are typically estimated by the $\textit {T}$ T -depth of its circuit implementation and the number of qubits used by the circuit (width). Since the AES S-box is the only component which requires $\textit {T}$ T -gates in a quantum implementation of AES, recent research has put its focus on efficient implementation of the AES S-box. However, any efficient implementation with low $\textit {T}$ T -depth will not be practical in the real world without considering qubit consumption of the implementation. In this work, we propose three methods of trade-off between time and space for the quantum implementation of the AES S-box. In particular, one of our methods turns out to use the smallest number of qubits among the existing methods, significantly reducing its $\textit {T}$ T -depth. [ABSTRACT FROM AUTHOR]

In recent years, owing to important improvements, the applicability of supervisor synthesis has significantly increased. We discuss notable developments that were pivotal in the application of supervisor synthesis to large infrastructural systems. [ABSTRACT FROM AUTHOR]

True random number generators (TRNGs) based on ring oscillators are employed in many devices because they can be constructed with logic gates only. Random numbers generated by TRNGs are used for various cryptographic systems as session keys, nonces, and masks. The randomness of a TRNG is characterized by uniformity, nonreproducibility, and unpredictability. Moreover, the quality of random numbers affects cryptographic systems. In particular, degradation of the unpredictability can reduce the security of the cryptographic system because random numbers can be easily estimated. Side-channel attacks, which exploit additional information leaked from a cryptographic module to reveal secret information, are well known. If some additional information reflecting the output bit can be measured from electromagnetic (EM) emission as a side-channel leakage against a TRNG, the unpredictability of the TRNG may decrease. Accordingly, this article introduces the leakage model that reflects an output bit generated by a transition effect ring oscillator (TERO) based TRNG, and an attack that estimates random number bits by measuring EM emission from an integrated circuit against TERO-based TRNG. We propose a leakage model against a TERO-based TRNG and demonstrate that the output bits of the TRNG can be estimated by analyzing the radiated emissions. We also consider a countermeasure against the proposed attack. [ABSTRACT FROM AUTHOR]

In the mm-wave frequency band, the rectifier’s sensitivity is the bottleneck of a wireless-powered IoT transponder’s distance. At a meter’s distance, the received power is weak, and transistors in a front end of a wireless power receiver operate in the weak inversion region. This article presents a mathematical analysis of the mm-wave multi-stage rectifier in the low-power region. A design methodology of a 57–64-GHz fully integrated eight-stage rectifier with a bulk-drain connection in 40-nm CMOS technology is presented. Parasitic effects on a multi-stage rectifier are analyzed. Based on the analysis, an intrinsic threshold voltage modulation is applied to improve the sensitivity. A tree-type power splitter is also proposed for the RF power signal’s phase balance. With this method, the RF signal arrives at each stage with an equal phase, and its suppression at the output is improved by 16 dB. This mm-wave rectifier achieves −7.1-dBm input sensitivity at 57 GHz with 1-V dc output voltage. The overall sensitivity from 57 to 64 GHz is better than −4.5 dBm. Compared to other mm-wave silicon-based rectifier state of the arts, the proposed mm-wave rectifier achieves better sensitivity while maintaining a compact size. [ABSTRACT FROM AUTHOR]

Quantum algorithms can be described as quantum circuits and are supposed to be carried out on an ideal quantum device that is far from current ones. The current quantum devices have a significant limitation on the connectivity between quantum bits. In other words, a quantum bit is only allowed to interact with its nearest neighbors (NNs). In reality, quantum bits have to be placed on a grid, where the connectivity between quantum bits is predefined. The predefined connectivity of a grid further determines the possible range of architectures of a quantum device after the placement of quantum bits. In this article, we propose to place quantum bits based on a 2-D hexagonal architecture rather than a 2-D Cartesian architecture. To validate the effectiveness, we leverage a workflow for mapping NN compliant quantum circuits onto targeting grids, where the workflow consists of a global reordering strategy and a local reordering strategy. With the advantages of the hexagonal grid, the overhead of making quantum circuits NN compliant is reduced significantly compared with the Cartesian grid. We also provide a comprehensive set of ablation analyses to gain a better understanding of the contributions of the components within our workflow. According to the experimental results, when changing the grid type from Cartesian to hexagonal, the global reordering strategy is crucial for small quantum circuits. In contrast, the local reordering strategy is more important than the global reordering strategy for large quantum circuits. [ABSTRACT FROM AUTHOR]

Superconductive rapid single-flux quantum (RSFQ) is an emerging cryogenic technology, promising a significant boost in performance and ultralow power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS—single-flux Quantum (SFQ) Clock Tree Synthesis—is presented. QuCTS utilizes a two-stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1049 clock sinks in 53 min while satisfying the clock arrival time. [ABSTRACT FROM AUTHOR]

This letter presents a partial-bootstrap gate driver circuit for switching loss reduction and crosstalk mitigation. The proposed circuit is simple and no additional power supply or control is needed. The circuit structure and operating principles of the proposed gate driver are introduced. Three different operating modes of the proposed gate driver are presented. Finally, the experimental results are presented to validate the proposed gate driver. It is found that the proposed gate driver can greatly accelerate the switching process and reduce switching loss. The proposed gate driver can also generate a gradually decaying negative voltage during the turn-off process to suppress crosstalk. [ABSTRACT FROM AUTHOR]

This brief presents an analog multiplier based controller for a noninverting buck-boost (NIBB) converter, in which the controller can work for both buck and boost modes of the NIBB converter, thus simplifying the design and saving the power and area for the controller. Moreover, it can obtain good line regulation and load regulation performances. The analog multiplier based controller can automatically change over between the buck and boost modes according to the input and output voltages. This brief, fabricated in 65-nm CMOS process, exhibits a core area of ${1}.{67}{\times }{0}.{64}{mm}^{2}$. It outputs a stable 0.9 V when the input voltage changes from 0.7-1.4 V, with a maximum output load current of 200 mA. [ABSTRACT FROM AUTHOR]

The HfxZryO2 with high Zr content is demonstrated to form the anti-ferroelectric tetragonal phase (AFE t-phase). The peak dielectric constant (47) of Hf0.2Zr0.8O2 is achieved. By taking advantage of the high dielectric constant, the Hf0.2Zr0.8O2 is used in the gate stack on the high mobility Ge0.98Si0.02 channel to significantly enhance the drive current. Stacked two Ge0.98Si0.02 gate-all-around nanowires can have high ION per perimeter of $740~\mu \text{A}/\mu $ m at $\mathrm{V}_{\mathrm{OV}}= \mathrm{V}_{\mathrm{DS}}= 0.5\text{V}$. The thermal budget is as low as 450 °C. [ABSTRACT FROM AUTHOR]

Synaptic electronics based on three-terminal transistors can become a promising technology in the neuromorphic field. However, most synaptic transistors are composed of layer-by-layer structures and thin films. Due to the large power consumption and operating voltage, it is difficult to meet the current pursuit of low energy consumption devices. Herein, the artificial synapse behavior is demonstrated through a lithium-based electrolyte-gated transistor with a three-dimensional (3D) interface conduction channel for low-power synapse simulation. The device fabricated by the electrospinning process successfully simulates typical artificial synaptic characteristics under different stimulation intensities. The energy consumption of a single spike of a synaptic device can be as low as $\sim 1.25$ pJ. In addition, the device simulates behavior similar to the Ebbinghaus memory. This work provides a simple and effective reference for the fabrication of low-voltage artificial synaptic devices. [ABSTRACT FROM AUTHOR]

Recently, the main issue for developing the latest small pixels is maintaining the full-well capacity (FWC) while minimizing image lag as the pixel pitch is scaled down within the sub-micron scale. In this letter, the FWC and image lag characteristics are optimized by varying the photodiode (PD) doping profiles in $0.5~\mu \text{m}$ CMOS image sensors with vertical transfer gates (VTGs) for the first time. Measurements and simulated results of various pitch generations are correlated to propose the most desirable PD doping conditions for $0.5~\mu \text{m}$ pixels which have not been developed yet. As a result, the ceiling position of the top PD doping significantly affects the image lag characteristics resulting in the lowest image lag when increasing the ceiling by 30% from the initial position. In conclusion, a fruitful guideline for photodiode design in 3D active pixel sensors is provided for optimization of FWC and image lag in $0.5~\mu \text{m}$ pixel pitches. Also, this methodology associating potential curve analysis can be of potential use for development in ultra-small pixel pitches in the near future. [ABSTRACT FROM AUTHOR]

In this letter, fin-shape tri-gate $\beta $ -Ga2O3 lateral MESFETs are demonstrated with a high power figure of merit (PFOM) of 0.95 GW/cm2 – a record high for any $\beta $ -Ga2O3 transistor to date. A low-temperature un-doped buffer-channel stack design is developed which demonstrates record high Hall and drift electron mobilities in doped $\beta $ -Ga2O3 channels allowing for low ON resistances (RON) in $\beta $ -Ga2O3 MESFETs. Fin-widths (Wfin) were 1.2- $1.5~\mu \text{m}$ and there were 25 fins (Nfin) per device with a trench depth of $\sim ~1~\mu \text{m}$. A $\beta $ -Ga2O3 MESFET with a source-drain length of 6.4 $\mu \text{m}$ exhibits a high ON current (187 mA/mm), low RON ($20.5~\Omega $.mm) and a high average breakdown field (4.2 MV/cm). All devices show very low reverse leakage until catastrophic breakdown for breakdown voltages (VBR) scaling from 1.1kV to ~3kV. This work demonstrates the potential of channel engineering in improving $\beta $ -Ga2O3 device performance towards lower conduction losses for low-to-medium voltage applications. [ABSTRACT FROM AUTHOR]

Availability of a reliable ON-chip oscillator can secure a system-on-chip (SoC) against physical clock attacks by enabling applications such as boot-up using ON-chip oscillator and hardware clock monitors. This article proposes a frequency-error feedback (FEF) loop-based relaxation oscillator for such applications. It suppresses the low-frequency noise and improves the time interval error (TIE) without degrading the period jitter. It also stabilizes the oscillator against supply and temperature variations. A 77-MHz oscillator prototype is fabricated in a commercial 5-nm FinFET process. Operating from 0.9-V digital and 1.2-V analog supplies, the prototype consumes a total of 0.84 mW and occupies an area of 0.0152 mm 2. It achieves a TIE of 3 ns over 10 K cycles which is $3\times $ better than an oscillator without an FEF loop. Chip samples are picked from four wafer split lots. The worst case frequency variation measured from 16 samples is $\pm 0.25\%$ across an analog supply change of 1.1–1.35 V, while a variation of $\pm 0.3\%$ is measured over −40 to $125 ^\circ \text{C}$ temperature from eight samples. [ABSTRACT FROM AUTHOR]