92 results on '"Kikuno, T."'
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2. Balance and Proximity-Aware Skip Graph Construction.
3. Towards Automated Verification of Distributed Consensus Protocols.
4. Using the NuSMV Model Checker for Test Generation from Statecharts.
5. Model Checking a Modular-Structured Nonblocking Atomic Commitment Protocol for Asynchronous Distributed Systems.
6. Pairwise Testing in the Presence of Configuration Change Cost.
7. Detecting Feature Interactions in Home Appliance Networks.
8. Language and Tool Support for Model Checking of Fault-Tolerant Distributed Algorithms.
9. Fault-Prone Filtering: Detection of Fault-Prone Modules Using Spam Filtering Technique.
10. Constructing Overlay Networks with Low Link Costs and Short Paths.
11. On the effects of partial membership knowledge on reliability of gossip-based multicast.
12. Analysis of software test item generation - comparison between high skilled and low skilled engineers.
13. Evaluating semantic warnings in VoIP programmable services with open source environment.
14. Semantic warnings and feature interaction in Call Processing Language on Internet telephony.
15. A Bayesian belief network for assessing the likelihood of fault content.
16. Statistical analysis of time series data on the number of faults detected by software testing.
17. Elimination of crucial faults by a new selective testing method.
18. Detecting feature interactions in telecommunication services with a SAT solver.
19. On estimating testing effort needed to assure field quality in software development.
20. Deriving interaction-prone scenarios in feature interaction filtering with use case maps.
21. Development of session management mechanism for cellular phone with WWW connection.
22. Improving the testing process by program static analysis.
23. Automatic verification of fault tolerance using model checking.
24. An implementation of electronic shopping cart on the Web system using component-object technology.
25. A selective software testing method based on priorities assigned to functional modules.
26. On prediction of cost and duration for risky software projects based on risk questionnaire.
27. Fault-secure scheduling of arbitrary task graphs to multiprocessor systems.
28. Generating test items for checking illegal behaviors in software testing.
29. Intelligent scheduling based on start time adjustment for advanced sequential control systems.
30. A new model with time constraints for conformance testing of communication protocols.
31. Timed reachability analysis method for communication protocols with time intervals.
32. Fault analysis based on fault reporting in JSP software development.
33. Experimental evaluation of the cost effectiveness of software reviews.
34. On fault tolerance of reconfigurable arrays using spare processors.
35. Fault-tolerant attribute evaluation in distributed software environments.
36. Spare channel assignment for restoration in fault-tolerant loop network.
37. Minimum number of links needed for fault-tolerance in cluster-based network.
38. Reconfiguration algorithm for fault-tolerant arrays with minimum number of dangerous processors.
39. Experimental evaluation of software reliability growth models.
40. An approach to form creation based on AND/OR tree.
41. A routing protocol for finding two node-disjoint paths in computer networks.
42. Responsiveness evaluation of a class of communication protocols.
43. Efficient test sequence generation for localization of multiple faults in communication protocols.
44. A new approach to realizing fault-tolerant multiprocessor scheduling by exploiting implicit redundancy.
45. Automated synthesis of protocol specifications with message collisions and verification of timeliness.
46. A new heuristic algorithm based on GAs for multiprocessor scheduling with task duplication.
47. Heuristics for computing attribute values of C++ program complexity metrics.
48. Timed reachability analysis method for EFSM-based communication protocols and its experimental evaluation.
49. A new framework of measuring software development processes.
50. Measurement of glitches based on variable gate delay model using VHDL simulator.
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