Search

E-beam voltage contrast inspection is a very common method for in-line detection of many key defect types for rapid yield learning during technology development. Generally, the wafer surface is charged positive, but sometimes charging the wafer surface negative makes more sense. This paper reviews four advantages that negative charging may provide. Switching from positive to negative charging is typically achieved using landing energy and/or extraction voltage. A third control knob is introduced and demonstrated using three common inspection layers, contact chemical mechanical polish (CMP), 3D NAND wordline shorts and 3D NAND wordline opens. [ABSTRACT FROM AUTHOR]

Accurate segmentation of power lines in various aerial images is very important for UAV flight safety. The complex background and very thin structures of power lines, however, make it an inherently difficult task in computer vision. This paper presents PLGAN, a simple yet effective method based on generative adversarial networks, to segment power lines from aerial images with different backgrounds. Instead of directly using the adversarial networks to generate the segmentation, we take their certain decoding features and embed them into another semantic segmentation network by considering more context, geometry, and appearance information of power lines. We further exploit the appropriate form of the generated images for high-quality feature embedding and define a new loss function in the Hough-transform parameter space to enhance the segmentation of very thin power lines. Extensive experiments and comprehensive analysis demonstrate that our proposed PLGAN outperforms the prior state-of-the-art methods for semantic segmentation and line detection. [ABSTRACT FROM AUTHOR]

Infrared (IR) small dim target detection near the sea–sky line (SSL) is crucial for enhancing the early warning capability of maritime vehicles. However, the interferences caused by the strong contrast have not been properly addressed. Consequently, a specially designed algorithm regional-division local contrast measure (RDLCM) that focuses on the detection of IR small dim targets appearing near the SSL is proposed. First, an SSL detection module based on a lightweight convolutional neural network (CNN) is devised to achieve fast pixel-level SSL detection. Then, a set of regional-division windows (RDWs) are designed according to the strong grayscale contrast distribution around the SSL, and through the division of the effective regions, the RDWs could realize the potential extraction and refinement of the IR small dim targets that appear near the SSL. Experiments on three IR image sequences demonstrate that the proposed algorithm achieves the best detection accuracy among the classical and state-of-the-art algorithms in comparison and runs at 44 frames per second (FPS), which could meet real-time requirements. The code and dataset are available at RDLCM. [ABSTRACT FROM AUTHOR]

The electrostatics of two-dimensional (2D) lateral pn homojunctions considering the impact of electrostatic doping by means of two split bottom-gates are studied here. Analytical expressions are obtained from the solution of the 2D Poisson equation considering a depletion approximation. Straightforward analytical models for the electrostatic potential and the depletion width within both the dielectric and the 2D semiconductor are obtained for both the symmetrical and asymmetrical cases. In contrast to the case of devices with chemical doping, the obtained depletion width model of devices with electrostatic doping do not depend on the dielectric constant but only on the electrostatic potential and oxide thickness. The models describe the electrostatics of gate-tunable 2D pn junctions at arbitrary bias. A benchmark against numerical device simulations of MoS $_{2}$ -based pn junctions validate the analytical models. [ABSTRACT FROM AUTHOR]

In this work, an acoustic emission (AE) technique was applied to online condition monitoring (CM) of solder fatigue in a clip-bonding SiC mosfet power assembly during short and long power cycling tests (PCTs). Solder fatigue caused by PCTs was identified in the clip-bonding assembly via scanning acoustic tomography and scanning electron microscopy and successfully diagnosed via the AE-based online CM. By analyzing AE signals, junction temperature, and junction-to-case thermal resistance, it can be confirmed that the AE signal shows a superior sensitivity in initial fatigue diagnosis to the thermal or electrical signals. Meanwhile, two solder fatigue processes, cracking initiation and cracking acceleration, were identified based on the cumulative AE counts and AE energy during the long PCT. An abrupt increase in AE energy happened at the end stage of the long PCT due to a severe cracking process, which can be regarded as a prewarning of a failure point of the power assembly. In addition, the relationship between transitional thermal resistance and accumulative AE energy was investigated and shows a linear relationship. These results suggest that the AE technique can be a promising online CM approach to diagnose and predict solder fatigue in power assemblies during operation. [ABSTRACT FROM AUTHOR]

Tracking the myotendinous junction (MTJ) motion in consecutive ultrasound images is essential to assess muscle and tendon interaction and understand the mechanics’ muscle-tendon unit and its pathological conditions during motion. However, the inherent speckle noises and ambiguous boundaries deter the reliable identification of MTJ, thus restricting their usage in human motion analysis. This study advances a fully automatic displacement measurement method for MTJ using prior shape knowledge on the Y-shape MTJ, precluding the influence of irregular and complicated hyperechoic structures in muscular ultrasound images. Our proposed method first adopts the junction candidate points using a combined measure of Hessian matrix and phase congruency, followed by a hierarchical clustering technique to refine the candidates approximating the position of the MTJ. Then, based on the prior knowledge of Y-shape MTJ, we finally identify the best matching junction points according to intensity distributions and directions of their branches using multiscale Gaussian templates and a Kalman filter. We evaluated our proposed method using the ultrasound scans of the gastrocnemius from 8 young, healthy volunteers. Our results present more consistent with the manual method in the MTJ tracking method than existing optical flow tracking methods, suggesting its potential in facilitating muscle and tendon function examinations with in vivo ultrasound imaging. [ABSTRACT FROM AUTHOR]

Intensive use of photovoltaic (PV) inverter in the volt/var control (VVC) methods in active distribution networks can impair inverter reliability. This article proposes a PV inverter reliability-constrained (PiReCon-) VVC method with a power smoothing scheme under uncertainties. First, considering impacts on inverter reliability, new reliability constraints are developed with a power smoothing factor to constrict inverter apparent power variation. Second, a new VVC optimization model is proposed with the reliability constraints, which minimizes power losses by optimizing both inverter var output and PV curtailment. Uncertainties of PV generation and loads are fully considered and addressed via a stochastic optimization method. Third, this article develops a penalty convex-concave programming method to effectively tackle nonconvexity of the proposed optimization model. The proposed PiReCon-VVC method is tested on a 33-bus distribution network, and simulation results verify its high efficiency in both minimizing the power losses and enhancing the PV inverter reliability. [ABSTRACT FROM AUTHOR]

Junction temperature is the most important factor to induce the insulated gate bipolar transistor module failure and conduct operational management. In-situ calibrated method and junction temperature calculation model are proposed to timely indicate the junction temperature for the electric vehicle drive system. It aims to solve that the conventional calibration methods need to be calibrated in the temperature chamber and the model cannot meet variable current conditions, which ignores the effects of the stray parameters of electrode connection on the on-state voltage. A mathematical junction temperature estimation model based on the relationship between saturation voltage drop and different currents is established, whose accuracy depends on the prior narrow range junction temperature calibration. A control strategy for the in-situ calibration is proposed to generate an instantaneous large current by creating a zero-torque condition and using integrated negative temperature coefficient thermistors, current sensor, and on-state voltage measured circuit when the new-energy vehicle is in an idle state. Experimental results prove that the proposed in-situ calibration method can be realized totally inside the electric vehicle, which can serve the full-service lifetime of the electric vehicle with high precision. [ABSTRACT FROM AUTHOR]

Owing to the superior performances, silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfets) attract a lot of attention. To increase the power density, it is desired to use the third quadrant (3rd-quad) characteristics of the mosfet rather than the externally paralleled Schottky diode for freewheeling during the deadtime. It has been known that the 3rd-quad is far more than a body diode, and the MOS channel is also an important part of it. The channel may be not fully closed and, therefore, play a significant role in the reverse conduction even when the gate is zero or negatively biased. However, a comprehensive study of the 3rd-quad characteristics is still to be conducted. In this article, experiments and simulations are conducted and a physical model is developed to explain the 3rd-quad characteristics of the SiC mosfet. It reveals how and why the 3rd-quad characteristics are affected by the gate voltage and the junction temperature. This article is helpful for not only the application of SiC mosfet but also the device design. [ABSTRACT FROM AUTHOR]

Thermal management is a cost-effective means to improve the lifetime of power module, but it also brings negative influence to the converter. To alleviate the negative effect, this article proposes a strategy to design the reference junction temperature swing based on the distribution characteristics of consumed lifetime and the thermal control efficiency. We show that the selected reference temperature swing, including its type and amplitude, allows each application of thermal control to reduce as much consumed lifetime as possible and, at the same time, to guarantee the performance of the converter. Moreover, this approach does not need to obtain the junction temperature swing in real time, which makes the thermal management simple and efficient. The experimental results are presented to verify the merits of the proposed strategy. This article also evaluates the impact of uncertainties due to the semiconductor parameter variations and performs the error analysis of junction temperature estimation. [ABSTRACT FROM AUTHOR]

Temperature sensitive electrical parameters (TSEP) provide an indirect and noninvasive method for on-line junction temperature estimation of power semiconductor devices. It is known that the fundamental of TSEP-based methods is to calibrate the relationship between TSEP and junction temperature in advance. However, the calibration methods in the literature need to open the module, require pretesting, or record the operating data of a converter in the entire power rating range, which are inconvenient in field applications. This article proposes an on-line and noninvasive calibration method by measuring the data at three operating states that are already existed in the regular converter operation. It is achieved by measuring the accessible heatsink/case temperature and TSEP during converter regular operation. The concept, implementation, and error analysis of the proposed method are presented in this article. Experimental verification is given to prove the effectiveness, accuracy, and convenience of the proposed method. [ABSTRACT FROM AUTHOR]

This article investigates the effects of the average power variation and the ambient temperature on the behavioral modeling and predistortion of high-power amplifiers concurrently. The measurement results showed that in addition to the average power variation, the behavior of a high-power PA is a function of ambient temperature as well. This article proposes a novel smart digital predistortion (DPD) model that considers both average power variation and temperature (PTI-DPD). The PTI-DPD is implemented using artificial intelligence-based model and it benefits from sets of data formats containing the signal, its delayed versions, average power variation, and ambient temperature. The developed architecture provides an uninterrupted linearization across the ambient temperature and average power variation span without need for a continues feedback path or multiple models. A series of measurements have been conducted to study the PTI-DPD performance across the temperature and average power range. According to the results, the PTI-DPD achieves an average of −48.5 dBc adjacent channel power ratio across the average power and temperature span. [ABSTRACT FROM AUTHOR]

The current limiting function enables the solid-state circuit breaker (SSCB) to have proper protection coordination. It allows sustained overcurrent for a certain period while preventing the fast fault current increase in dc systems. For the conventional method of using switches alone to limit the current, the high loss results in a short withstand time and low current limiting capability of the SSCBs. In this letter, a control strategy is proposed to utilize the energy absorption component to handle the major part of the energy during the current limiting stage to increase the current limiting capability for series-connected SSCB switching cells. The proposed method is experimentally verified to have more than 3X current limiting withstand time compared to the conventional control strategy in a case study. [ABSTRACT FROM AUTHOR]

Junction temperature monitoring is the basis of high reliability operation for silicon carbide (SiC) devices, since thermal stress is the dominating aging factor. Conventional thermal sensitive electrical parameter methods have a poor monitoring performance for SiC Mosfets with low sensitivity. Thus, a high-sensitivity online junction temperature monitoring method is proposed based on the turn-on drain–source current overshoot. First, theoretical analysis is provided to clarify that the temperature difference between the body diode region and the on-state resistance region can be ignored in SiC Mosfets. It is an important basis for the proposed method, which is proven by an isothermal experiment. It is the first time to discover that the turn-on current overshoot (ΔiCm) of SiC Mosfets consists of both the reverse recovery current (iRR) and the intrinsic current overshoot (Δi0m). Next, a novel Tj monitoring strategy for SiC Mosfets is proposed based on comprehensive utilization of iRRm, Δi0m and ΔiCm. Finally, the effectiveness of the proposed method is verified by online experiments based on a dc–dc converter. The proposed method is more accurate than conventional TSEP methods with a high sensitivity of 20 mA/°C. Moreover, it still has a high monitoring performance when boundary conditions change. [ABSTRACT FROM AUTHOR]

Pulsed readout of Direct Current (DC) Superconducting Quantum Interference Device (SQUID) is crucial for experiments which need to be performed at millikelvin temperatures, such as the readout of superconducting and electron spin based qubits. Pulsed readout algorithms used in these experiments are usually specific to the experimental setup and require some optimization. We present a circuit that emulates the behavior of a DC-SQUID in order to allow the development and evaluation of pulsed readout algorithms at room temperature without the need of a running dilution refrigerator. This novel circuit also constitutes a low cost device which can be used to teach the principles of a DC-SQUID in courses aimed at training the next generation of quantum engineers. [ABSTRACT FROM AUTHOR]

This article studies the influence of fiber Bragg grating (FBG) head length on insulated gate bipolar transistor (IGBT) direct on-chip thermal sensing performance of FBG sensors. To this end, the surface of a commercial IGBT chip is thermally simulated and experimentally characterized. Uniform FBG sensors with three head sizes are then tested in two promising thermal sensing locations. The study has found that the large thermal gradients in this application create an additional constraint when using longer head lengths. A distortion in the reflected spectrum of the 5-mm FBG sensor is used to illustrate the underlying physical effect, which causes this limitation for IGBT junction temperature measurement. This additionally affects the length of head sizes providing accurate temperature readings of the IGBT surface hotspots, and significantly, this limit is location-dependent in a given IGBT geometry. [ABSTRACT FROM AUTHOR]

Excellent high-temperature performance (298–523 K) of the 4H-SiC n-p-n bipolar phototransistor detector (PTD) was explored. It was fabricated using the 4H-SiC epitaxial wafer grown by high-temperature chemical vapor deposition (HTCVD). The static and dynamic properties of the device were tested and analyzed. The results show that the device still has an optical gain of up to 103, a wide linear response range, and good repeatability at the high temperatures up to 523 K under a 3-V bias with a wavelength of 360 nm. The temperature coefficient of the optical gain is extracted, the value of which is 1.02/K. Although the response time of the device increases with the temperature, the increased percentage in responsivity is significantly greater than that of the response time. The results provide an important experimental reference for the application of high-temperature detection and suggest that the PTD has the potential to be used in ultraviolet (UV) detecting systems at high temperatures. [ABSTRACT FROM AUTHOR]

The goal of molecular optimization is to generate molecules similar to a target molecule but with better chemical properties. Deep generative models have shown great success in molecule optimization. However, due to the iterative local generation process of deep generative models, the resulting molecules can significantly deviate from the input in molecular similarity and size, leading to poor chemical properties. The key issue here is that the existing deep generative models restrict their attention on substructure-level generation without considering the entire molecule as a whole. To address this challenge, we propose Molecule-Level Reward functions (MOLER) to encourage (1) the input and the generated molecule to be similar, and to ensure (2) the generated molecule has a similar size to the input. The proposed method can be combined with various deep generative models. Policy gradient technique is introduced to optimize reward-based objectives with small computational overhead. Empirical studies show that MOLER achieves up to 20.2% relative improvement in success rate over the best baseline method on several properties, including QED, DRD2 and LogP. [ABSTRACT FROM AUTHOR]

LED lighting still suffers from its thermal problem linked mainly to the increase in junction temperature. The situation becomes more and more aggravated when it comes to decorative lighting. Indeed, this type of lighting application sometimes requires that the heat sink of the LED lamp be integrated into a narrow space, such as false or sloped ceilings, which limits the transfer of heat to the outside. In this article, the current study reports a numerical analysis of natural convection heat transfer around rectangular heat sink for LEDs lighting applications. The radiator is put in an inclined cavity with an orientation angle varying from 0° to 60°. The effects of the enclosure inclination and its length on thermal behavior, flow structure in the cavity as well as on optical properties of the light source were highlighted. The CFD simulation showed a significant effect on the heat transfer rate when varying the cavity length (presented as an aspect ratio A) and its orientation. A = 4 was determined as an optimal cavity aspect ratio, and it was found that higher orientations are more sensitive to the increase of the length of the cavity. For θ = 60°, the luminous efficiency is ameliorated by about 10% when increasing the cavity length from one to four. Accordingly, we proposed correlations in simple form to predict the heat transfer rate for different configurations studied. [ABSTRACT FROM AUTHOR]

The impact of ring-shaped collector contact (RCC) on total ionizing dose (TID) susceptibility of 40-V vertical n-p-n bipolar transistors is investigated. The 60Co $\gamma $ -ray irradiation experiment shows that the devices with RCC suffer less current gain degradation than their counterparts with conventional collector contact structure, which is independent of the emitter area and bias condition during irradiation. Technology computer-aided design (TCAD) simulation results indicate that the enhancement in radiation tolerance of the RCC devices should be attributed to the mitigation of trap-assisted carrier recombination at the Si/SiO2 interfaces near emitter–base (EB) junction rather than the concentration or distribution variations of radiation-induced traps. Moreover, the mitigation of carrier recombination in RCC devices could result from the creation of new current flow paths that suppress the diffusion of injected electrons toward the trap-enriched Si/SiO2 interfaces. [ABSTRACT FROM AUTHOR]

In this article, the influence of thermal coupling in power modules on lifetime under power cycling test (PCT) is investigated. In a full-bridge power module for electric vehicle application, the thermal coupling is strong due to high power density and causes lateral temperature difference. In PCT, at the same maximum junction temperature Tvjmax and temperature swing ΔTvj, the influence of thermal coupling on lifetime and failure mode is investigated. The root cause of why thermal coupling influences lifetime and the failure mode is discussed by finite-element analysis. Transient thermal impedance is used to calibrate the simulation model. The Influence of thermal coupling on chip surface and solder layer temperature distribution is analyzed under the same test conditions. Furthermore, two parameters are extracted from the temperature distribution of chip surface as flags of failure mode determination. Finally, taking thermal coupling into account, combined with direct copper bonding structure, an improved layout is recommended in terms of lifetime. [ABSTRACT FROM AUTHOR]

In this article, an electrothermal model of a diode–insulated gate bipolar transistor switch for modeling dc–dc converters is proposed. The formulated model has the form of a subcircuit for the simulation program with integrated circuits emphasis (SPICE) program and enables computations of both electrical characteristics of the converter and junction temperatures of the semiconductor devices. The equations used in the formulated model allow modeling the operation of the converter in both continuous conduction mode and discontinuous conduction mode. The correctness of the formulated model is experimentally verified for the boost converter. Good accuracy of modeling the characteristics of the converter is obtained. A.cir file based on the formulated model for an analysis in the SPICE program is attached to the article as the active content. [ABSTRACT FROM AUTHOR]

A quantum phase slip junction (QPSJ) based direct inverter gate is proposed in this article for the first time. The proposed inverter is simpler than the QPSJ-based inverter designed indirectly by using a two-input xor gate with specific input conditions. In the indirect inverter, one of the two inputs of the xor gate must be set to the clock pulse in order to perform the true inverter operation. However, the proposed direct inverter has only one input to which the input voltage can be applied directly, and therefore, it has a simpler structure with fewer elements that occupies less area on the chip. The true operation of the proposed inverter is verified by feeding its input with the standard pseudorandom binary sequence 3 and connecting its output to the next gate to test its ability for driving the next gate. [ABSTRACT FROM AUTHOR]

The uncertainties of charging behavior of electric vehicle (EV) owners have a negative impact on the loss of life (LOL) of distribution transformer. This article proposes a decentralized EV charging framework for optimization of the LOL of distribution transformer considering the dissatisfactions of EV owners. Specifically, long-short-term memory (LSTM) neural network is first utilized to capture the uncertainties caused by the load demand and electricity price. After that, each EV is modeled as an intelligent agent and a multiagent deep reinforcement learning approach is applied to solve the coordinated charging problem based on the forecasting information by the LSTM network. All the agents are trained in a centralized manner to develop coordinated control strategies while informing decisions based on local information when finishing the training process. The proposed approach can achieve coordinated charging management of EVs based on local information, which helps preserve the privacy of EV owners, reduce the cost induced by the deployment of communication devices, and avoid single-point failure. In addition, the parameter space noise and deep dense architecture in reinforcement learning are introduced to overcome premature convergence, training instability, and inefficiency due to the large action space of multiagent scenario. Comparative tests are carried out among several benchmarks utilizing real-world data to illustrate the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

A GaN on engineered bulk silicon (GaN-on-EBUS) power IC platform featuring an industry-standard 200-V GaN power HEMT epi-structure has been recently demonstrated, showing effective isolation and crosstalk suppression between the high-side (HS) and low-side (LS) GaN transistors in half-bridge configuration. In this work, we scale up the vertical breakdown voltage (BV) of the GaN film on the EBUS substrate to be over 600 V. Meanwhile, the built-in back-to-back PN junctions along the trench created in the Si substrate are employed to provide an overvoltage-protection scheme through their intrinsic avalanche capability for the overlaying GaN half-bridge circuit. [ABSTRACT FROM AUTHOR]

In this work, we demonstrated capacitor-less 4F2 2-terminal InGaAs npn junction DRAM through careful device design. Using epitaxially grown InGaAs which have a steep junction, fabricated InGaAs bistable resistor (biristor) DRAM showed low voltage operation (~2 V), fast switching speed (<20 ns), long-term retention (103 s at 85 °C), and high endurance (>1010 cycles) with a high sensing margin. Considering this feasibility study, we believe that InGaAs $\text{n}^{+}$ pn+ junction DRAM could be a good technological option for future scalable 3D DRAM. [ABSTRACT FROM AUTHOR]

High-speed, high-photoresponse, low-dark current photodetectors with monolithic integration compatibility on a single silicon chip have a vital role in fast optical communication. Schottky barrier junctions provide ultrahigh frequency bandwidth, which makes them suitable for a high-speed data rate optical transition system. In this article, we proposed the novel design of a fast silicon Schottky photodiode (SPD) with reduced dark current and enhanced photocurrent to produce an acceptable photo-to-dark current ratio. A differential Schottky diode is used in series with the designed SPD to reduce the final dark current delivered to the next signal conditioner electronics. A periodic plasmonic array is applied on the metallic Schottky contact layer to localize the illuminated light in the depletion region of Schottky contact and increase light absorption, which results in enhanced photocurrent. The simulation of the device shows a photo-to-dark current ratio of ${2.7} \times {10}^{{4}}$ at room temperature and 1-V biasing voltage, which is much greater than the reported data. Moreover, the design results in a complementary metal–oxide–semiconductor (CMOS)-compatible photodiode (PD) with 28-time reduced dark current and 3.3-time photocurrent enhancement with an ultrafast impulse response of 3 ps and a response time of about 18 ps that are attractive for ultra-fast data communication applications in 850-nm region. [ABSTRACT FROM AUTHOR]

An efficient lightweight modeling method was examined to analyze the shielding characteristics of large-scale models such as real-world buildings, and the findings were verified based on the relevant standards. In general, electromagnetic threats with high energy can cause severe damage by causing malfunctioning and system failure of electronic systems. To protect electronic systems, the shielding characteristics of the building in which the systems are located must be clarified. Extensive research has been conducted on the shielding characteristics of building materials and reinforced concrete. However, only a few researchers have adopted a simulation-based approach to analyze and verify the shielding characteristics of actual-scale reinforced concrete buildings up to the gigahertz (GHz) band. Therefore, in this study, a lightweight 3-D modeling method was used to analyze large-scale models such as buildings up to the GHz band. The shielding characteristics of the building were determined using the proposed approach, and the results were compared and verified against measurement data using feature selective validation. Furthermore, the proposed method was used to analyze the shielding characteristics of a reinforced concrete building pertaining to the transmission and reflection characteristics of reinforced concrete walls. [ABSTRACT FROM AUTHOR]

High junction temperature is usually the main factor leading to device failures in high-power working conditions, such as surges or avalanches. It is of great significance to obtain the junction temperature quickly and accurately. Direct measurement of junction temperature is inconvenient, and usually indirect electrical measurement combined with model calculation is used. An electrothermal coupling junction temperature calculation model with distributed heat sources is proposed in this article. This model can accurately and quickly predict the device behavior during the surge process, as well as the voltage drop and temperature changes of each part of the device, without actually performing surge tests. This article describes the theoretical basis and calculation principles of the model. By taking a commercial SiC merged PiN Schottky diode as an example, this article also explains the details of the establishment of the electrical and thermal characteristic models of the device, as well as the calculation steps of the junction temperature by the thermal coupling model. The calculated device voltage drop curve of the device is in good agreement with the measured ones, and the calculated junction temperature curve is more consistent with the device failure mechanism than the one by the traditional RC thermal circuit model. [ABSTRACT FROM AUTHOR]

Global and local multitrace formulations (MTFs) provide a flexible and efficient method for the modeling of scattering and transmission of time harmonic electromagnetic (EM) waves by composite structures. This contribution extends the domain of applicability of global MTFs to cases where penetrable domains, perfectly conducting domain, and perfectly conducting thin sheets are all part of the design. A novel and easy to implement resonance-free equation to model scattering by perfect conductors is introduced. A Calderón preconditioner designed to limit the number of iterations required for the solution of the discrete system is designed and studied. The accuracy, flexibility, and efficiency of the method are demonstrated on a representative range of examples. [ABSTRACT FROM AUTHOR]

We report an avalanche-mode light-emitting transistor (AMLET) in silicon (Si), based on a lateral bipolar junction, which emits light near 760 nm optical wavelength with a record low bandwidth of 38 nm. The AMLET, designed in a CMOS-compatible silicon-on-insulator (SOI) photonics platform, is optically confined within a $0.21 ~\mu \text{m}$ thick SOI layer, which forms a Fabry-Pérot (FP) resonator perpendicular to the Si surface. Light is emitted from the reverse biased emitter-base junction via phonon-assisted hot carrier recombination and, additionally, minority carriers are injected via the forward-biased Base-Collector junction. The combination of injection from collector terminal through a narrow base and FP optical resonance, yields a high optical power efficiency of $4.3\times 10^{-6}$ at ${V}_{\text {BC}}=0.8$ V and ${V}_{\text {EB}}=10$ V. Our work opens new possibilities in spectral-engineering of Si light-emitters, which could boost performance of all-Si optical interconnects and sensors. [ABSTRACT FROM AUTHOR]

This letter demonstrates a novel HEMT controlled ultraviolet light emitter by directly modifying the drain of AlGaN/GaN HEMTs. The selective epitaxial growth (SEG) p-GaN on HEMTs contacts with two dimensional electron gas (2DEG) to form a lateral p-GaN/2DEG junction, which utilizes the recombination of holes in p-GaN and high-density electrons in 2DEG to realize luminescence. Our results show that the ultraviolet light with a maximum intensity of 374.9 nm is emitted by the new devices, which is also able to realize color conversion by driving quantum dots (QDs). The new method shows an idea of converting electrical devices into light-emitting devices, which is different from the traditional integration. This work represents the first light emitting HEMT without integrated LEDs. [ABSTRACT FROM AUTHOR]

Motion planning at urban intersections that accounts for the situation context, handles occlusions, and deals with measurement and prediction uncertainty is a major challenge on the way to urban automated driving. In this work, we address this challenge with a sampling-based optimization approach. For this, we formulate an optimal control problem that optimizes for low risk and high passenger comfort. The risk is calculated on the basis of the perception information and the respective uncertainty using a risk model. The risk model combines set-based methods and probabilistic approaches. Thus, the approach provides safety guarantees in a probabilistic sense, while for a vanishing risk, the formal safety guarantees of the set-based methods are inherited. By exploring all available behavior options, our approach solves decision making and longitudinal trajectory planning in one step. The available behavior options are provided by a formal representation of the situation context, which is also used to reduce calculation efforts. Occlusions are resolved using the external perception of infrastructure-mounted sensors. Yet, instead of merging external and ego perception with track-to-track fusion, the information is used in parallel. The motion planning scheme is validated through real-world experiments. [ABSTRACT FROM AUTHOR]

Single-photon avalanche diodes (SPADs) are widely used for weak light detection due to their high gain and high sensitivity. Unfortunately, SPAD devices have random telegraph signal (RTS) noise during the avalanche transition phase, which makes circuit design more difficult. Therefore, the modeling of RTS noise in SPAD devices is of great significance for the design of signal processing circuits. However, RTS noise is not included in the traditional equivalent circuit model. In response to the above problems, this paper implements an equivalent circuit model with RTS noise based on the Cadence. The model is built based on the basic components in the library, and it has strong application universality. The model is validated in a novel embedded photogate SPAD device (EP-SPAD). It accurately simulates the RTS noise and IV characteristics of the EP-SPAD device. In addition, the threshold voltage of EP-SPAD device operating in Geiger mode is precisely defined based on the characteristics of RTS noise. When the reverse bias voltage is increased from 0 V to 15 V, the IV characteristics of the model are consistent with the EP-SPAD device. [ABSTRACT FROM AUTHOR]

Vertical power devices require significant attention to their edge termination designs to obtain higher breakdown voltages without substantial increase in ON-state resistance. A simple edge termination structure for a GaN p-n diode is proposed, comprising a full layer lightly doped p-type GaN region underneath the higher doped ${p} +\!+$ contact layer. A TCAD model of the device is developed, and removal of the portions of ${p}$ ++ cap outside of the device active area in simulations is shown to increase the device blocking voltage capability. It causes the depletion width to increase in the lightly doped p-type layer and allows it to act similar to a junction termination extension (JTE). These predictions are validated empirically, resulting in a 52% measured increase in breakdown capability after selective removal of the ${p}$ ++ cap. This simple edge termination technique can be formed with only a single low-energy nitrogen implant or etching procedure, greatly increasing its manufacturability over more complex structures. Design optimization studies are pursued in TCAD to determine optimal parameter values for further improving breakdown performance. It is shown that the proposed edge termination technique can be employed to produce future high voltage vertical GaN devices without a significant gain in ON-state resistance and with wide tolerance to process variations. [ABSTRACT FROM AUTHOR]

This article presents a wide-spectral response single photon avalanche diode (SPAD) designed and fabricated in advanced 55-nm CMOS image sensor technology. SPADs with different active areas and doping profiles are simulated by Sentaurus-TCAD to optimize their electrical and optical performances. A global well-sharing technique is employed to deliver a pixel pitch of $16.4 ~\mu \text{m}$ and a fill factor of 50.96% for a device with a $6 ~\mu \text{m}$ radius. The proposed structure is based on a p+/deep n-well (DNW) multiplication junction, extending its spectral response as much as possible. Compared to the existing BSI SPADs, a triple protection method is innovatively used to suppress premature edge breakdown and to reduce the dark count rate (DCR) through a combination of a virtual retrograde DNW, p-well guard ring, and a poly gate ring located above the shallow trench isolation. Furthermore, deep trench isolation is employed to suppress crosstalk. Samples of different radii from 2 to $6 ~\mu \text{m}$ are manufactured. The SPADs exhibit a low DCR below 20 cps/ $\mu \text{m}$ 2 at room temperature and with a 2-V excess bias. The peak photon detection probability is 20.3% at 660 nm and is maintained at a high value, more than 10%, in the spectral range of 550–820 nm. [ABSTRACT FROM AUTHOR]

A silicon single-photon avalanche diode (Si-SPAD) with a deep multiplication zone was fabricated using 0.11- $\mu \text{m}$ -CMOS technology. Deep n-well (DNW) implantation with three energy levels was performed to prepare a deep junction, and the highest breakdown voltage (${V}_{\text {BR}}$) and lowest dark count rate (DCR) were obtained at the highest DNW implantation energy. In addition, devices with different structures were manufactured: a shallow junction, deep junction with mask DNW, deep junction with mask DNW without shallow trench isolation (STI), and deep junction with blank DNW. The blank DNW structure exhibited a lower edge breakdown risk and less deviation between samples compared to those of mask DNW structure in terms of the ${V}_{\text {BR}}$ and DCR. Moreover, a new edge breakdown risk was observed between DNW and p-well (PW) in the DNW blank structure, which could be alleviated by adjusting the PW sizes. According to the measurement results, the STI structure was preferable in terms of fill factor. Measurements were obtained from real fabricated test device structures, and technology computer-aided design (TCAD) for various factors associated with Si-SPADs with deep multiplication structures was performed. [ABSTRACT FROM AUTHOR]

A first principle analysis of Fe/MgO/Fe magnetic tunnel junction (MTJ) having gate voltage over insulated barrier region (MgO) is presented. Because of different work functions of gate and barrier materials, transfer of density of states (DOS) in forbidden energy gap of MgO is found above Fermi energy due to Schottky effect. It is reported that diffused DOS allows high tunneling of majority channel current because of less interference of ${\Delta _{{1}}}$ symmetry of Bloch states with evanescent states in barrier. It shows high spin injection efficiency 0.9928, 0.9959, and 0.9871 with tunnel magneto resistance (TMR) ratios 1743.30%, 1450.06%, and 572.62% at gate voltages 1–3 V, respectively, with left and right electrodes at 0.5 V. Present work gives a basis for using MTJs as three terminal devices in magnetic random access memory (MRAM) applications. [ABSTRACT FROM AUTHOR]

This article presents the coupled electrothermal simulation results of single event burnout (SEB) in power diode with field limiting rings termination structure. Two different hardening techniques of low carrier lifetime control and introducing the buffer layer are investigated comparatively in both the radiation tolerance improvement and the electrical performance degradation. Our simulations reveal that a significant reduction in the carrier lifetime is needed for the hardening of the power diode using only the carrier lifetime control method. However, the sharp increases in the forward voltage drop and the leakage current at the lower carrier lifetime make this hardening technique unacceptable. On the contrary, the addition of the buffer layer is able to improve the safe operating area under the heavy ion irradiation even up to the breakdown voltage, while the breakdown characteristics and the leakage current are kept unchanged and the increases in the forward voltage drop and the reverse recovery charge can be well controlled. In conclusion, adding a buffer layer is considered a superior and promising hardening technique. [ABSTRACT FROM AUTHOR]

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2\times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions. [ABSTRACT FROM AUTHOR]

The corrugated p-base (CB) structure has been acknowledged as an effective method to improve the maximum controllable current (MCC) of asymmetric integrated gate-commutated thyristor (IGCT), but never clarified in symmetrical devices such as reverse blocking IGCT (RB-IGCT). This study focuses on the influence of the CB structure on the MCC and the failure mechanism of RB-IGCT. First of all, by employing the CB structure in the RB-IGCT samples, it is verified that the CB structure can improve MCC of the symmetrical devices by more than 50%, no matter under high or low dc-link voltages. Moreover, regarding the scenario under the high dc-link voltage, the effect of the CB structure on the dynamic avalanche is analyzed via simulation, and the improvement of MCC and the positive trend of MCC upon temperature are further clarified. As to the scenario under the low dc-link voltage, distinct failure phenomenon and negative temperature dependence of MCC are observed evidentially on the symmetric devices with CB structure. To explain these failure characteristics that are conflicting with the well-acknowledged dynamic avalanche failure, a novel failure mode named cathode retrigger failure is proposed in this study. It is believed that this study not only deciphers the fundamental mechanisms of the CB structure in RB-IGCT, but also provides practical strategy to optimize the symmetric IGCT devices. [ABSTRACT FROM AUTHOR]

A high-efficiency ${D}$ -band monolithically integrated GaN frequency doubler based on a pair of antiseries four-anode planar GaN Schottky barrier diodes (SBDs) has been successfully fabricated. Unlike the traditional hybrid integrated circuit technology, the monolithic integrated circuit technology has been used in the design and fabrication of GaN SBD-based frequency doubler circuits to achieve good alignment and low conversion losses. At room temperature, the experiments show that the peak conversion efficiency reaches 17.0% at 115.6 GHz under a continuous wave (CW) driving which is a critical requirement for many practical applications. The efficiency of 17.0% is the highest efficiency of GaN SBD-based multipliers at present under CW driving mode. This monolithically integrated doubler also exhibits a broadband high efficiency characteristic of more than 4.7% (−5.58 dB from 17%) across a 10% band from 109 to 121 GHz. In addition, high CW power handling capability of the proposed frequency doubler is verified. The experiments show that the frequency doubler can endure a maximum CW input power of 0.5 W. [ABSTRACT FROM AUTHOR]

In the design process of power electronics converters, the power semiconductors thermal modeling is one of the most critical tasks. An accurate estimation of the junction temperature allows the validation of the converter design and also the calibration of the thermal models during prototyping. Therefore, this article presents a straightforward method to estimate the junction temperature directly on the target converter using a plug-in measurement system. The estimation is based on the IGBT on-state voltage measurement under high current with a dedicated sensing circuitry externally connected to the converter under test. This solution is specifically designed to fulfill the needs during the prototyping process and design validation since allows a fast and reliable monitoring in all working conditions of interest and the sensing circuitry does not affect the normal operation of the converter under test (CUT). The acquisition circuitry and the calibration procedure are described and tested on a 68-kVA IGBT industrial three-phase inverter. The experimental results obtained on the target inverter prove that the proposed design validation based on the implemented estimation of the junction temperature provides better results than the conventional design methods based on thermal models implemented in simulators. [ABSTRACT FROM AUTHOR]

The insulated-gate bipolar transistor (IGBT) is characterized by metal-oxide-silicon (MOS)-gating, high current density, and high blocking capabilities. The trench field-stop reverse-conducting IGBT (TFR-IGBT) is distinguished from conventional IGBT (CON-IGBT) by trench MOS gate, field-stop layer, and collector-short structure. As a composite structure made of MOS and bipolar junction transistors (BJTs), TFR-IGBT is susceptible to displacement damage (DD). This work reports the DD effects on TFR-IGBT with the fast neutron fluence up to a fluence of 1013 cm−2. The transfer, forward conductive, and forward blocking characteristics are degraded subsequent to neutron exposures. The suppression of the hump current in the transfer curve is observed by neutron-induced damage. This article proposes, from a device physics perspective, the mechanism behind the characteristics degradation from DD in TFR-IGBT. The dependencies of the key parameters on neutron fluence are analytically modeled. Our models provide a good fit to the experimental data of the IGP20N65H5 TFR-IGBT subjected to fission neutrons. [ABSTRACT FROM AUTHOR]

Aiming at the temperature rise and thermal control issues of power devices in H-bridge converters under conventional pulsewidth modulation (PWM) methods, a novel PWM method of H-bridge converter with temperature rise balancing and minimization based on periodically alternating employment of power devices is proposed. In the proposed method, two novel operation mechanisms of power devices are alternately applied into the eight regions with the identical and opposite polarities of reference voltage and input current, which are composed of two fundamental frequency periods. All active switches and antiparallel diodes in H-bridge converters are made to work alternately in these eight regions, each of them is designed to keep in on-state in one region, operate in switching state in another two regions, and inactive in the left other five regions. This way, the power dissipation and temperature rise of all the devices are balanced and minimized, and H-bridge converters no longer suffer from the dead-time effect on current quality and dc-bus voltage utilization. The implementation strategy of the proposed modulation method is discussed in detail. Simulation and experimental results are presented that verify the effectiveness of the proposed method and the corresponding implementation strategy at different operating points. [ABSTRACT FROM AUTHOR]

An optimized concept of the Cold-Electron Bolometer (CEB) with Superconductor-Insulator-Normal (SIN) Tunnel Junction and Andreev SN contact for voltage-bias mode has been developed. The responsivity of this design is much better than the widespread concept of the CEB with two SIN tunnel junctions for the current-biased mode (SINIS structure) due to degradation of responsivity by a factor of two in voltage-bias (VB) mode. Besides that, for the realization of the CEB with the same capacitance, we need twice larger junctions that lead to four times larger area and volume of the absorber. As a result, the NEP of one SIN junction CEB is half that of two SIN junction CEB. A novel concept of the quasiparticle cascade amplifier (QCA) based on harvesting the waste energy of relaxed quasiparticles without any additional voltage bias has been developed. The distinguish feature of the cascade principle is utilizing the same dc voltage as used for CEB. The cascade principle of signal amplification proved to be possible due to the conversion of electrons to holes in the second absorber. The amplifier is based on the optimized CEB with one SIN junction and one SN contact. The coefficient of power amplification of the incoming signal to the potential energy of hot quasiparticles is huge and can achieve a level of 140 at the optimal bias point. The coefficient of power amplification of the QCA can reach a value of 30 and more to overcome the noise of the SQUID amplifier. For a power load of 6 pW, the total NEP of the CEB is decreased to the level of photon noise NEP, down to 0.7*NEPphot. [ABSTRACT FROM AUTHOR]

A type of multilayer microstrip diplexer with highly- selective wideband filtering channels is reported. Its closely-spaced fourth-order passbands are attributed to two circuit parts: (i) two third-order quasi-elliptic-type microstrip-to-microstrip wideband vertical transitions and (ii) a shunt two-stub dual-band bandpass filter (BPF) junction printed on the top layer. The two microstrip vertical transitions are developed by means of open-/short-circuit-ended microstrip lines and slotline stepped-impedance resonators (SIRs), respectively, and they correspond to the constituent lower and upper channels. The shunt dual-band BPF junction produces one additional transmission pole and one more pair of close-to-passband transmission zeros (TZs) for each channel to further increase their filtering selectivity. The RF theoretical foundations and design procedure of the engineered broadband diplexer are detailed. For practical-validation purposes, a proof-of-concept prototype of two-layer fourth-order microstrip wideband diplexer is simulated, manufactured, and tested. Its measured lower and upper channels has two closely-spaced sharp-rejection passbands with center frequencies of 1.496 GHz and 2.759 GHz and 3-dB fractional bandwidths of 62.83% and 24.83%, respectively, while featuring power-isolation levels above 27.39 dB from 0.5 to 4 GHz. [ABSTRACT FROM AUTHOR]

In this letter, a 1.2kV optically-controlled SiC transistor (OCT) is proposed and fabricated. A pin diode is monolithically integrated with the SiC OCT for reverse conducting and online junction temperature measurement capability. Field limiting rings are designed as terminal structure for forward blocking capability. The test results indicated that, besides full optical control and high blocking voltage performances, the fabricated transistor chip was also capable of reverse conducting and online junction temperature measurement. The forward breakdown voltage of the transistor was about 1400V and the leakage current at 1200V was ${2.5}\,\,\times \,\,{10}\,\,^{-{8}}\text{A}$. The reverse turn-on voltage was about 2.6V, while the temperature sensitivity of the integrated diode was 2.99mV/K at 5mA. Under 365nm ultraviolet (UV) light with 300mW/cm2 incident intensity, the forward current of the OCT chip was $203.2\mu \text{A}$ at 0.3V, which is about ${1.2}\,\,\times \,\,{10}\,\,^{{5}}$ times the corresponding dark current. The transient characteristic was tested at a 600V bias voltage in a resistive load circuit and the results indicate that the OCT can be switched using a 365nm UV light emitting diode. [ABSTRACT FROM AUTHOR]

Multi-channel GaN power device, consisting of stacking multiple two-dimensional-electron-gas (2DEG) channels, has been demonstrated to achieve unprecedented on-state performance while maintaining high breakdown voltage (${V}_{BR}$). However, the large carrier density (${N}_{s}$) makes it more challenging to achieve high positive threshold voltages (${V}_{TH}$) on multi-channel epitaxies. In this work, we demonstrate enhancement-mode (e-mode) multi-channel GaN transistors based on conformally deposited p-type LiNiO over tri-gates to form a multi-channel junction gate structure. Compared to the normal MOS gate, the p-type LiNiO junction gate provides an additional depletion of the channels to yield a more positive ${V}_{TH}$ , reaching a maximum ${V}_{TH}$ of 1.2 V (defined at $1 ~\mu \text{A}$ /mm). Moreover, high-quality LiNiO provided excellent on-state performance in multi-channel tri-gate devices with a stable operation at high temperature, which present small ${V}_{TH}$ shift and hysteresis, and low off-state leakage current. The e-mode devices in this work presented a small specific ${R}_{ON}$ (${R}_{ON, sp}$) of 0.62 $\text{m}\Omega \cdot $ cm−2 along with a hard breakdown voltage (${V}_{BR}$) of 920 V. This work demonstrates the potential of LiNiO for high-performance e-mode power devices. [ABSTRACT FROM AUTHOR]

With a switching drain bias, the gate reliability of Schottky-type ${p}$ -GaN gate high-electron-mobility transistors (HEMTs) under AC positive gate bias stress has been systematically investigated. The mean-time-to-failure (MTTF) under such application-relevant stress is found to be prolonged compared to that extracted from static and AC gate bias stress tests with the absence of a switching drain bias and exhibits positive coefficients with frequency and OFF-state drain bias (${V} _{\text {DSQ}}$). Such results can be explained by the drain-induced hole insufficiency in the gate stack at large ${V} _{\text {DSQ}}$ , a physical mechanism that results in elevated energy band at ON-state when ${V} _{\text {DSQ}}$ is just switched to low voltage. This non-equilibrium transient status could suppress injection of electrons from the 2DEG channel to the ${p}$ -GaN gate, which in turn substantially weakens the hot-electron’s generation in the depleted ${p}$ -GaN layer and the subsequent bombardment to the gate-metal/ ${p}$ -GaN interface, and thus prolongs the gate lifetime. [ABSTRACT FROM AUTHOR]