11 results on '"Jullian S"'
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2. Integration of multi-level self-aligned CoWP barrier compatible with high performance BEOL
3. MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances.
4. Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOS.
5. High performance 40 nm nMOSFETs with HfO2 gate dielectric and polysilicon damascene gate.
6. Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOS
7. 0.248μm/sup 2/ and 0.334μm/sup 2/ conventional bulk 6T-SRAM bit -cells for 45nm node low cost - general purpose applications
8. High performance 40 nm nMOSFETs with HfO/sub 2/ gate dielectric and polysilicon damascene gate
9. Highly performant double gate MOSFET realized with SON process
10. MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances
11. A conventional 45mn CMOS node low-cost platform for general purpose and low power applications
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