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In this paper, we put forward an energy-efficient configurable asynchronous SNN accelerator for energy-constrained applications, which includes 256 neurons and 131K synapses with 8-bit fixed point weight. To achieve high energy efficiency and on-chip learning ability, we propose a sparse target propagation (S-TP) algorithm and design the accelerator with Click-based bundled-data asynchronous circuits. The SNN accelerator is implemented in 28nm CMOS process, and the post place and router (post-PAR) simulation results indicate that the SNN accelerator achieves on-chip learning with inference power efficiency of 3.97 pJ/SOP and 95.7% classification accuracy on NMNIST test dataset, which outperforms prior neuromorphic on-chip learning systems.

Biological neural networks are connected in a highly recurrent manner, which displays complex activity patterns spontaneously upon an awareness stimulus. Here, we emulate such a network based on a recurrently connected memristor array. To generate a target function, a first-order and controlled error (FORCE) learning rule that only needs to modify a small fraction of connections is introduced. This rule tries to minimize the amount of modification and thus is especially suitable for memristor-based synapses. After learning, the network could spontaneously generate the desired function after a random stimulus, just as the biological systems do.

In this work, a multi-functional self-rectifying memristor (Pt/TiO x /Ti) is fabricated. The device shows convertible volatile and non-volatile resistive switching. More importantly, the device has a high rectifying ratio in both switching modes (~105 for volatile and 106 for non-volatile), which is favorable for high-density 3D vertical integration. The convertible multi-switching behaviors and high self-rectifying ratio in a single memristor provide the flexibility for multi-functional applications in a large-scale array.

SNNs with temporal coding (TC), inspired by the human visual system, have a powerful ability to enable fast and low-power neuromorphic computing. Memristive devices show excellent performance on emulating spiking neurons and synapses in hardware. However, the neuron circuits used for implementing a fully memristive TC SNN are absent. In this work, for the first time, we demonstrate a LIF neuron based on a NbO x device to meet the requirements for the hardware implementation of TC SNNs. The neuron fires at most one spike within an inference window, and its spiking latency inverse to the input current intensity. Using such a neuron, we further experimentally demonstrated a fully memristive TC SNN (256 × 5) to recognize the Olivetti face patterns. Attributing to the one-spike scheme, the TC SNN achieves a sparser spiking number (~ 72 × reductions), faster inference speed (> 1.5 × improvement), lower power (~ 53 × reductions) than what happens in rate-coding SNNs.

In this paper, we put forward an asynchronous spiking neural network (SNN) accelerator with 1024 neurons and 1 million synapses, which is reconfigurable in terms of network connection and neuron parameters. Bundled data asynchronous circuits are adopted to design the neuromorphic computation core and mesh network. Multicast communication is used to transmit packet among and within each core for less packet transmission and better energy efficiency. A novel time step update mechanism, which updates neurons in an event-driven manner without considering the chip-wide activity of other unrelated neurons, is proposed to improve the performance of speed. The SNN accelerator is verified by classifying MNIST handwritten digit with Xilinx VC707 FPGA. The results show that the accelerator achieves 98% accuracy with MINST database, and more than 1 GIPS/W energy efficiency which is 32 times better than previous work.

At present, the neuromorphic hardware with analog neuron is widely studied by researchers. Address event representation (AER) is an event protocol, which usually used for inter-chip communication between neuromorphic chips. Fixed priority arbiter often results in unfair allocation of bus resource to only the high priority neuron, thus introducing fixed noise in the neural network. In this paper, we propose an asynchronous AER circuits with rotation priority tree arbiter to alleviate this issue. Moreover, to match the different delay between AER's handshake signal and neuron's handshake signal, a special handshake circuits is designed. Simulation results show that the 64 channels AER circuits can perform up to 143M event/s. The design is designed with SMIC180 process for fabricating RRAM based neuromorphic chip.

Address event representation (AER) is an event-based protocol, which usually used in inter-chip communication between neuromorphic chips and image sensors to transmit pulses. Generally, fixed priority is adopted in AER for multiple-pulse input channels, which leads to unfairness among channels, and even serious timing error and performance loss when there is pulse collision. In this paper, we proposed an AER circuit with rotation priority which changes the priority of each channel after every transmission. The simulation results show that our rotation priority method has distributed the timing errors to all channels and guaranteed fair priority for each channel. Moreover, this circuit is designed with Link-Joint model which brings clear structure, easy design process, and flexibility towards variety application.

We report a fully CMOS compatible bilayer, forming-free and non-filamentary memristive device with excellent bidirectional analog switching behavior as artificial synapse for neuromorphic computing applications. The bilayer stack structure, consisting of 8 nm TaO x formed via oxidation process on Ta bottom electrode and 7 nm Al 2 O 3 via atom layer deposition (ALD), is sandwiched between the Ta bottom electrode and Pd top electrode. The Pd/Al 2 O 3 /TaO x /Ta device shows bidirectional analog resistive switching behaviors, and multilevel conductance states (>60) with satisfying retention time can be obtained. Long term plasticity, consisting of long-term potentiation (LTP) and long-term depression (LTD), have been demonstrated based our device. And a nearly linear conductance change behavior is obtained by optimizing the training scheme: adopting non-identical training pulses.Atwo-layer perceptron neural networkwas performed to estimate the synapse characteristics of our devices. More than 94% recognition accuracy of MNIST handwritten digit dataset are achieved. Based on these results, the device is a promising emulator for biology synapse, and has a great potential to be used in neuromorphic systems.

The model of a novel drug delivery device of gastrointestinal microcapsule in a gas pressure driving way is proposed. The model experiments have been carried out to investigate into the main factors impacting on the performance of capsule, such as ultrasonic frequency, the relationship between the quantity and reaction time of the selected reactants, the relationship between the carried drug capacity and releasing drug time; and the optimal parameters of the capsule model are recommended on the basis of experimental results. Finally, the capsule structure of the model is proved being safe through strength analysis by ANSYS. Index Terms — Drug delivery; capsule; ultrasonic cavitation; chemical reaction

The function and the progress of site-specific delivery capsule system is presented. The model of a novel drug delivery device of gastrointestinal microcapsule in a gas pressure driving way is proposed, in which a new triggered control technique based on the principle of ultrasonic cavitation is used for inducing chemical reaction that brings gas pressure to drive gastroenteric drug delivery. The microcapsule can be used as a human drug absorption experiment tool. Index Terms — Drug delivery; capsule; ultrasonic cavitation; chemical reaction