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Creep properties of Sn, Sn-1.8Ag and their (100), (001) grain orientation were investigated by nanoindentation method, which could simulate the situation where solder joints suffered from stress. Also, the constant strain rate test was conducted to acquire hardness data in the steady state. The result shows that stress exponent (n) of Sn is 11.1 in (100) and 5.8 in (001); n of Sn-1.8Ag is 12 in (100) and 6.5 in (001). Increase of n represents that the content of Ag would greatly enhance the creep resistance in Sn matrix. Moreover, data of Sn (100) grain exhibit lower stain rate than (001) grain in the low stress region, which could indicate Sn (100) grain is more beneficial to be used in electronic package. As a result, combination of Ag addition and Sn (100) plane attached on the substrate would have better mechanical properties and prolong the creep life of solder joints.

The worldwide first 100MHz dynamic oxide semiconductor RAM (DOSRAM) is successfully demonstrated using a new high-mobility crystalline In-Ga-Zn-O (IGZO) material. The new IGZO exhibits around two times carrier mobility of conventional IGZO, while still achieving an extremely low off-state leakage (I off ) at ∼10−21A (zA) level. Attributed to DOSRAM performance improvement, 100MHz normally-off (Noff) CPU is successfully demonstrated with drastically reduced power consumption (∼94% power reduction for ARM Cortex-M0 and ∼70% power reduction for memory), making it a promising candidate for IoT application. In addition, an OS-FPGA is successfully fabricated by integration of 65nm SiFET and 60nm oxide semiconductor FET (OSFET) with an operation frequency of 360MHz. The application of the OSFET in analog circuits will also be discussed in this paper.

We report significant improvement of the TiSi / p-SiGe contact resistance by using a cryogenic (cold) boron implantation technique inside the contact trench of FinFET devices, providing both a source of dopants and a localized amorphization of the source/drain, self-aligned on the contact trench. A record low p-type contact resistivity of 5.9×10−9 ohm-cm2 is demonstrated and a 7.5% performance improvement is achieved. The variation of the implant temperature demonstrates a further improvement of the contact resistance when going to cryogenic (cold) implantation (−100 °C). Using TCAD, we demonstrate that the reduced implant temperature provides a higher degree of amorphization and reduces defects. This is the key to provide an enhanced recrystallization of the doped amorphized region through Solid Phase Epitaxial Regrowth (SPER) low temperature activation. We propose in this paper a novel mechanism for p-type contacts, and demonstrate it for the first time on state-of-the-art FinFET p-type devices using cryogenic (cold) implants and SPER regrowth.

Low-power embedded memory and an ARM Cortex-M0 core that operate at 30 MHz were fabricated in combination with a 60-nm c-axis aligned crystalline indium-gallium-zinc oxide FET and a 65-nm Si CMOS. The embedded memory adopted a structure in which oxide semiconductor-based 1T1C cells are stacked on Si sense amplifiers. This memory achieved a standby power of 3 nW while retaining data and an active power of 11.7 µW/MHz by making each bitline as short as each sense amplifier. The M0 core adopted the flip-flop in which an oxide semiconductor-based 3T1C cell is stacked on the Si scan flip-flop cell without area overhead and achieved a standby power of 6 nW while retaining data. The combination of the embedded memory and the M0 core provided high-performance, low-power Internet of Things devices operating with a broad range of active standby power ratios.

For 3D IC application, The thickness of micro joint is basically smaller than that in the conventional joint. IMCs can easily occupy micro joints during assembling or operation and then dominate the properties of micro joint. It is predicted that IMCs are going to be utilized as structural materials in near submicron-scale micro joint in these few years. The micromechanical behavior of IMCs is the important criterion to evaluate the suitability of IMCs as structural material in micro joints. In this study, the micromechanical behaviors of single crystalline IMCs generally formed in micro joints was conducted by micropillar compression. The failure mode of single-crystalline Cu6Sn5 and Ni3Sn4 are cleavage, however, the in-situ images and cross-section view showed that both Cu6Sn5 and Ni3Sn4 still preformed plastic deformation before failure, however, both Cu6Sn5 and Ni3Sn4 somehow plastically deformed through slip along the certain crystallographic direction on certain crystallographic planes. Most importantly, Ni3Sn4 can withstand a large amount of plastic deformation strain by compression which is more than 4 % in certain orientation. In comparison of these two IMCs, Ni3Sn4 showed the better mechanical performance including yield strength, strain to yield, failure strength, strain to failure and Young's modulus than Cu6Sn5. Thus, Ni3Sn4 has higher toughness and should be more promising to use as structure materials of 3D IC micro joints.

This paper presents a comparative study of three multi-function three-phase inverters, which include three-phase three-wire full-bridge (FB) inverter, three-phase four-wire half-bridge (HB) inverter and neutral-point-clamped (NPC) inverter. Each inverter is controlled by the division-summation (D-Σ) digital control and the control law for each inverter is derived in short. The comparison among these inverters is based on the criteria of common-mode voltage (CMV) issue for a PV system, component stress/count, efficiency, application and control complexity. Moreover, operation in both grid-connection and rectification modes are considered in the comparison. Experimental results measured from the inverters are included for performance evaluation.

An enterprise resource planning (ERP) system is the backbone in an e-business framework and is a process-oriented business management paradigm. An implementation of an ERP system can achieve “real-time” and “integration”. The staffs with manipulation skills of an ERP system are thus demanded for enterprises. E-learning are increasingly widespread by using information and telecommunication technologies. Therefore, this study develops a Moodle-based e-learning framework, consisting of a Moodle learning management system with a mobile learning (m-learning) solution and Web 2.0 applications (such as Wiki), and a proposed planning template of an e-learning content development for manipulation skill training of an ERP system. This study exhibits an implementation demo of the proposed framework, and indicating that (1) the used Moodle LMS can support e-learning and m-learning well, (2) an e-learning content (HTML5 format) created by the proposed template can be easily delivered to a Web and mobile devices. In future work, this study will integrate the proposed framework with a flipped classroom approach for ERP courses in a University. A statistical questionnaire analysis method will be performed to verify that the proposed framework can efficiently acquire the manipulation skills of an ERP system for learners.

The control of gate height uniformity, especially within-die gate height uniformity, and metal gate surface properties of 14nm technology node replacement metal gate (RMG) chemical mechanical polishing is important for 14nm high-k metal gate (HKMG) process. Good within-die uniformity would benefit for the following Tungsten etching back process(WEB) to have a uniform within-die etching depth, and proper post CMP Tungsten gate surface properties would generate a thinner Tungsten oxide surface to reduce WEB process loading. This study demonstrated the possibility of Tungsten gate CMP(WGCMP) to obtain good within-die gate height uniformity by selection of slurry and proper Tungsten gate surface by post buffing step CMP treatment. Due to high hardness of Tungsten, hardness of polishing pad and abrasive of slurry selection should be not a gap for micro scratch improvement, what the performance focus would put on within-die uniformity and post CMP Tungsten surface properties. In this study, the first result showed the control of erosion was important for within-die gate height uniformity. The criteria of slurry selection for WGCMP were higher Tungsten removal rate and lower oxide removal rate which especially resulted in lower pattern density area of erosion. And the second result showed Chemical-A polish time of post-Tungsten buffing CMP would dominate the Tungsten surface properties and influence WEB behavior.

For 3D IC application, solder volume in micro joint is much smaller than in the conventional joint. IMCs can easily occupied micro joints and dominate the properties of micro joint. Thus, it is anticipated that IMCs are to be used as structural materials in commercial scale in a few years. However, mechanical property data for reliability modelling are lacking. To characterize mechanical properties of IMCs becomes an urgent issue. In this study, we investigated the micromechanical behaviors of single crystalline IMCs generally formed in micro joints. Testing structures were produced by focused ion beam machining and subsequently tested by picoindenter in SEM which can simultaneously observe the sequence of failure of test structure. Our results are helpful on understanding the fracture modelling of IMCs.

Optimization of halo profile for advanced MOSFET device is important to control device short channel effect as well as device leakage. Multiple halo implants, such as mixture of Indium and boron to tailor the halo formation, have been used widely for n-FET devices. Amid its AMU and solubility, Gallium has a potential for better halo activation than Indium and reduced lateral straggling than boron. Therefore, Gallium could be a promising specie for device improvement through 1) halo optimization in planar devices, or 2) ground plane for retrograde well for better FinFET leakage characteristics. In this paper, Gallium is used to replace high scattering P dopant (HS-P) halo for SRAM or HS-P cluster halo for core NFET using a poly-SiON 28nm process with bare wafers and device splits. Secondary Ion Mass Spectroscopy (SIMS) was employed for dopant profiles for as-implanted and after thermal process. It is shown that when replacing HS-P or HS-P cluster halo by Gallium an excessive device shift is observed. The overlap capacitance indicates that overlap lateral diffusion regions are significant different with Gallium halo than established process flow. The paper will discuss potential underlying physical mechanisms.

Pre-amorphization implantation (PAI) of various energy and dosage are used on Ni-Silicide formation, which has achieved amorphism-like NiSi films. The electric characteristic, physical morphology and metallurgical of the NiSi were identified by sheet resistance, grazing incident X-ray diffraction (GIXRD), and selected-area electron diffraction (SAD) analysis. Result shows that lower energy and higher dosage of ion implantation can get amorphism-like NiSi film.

Optimization of halo profile for advanced MOSFET device is known to be very critical and challenging. Halo profiles around channel can cause carrier mobility degradation, leakage and higher Vt mismatch. Indium and high scattering P-type dopant (HS-P) mixed halo formation have been used widely for n-FET devices. Gallium has a better activation than Indium and is heavier specie than HS-P. Gallium could be promising specie for device improvement through halo optimization in planar devices or ground plane/retrograde well for better FinFET leakage characteristics. In this paper, Gallium is used to replace Indium halo on bare and device wafers using a poly-SiON 28nm process. Secondary Ion Mass Spectroscopy (SIMS) was employed for dopant profiles after anneals. Device gain in drive current with better Drain Induced Barrier Lowering or DIBL by 12mV was observed when Gallium replaced Indium in the HS-P/Indium mixed halo. The observed excessive device shift when Gallium was used to replace HS-P halo will be discussed in a future study. Ga for halo formation is not an plug/play and the interaction among the co-implant and dopant through implant induced damage should be investigated in the integration flow.

This paper studies how boron thermal diffusion in SiGe heterostructure are influenced by different source drain extension high-energy fluorine implant after SiGe thermal process for advanced HKMG SRAM device. Different fluorine profiles may introduce different fluorine concentration along Si/SiGe interface and result in fluorine interstitial cluster at different SiGe positions after SiGe 700°C thermal process. Blanket wafer secondary ion mass spectroscopy (SIMS) profiles were compared for different implant schemes and transmission electron microscopy (TEM) micrographs to establish the conditions under which F high energy implant suppresses B diffusion and cause breakthough dislocation at the bottom of SiGe. By tuning F co-implant from high energy into low energy, the breakthrough dislocations at the bottom of SiGe can be eliminated due to less clusters were formed. From real HKMG SRAM p-MOSFET device learning, better junction leakage improvement was found by Flow energy co-implant due to the elimination of cluster-induced dislocations. Ion/Ioff performance enhancement can also be found by suppresing boron transient enhanced diffusion (TED) from in-situ boron doped SiGe. Possible germanium concentration change inside SiGe with different boron diffusion mechanism by different fluorine co-implants may also influence the strain inside SiGe heterostructure and result in electrical device performance.

Polycrystalline silicon has attracted our interest for their applications. Its electrical characteristics are closely correlated to the crystalline structure after electrical activation. The parameters related to crystalline structure are strongly influenced by implant and annealing techniques. We investigate the influence and sensitivity of implant / annealing / microstructure / mobility on sheet resistance (Rs) of doped polysilicon film, which is prepared by a CVD reactor and implanted by various germanium and boron conditions. We also combine with RTP/LSA sequences to active and recrystallize polysilicon. Finally, fitting results of XRD is used to calculate grain size which shows strong correlation with Rs. We study on using implant/annealing process to modulate polysilicon Rs and its grain size. Different dopant species and annealing techniques were discussed its influence on these parameters. Data shows that Rs is inverse on grain size and it can be adjusted by process conditions to meet device requirement.

In this work, we compared the decouple plasma nitridation (DPN) and post nitridation anneal (PNA) processes for equivalent oxide thickness (EOT) scaling of ALD hafnium zirconate (HfZrO2) gate dielectric. Detailed physical, optical and MOSCAP electrical characteristics of HfZrON film were studied. It is found that DPN power parameter tuning could yield a more densified HfZrO2/SiO2 gate stack as compared to DPN pressure and PNA temperature process capability. Higher PNA temperature will cause the nitrogen tail diffuses throughout the HfZrO2/SiO2 gate stack and moves into the SiO2/Si substrate interface, more defects are shown in the SiO2/Si interfacial sub-band gap.

The reflective spectrum and the incident angle effects of double-layers AR-coating and Sub-Wavelength AR-coating on the triple-junction GaAs Solar Cell are characterized by short-circuit current (I sc ), open-circuit voltage (V oc ), and conversion efficiency (η).

The defectivity control of replacement metal gate (RMG) chemical mechanical polishing was important for high-k metal gate (HKMG) process. Micro-scratches of RMG CMP easily caused shorting or open of devices. In this study, the micro-scratch reduction of aluminum chemical mechanical polishing (AlCMP) has been investigated to provide solutions for preventing the formation of micro-scratches. Micro-scratches can be reduced by implementing soft pads at platen 2 and platen 3, pad cleaning chemical, and optimized post cleaning condition. Soft pads can reduce micro-scratch levels of AlCMP process, especially at platen 2. However, AlCMP with soft pads easily suffer serious dishing or erosion. Therefore, the balance between micro-scratches and dishing or erosion was crucial for pad selection of AlCMP. Besides, removal of pad stain was also important. Pad stain removed by pad cleaning chemical could get a lower micro-scratch level of AlCMP. In addition to polishing process, post cleaning process was a source of micro-scratch for AlCMP. An unsuitable post cleaning condition caused a counter effect of micro-scratch reduction.

Advanced junction scaling with device performance gain, leakage reduction and reduced threshold voltage (Vth) variation are critical for CMOS 28nm node and future scaling. In this paper, implant induced defect engineering for higher drive current with reduced SRAM defectivity, advanced junction formation and Vth mismatch (Vtmin) on a state-of-the-art 28nm logic flow are demonstrated and discussed.

In this work, we investigate the influence of incorporation Zirconia (ZrO 2 ) in gate dielectric HfO 2 on electrical properties and the reliability of nMOSFET for the 28nm technology node. Detailed film physical, chemical and optical properties of Hf 1−x Zr x O 2 as a function of Zr content were studied using HRTEM, AR-XPS, spectroscopic ellipsometer. Compared to HfO 2 , Hf 1−x Zr x O 2 provides lower C-V hysteresis, V t shift (ΔV t ) and higher Time to Failure (TTF) lifetimes are achieved with Zr incorporation in an ALD Hf 1−x Zr x O 2 /SiO2 gate stack. The improved reliability of the Hf 1−x Zr x O 2 gate dielectric is attributed to the reduced charge trapping in the Hf 1−x Zr x O 2 gate dielectric caused by the Zr incorporation.

In this paper, we have demonstrated that cryogenic implantation applied to source and drain (SD) extension, pocket/halo and SD formation offers advantages for higher core and SRAM driving current and one order lower Ioff bulk (Ioffb) leakage in NMOS with reduced SRAM defectivity. Atomistic Kinetic Monte Carlo (KMC) modeling confirms that the cryo-implantation has enabled a unique control of active Boron and point defect distribution in the channel/halo region of NMOS.

High-K/Metal-Gate (HK/MG) reliability TDDB and BTI are investigated systematically for the first time through HfZrO x gate stack engineering. To meet reliability requirements, it is shown that the HK film thickness, the position and concentration of a Zr dopant, utilizing post deposition anneal (PDA), and decoupled plasma nitridation (DPN) are important factors.

Strain techniques have been adopted and widely used in the advanced nodes since early 65nm for carrier mobility improvement. For PMOS, eSiGe incorporation in the SD is the process of choice to induce compressive strain in the channel for mobility improvement. To further lower the contact resistance, it is preferred to boost Boron concentration for pSD formed by eSiGe process. Normal implant process could lead strain relaxation caused by implant damage. In this paper, cryo-implantation technology is applied and characterization of strain relaxation is conducted using a state-of-the-art 28nm CMOS process flow. Experimental results indicate strain relaxation can be reduced with cryo implants relative to the room temperature implants. This study clearly showed that cryo-implantion reduced damage formation resulting in junction leakage reduction.

The fundamental film properties and microstructures of the different aluminum (Al) metal layers are evaluated to fabricate a replacement metal gate (RMG) device for the high-k metal gate (HKMG) application at 28nm node. A PVD Al fill-in metal deposition process, called one step hot Al (HAL), was found the resistivity increases with increasing the thickness of the Ti wetting layer. The higher pinhole density with the preferred (111) crystal orientation in the HAL layers indicate the film properties with lower reflectivity, higher resistivity and lower removal rate of the Al chemical mechanical polishing (AlCMP). In contrast, the other PVD Al deposition approach, called two steps cold hot Al (CHAL), was identified to possess lower resistivity and higher reflectivity without pinhole structures than the HAL. The smaller grain sizes with the preferred (220) orientation in the CHAL could effectively prevent the formation of pinhole and enhance the removal rate of the AlCMP. The non-uniform with crystallized TiAl3 phase detected in the bottom of the as-deposited HAL and CHAL films could obviously impact the removal rate of the AlCMP. An optimized CHAL fill-in metal deposition process with a larger than 40A Ti wetting layer are needed to simultaneously meet the process requirements of the Al gapfill and AlCMP planarization for achieving a reliable RMG structures.

The gyrotron, an ideal millimeter or terahertz source, requires mode converter. The mode converter is used to launch the desired wave to interact with the electron beam (e.g. traveling-wave amplifier) or to extract a wave power from the interaction region (e.g. backward-wave oscillator). A poor mode-converter, however, excites unwanted modes resulting in severe mode competition. In the previous study, Computer Numerical Control (CNC) lathe was employed. However, the machining error leads to a low yield rate at sub-terahertz region, which significantly hinders the progress of high-power terahertz gyrotrons. In this work, X-ray micro-machining (LIGA technique) is explored. LIGA technique is capable of fabricating devices with high precision, high aspect ratio, and low surface roughness. The prototype of the mode converter, TE 02 (190–220 GHz), is ready for the cold test.

We investigated molecular carbon (C 16 H 10 ) implant as a replacement for both a monomer carbon co-implant as well as a Ge pre-amorphization step for ultra-shallow junction (USJ) formation in a p-MOSFET SDE doping process in a 40nm logic device. Carbon is often used in the p-FET extension sequence because it reduces transient enhanced diffusion (TED) by trapping silicon interstitials. However, a Ge pre-amorphization implant (PAI) is still required because C is too light to self-amorphize under most conditions. The use of molecular carbon opens the possibility of eliminating the Ge PAI, which is known to leave residual end of range damage leading to junction leakage. As device scaling continues previously acceptable implant technologies for p-FET source/drain extensions (SDE) are struggling to meet advanced device requirements. We report device results showing that a single implant of C 16 H 10 can effectively replace a two step Ge + C implant sequence. We also studied the combination of C 16 H 10 , and B 18 H 22 at various energies, beam currents, and doses in terms of R s -X j under different advanced annealing schemes. We have also investigated the possibility of using a different molecular carbon (C 7 H 7 ) for n-MOSFET drive current enhancement through the formation of a Si:C stressor in the n-MOSFET source/drain (SD) region. Comparisons of XRD and Rs of the molecular carbon implanted samples from different process flow arrangements were made to identify the proper sequence of implants and anneals. Using a blanket wafer test, we demonstrated that molecular carbon implant produces a thick enough amorphous layer for high incorporation of carbon on the silicon lattice. The optimal location and distribution of high carbon concentration regions, which give the highest strain and least impact in SD Rs were determined. C 7 H 7 was implanted into the SD region of a 40nm logic n-MOSFET to verify the results from the blanket wafer test.

Magneto-transport measurements are performed on the AlGaAs/GaAs quantum Hall (QH) devices fabricated recently by our group. A series of Hall plateaus are observed with increasing the perpendicular magnetic field, and the mobility gaps resulting from localization effects are investigated at the minima in the longitudinal resistivity. Only the gap corresponding to the filling factor i = 2 is close to the expected cyclotron energy, and our study supports that the low-field QH conductors may suffer problems due to insufficient localization. The anomalous change on the Hall slope is observed when the i = 3 plateau is destroyed by the large current.

An evanescently-coupled-photodiode with partially p-doped photo-absorption layer was demonstrated and designed by a bandwidth simulation model to optimize its speed performance. Excellent performance of speed, saturation-power, and responsivity can be achieved simultaneously at 1.55 /spl mu/m wavelength.

The characteristics of galvanic corrosion in post-copper CMP cleaning are investigated. This type of corrosion occurs when CMP process completed, due to the heating lamp in SRD step. Particularly, it occurs only in device wafer, but not in structural test wafer. The corrosion behavior with light was identified. It occurs not only in integrated cleaner, but also in stand alone brush type cleaner. Copper lines were bridged after corrosion. The corrosion by-product can be removed by means of solvent cleaning. The mechanism and the prevention of this type of light-induced corrosion are reported in this paper.