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Smaller size and lower loss are always the target of EMI filter which suppresses EMI emitted by power electronics converter. Digital EMI filter (DEF) is the best solution to suppress the conducted EMI in size and loss, especially for high-power converters. However, for current DEF model, it is not enough to describe the filtering ability. The model which can describe DEF stability is absent. To cope with these, this paper proposes a modeling technique about filter and stable behavior of DEF system. In proposed technique, the insertion gain model can accurately describe the filtering behavior, and the loop gain model can predict the stability of DEF system. Experimental testbed based on a Boost converter as EMI interference is built. Experimental results validate that the proposed model can successfully predict the stability and performance of DEF system.

Ground-borne vibration in buildings is a growing problem in crowded cities due to the pressure to build ever closer to underground railway tunnels. Despite advances in numerical models for the prediction of ground-borne vibration, it is yet unclear how effective deep piled foundations are at mitigating the vibration transmitted into a building compared to shallow foundations, such as footings. The power-flow insertion gain is used as a measure of the building's overall vibration performance when piles, rather than footings, are included in the foundation. The tunnel-foundation system is based on the pipe-in-pipe model of a longitudinally invariant tunnel coupled to a boundary-element model of the foundation using an iterative wave-scattering approach. The initial theoretical study presented in this paper shows that piles generally attenuate the vibration levels in a benchmark building compared to footings. It is also shown how a simplified model for a tall building, based on a series of individual dashpots, can account for the modification of the foundation vibration field when the building is constructed.

This paper presents an analysis of a 8-12 GHz active 0.25 μm GaAs pHEMT MMIC circulator intended for integration into a phased array. The architecture is based on a closed-loop connection of three asymmetric -5.6-dB Lange couplers and resistive-feedback gain-matched amplifiers. The nominal simulated performance shows an isolation of 20 dB over a 40% bandwidth, with a return loss of better than 10 dB and an insertion gain of 2.4 dB across the band. The degradation in circuit performance is analyzed as a function of variations in port impedance. A loop-gain analysis demonstrates the circuit stability for port impedances in the VSWR = 2 circle, simulating coupling in a phased array. We show in simulation and measurements that the bandwidth, match on all ports and insertion gain are not sensitive and agree with simulations. However, the isolation degrades from 20 dB when the port impedances change within a VSWR=1.1 circle. Additionally, we show that the deviation of the coupler design from the nominal case affects the isolation. The statistical analysis gives insight into design criteria of this type of circulator for insertion into phased array.

This paper describes the design methodology and the On-Wafer (OW) measurement results of two broadband two stages MMIC High Power Amplifiers (HPAs) operating in the 8-12 GHz bandwidth. A Balanced HPA (BA-HPA) and a Single-Ended HPA (SE-HPA) are considered, they are fabricated on 150 nm HEMT Gallium Nitride on Silicon Carbide technology (AlGaN/GaN on SiC) called GH15 from UMS. The main aim of this realization was the achievement of a high Output Power associated with a very high Power Added Efficiency. To obtain a good compromise between output power and power added efficiency, a multi harmonic tuning approach of load and source impedances has been applied. In addition, particular attention was given to the way of drawing the matching network layouts to minimize the coupling effect between different elements.The On-Wafer measured power results under pulsed wave signal of the BA-HPA demonstrate a maximum output power (P OUT ) higher than 15 W (42 dBm) with 52% Power Added Efficiency (PAE) and 22 dB of insertion gain (G I ) in the 8-12 GHz bandwidth. Moreover, in the same previous bandwidth, the SE-HPA reaches a maximum P OUT equal to 43 dBm associated with54% PAE and 23 dB G I .To our knowledge, these results are one of the best in terms of PAE performances and frequency bandwidth trade-offs.

This paper presents the realization and characteristics of broadband plastic low cost packaged 5G High Power Frond-End (HPFE) operating in 24-31GHz bandwidth. This demonstrator includes a Transmit and Receive paths realized on mixed technologies: 150nm Gallium Nitride on Silicon Carbide (AlGaN/GaN on SiC) and 150nm Gallium Arsenide (GaAs). Continuous Wave (CW) measured power results of the Transmit path (Tx) demonstrates a maximum output power (P OUT, Tx ) higher than 2W (33.5dBm) with 24% power added efficiency (P AE), and 36dB of insertion gain (G I, Tx ) in the 24-31GHz bandwidth. The receiver path (Rx) presents an maximum output power (P OUT, Rx ) of 30mW (15.5dBm) and an average Noise Figure (NF) of 3.6dB with an associated Insertion Gain (G I, Rx ) of 20dB in the same bandwidth. The HPFE/Tx linearity has been investigated with several M-QAM modulation signals with 25/50 and 100MHz channel spacing and using Digital Pre-Distortion (DPD) leading to 48dBc Adjacent Channel Leakage Ratio (ACLR) and 40dB Mean Squared Error (MSE) for average output powers ranging from 17dBm to 25dBm. The linearity performances have been compared to the ones obtained with two other linear GaAs amplifiers (P A1 and P A2) dedicated to point to point telecommunications application: the HPFE presents similar linearity performances associated to a higher efficiency.

This paper presents the realization and characteristics of broadband plastic low cost packaged 5G High Power Frond-End (HPFE) operating in 24-31GHz bandwidth. This demonstrator includes a Transmit and Receive paths realized on mixed technologies: 150nm Gallium Nitride on Silicon Carbide (AlGaN/GaN on SiC) and 150nm Gallium Arsenide (GaAs).Continuous Wave (CW) measured power results of the Transmit path (Tx) demonstrates a maximum output power (P OUT,Tx ) higher than 2W (33.5dBm) with 25% drain efficiency (DE), 24% power added efficiency (PAE), and 36dB of insertion gain (G I,Tx ) in the 24-31GHz bandwidth. The receiver path (Rx) presents an maximum output power (P OUT,Rx ) of 30mW (15.5dBm) and an average Noise Figure (NF) of 3.6dB with an associated Insertion Gain (G I,Rx ) of 20dB in the same bandwidth.The HPFE/Tx linearity has been investigated with several M-QAM modulation signals with 25/50 and 100MHz channel spacing and using Digital Pre-Distortion (DPD) leading to 48dBc Adjacent Channel Leakage Ratio (ACLR) and 40dB Mean Squared Error (MSE) for average output powers ranging from 17dBm to 25dBm. The linearity performances have been compared to the ones obtained with two other linear GaAs amplifiers (PA1 and PA2) dedicated to point to point telecommunications application: the HPFE presents similar linearity performances associated to a higher efficiency.Thanks to the mixed technologies approach, an optimized trade-off in terms of integration, electrical performances and cost has been demonstrated.

A 36–40 GHz full 360° ultra-low phase error passive phase shifter with a novel phase compensation technique is presented in this paper. The proposed phase shifter consists of a four-way quadrature power divider as a vector generator, vector selector and two digital controlled artificial dielectric (DiCAD) phase shifter cells to achieve 4-bit (22.5° phase resolution) and full 360° synthesizing. DiCAD phase shifter cells not only provide 22.5° and 45° phase shifts but can also compensate the phase error due to its tuning mechanism. The measured RMS phase and gain error are under 2.6° and 2.6 dB over 36–40 GHz, respectively. The average insertion gain is about −20.2 dB with no dc consumption. Implemented in 90-nm CMOS, the chip size is 0.75 × 0.4 mm2 without pads. To the authors' knowledge, this phase shifter demonstrates the lowest RMS phase error among other reported millimeter-wave phase shifters.

This paper presents a 2-input and 3-output 0.35–1.5GHz switch cell with active balun. The proposed differential switch cell is composed of 8 differential series-shunt-series switches which improve the transmit efficiency of switch cell. Two wideband active baluns are used to compensate for the loss of passive switch cell which almost consumes no DC power. Fabricated by 0.18μm SiGe BiCMOS technology, the switch cell shows highest insertion gain of 9 dB and more than 40 dB isolation in working frequency band.

This paper presents a 6-bit active phase shifter in 0.13-μm SiGe BiCMOS technology for Ku-band phased arrays based on a phase interpolation technique. An input Marchand balun and a RC poly phase filter are used for high I/Q accuracy wideband quadrature generation with high linearity and an integrated current-mode DAC is used for controlling the amplitude of I/Q path signal to achieve 6-bit phase resolution. The phase shifter operates in the 12–18 GHz range. The simulation results show an rms phase error less than 2.61°. The average insertion gain ranges from −11.16 dB to −20.39 dB with an rms gain error less than 0.4 dB for 64 phase states. The phase shifter achieves an input P1dB of 9.98 dBm at 16 GHz for 0°-phase state. The core area of the phase shifter is 1.1×0.9 mm2, with a total current consumption of 13.4 mA from a 3.3 V supply voltage.

In this paper, a novel balanced amplifier antenna has been proposed for X-band. The antenna module consists of a microstrip fed ground slot excited cylindrical dielectric resonator (CDR). The unbalanced antenna output is converted into balanced outputs by a 180 degree rat-race hybrid which feed a differential low noise amplifier (LNA) consisting of two cascade stages. A marchand balun type biasing arrangement is employed for the differential LNA to increase common mode rejection ratio (CMRR). The differential LNA provides peak differential gain of 30 dB, CMRR of 16.8 dB and 12.6% 3 dB FBW. The insertion gain of the hybrid fed LNA is about 21 dB, 3 dB FBW is 8.4% and overall noise figure of the system is about 4 dB. The CDRA has peak gain of 5.47 dBi. The proposed design is suitable for modern receiver front-end applications requiring balanced outputs.

International audience; This paper presents the design, the realization and the power characteristics of plastic low cost packaged symmetric Doherty Power Amplifiers (DPA) operating in the 5.5-6.5GHz bandwidth. A single input (SI-DPA) and a dual input (DI-DPA) DPAs are proposed based on two power bars composed of two GaN HEMT cells (8 fingers of 275μm unit gate width). Input and output matching networks are designed on passive GaAs MMIC technology. To our knowledge, it is the first published SI and DI-DPAs working in C band, designed using Quasi-MMIC technology and assembled in plastic package. The measured power results under Continuous Wave (CW) signal of the SI-DPA demonstrate a maximum output power (Pout) upper than 20W (43.5dBm) with 50% drain efficiency (dE), 42% power added efficiency (PAE), 11dB of insertion gain (GI) in the 5.5-6.5GHz bandwidth. At 6dB output power Back-off (oBo), the drain efficiency is greater than 35% (32% PAE). The DPA linearity has been investigated with a 256QAM modulation signal of 30MHz bandwidth and using Digital Pre-Distortion (DPD) leading to a 50dBc Adjacent Channel Leakage Ratio (ACLR) at a 34 dBm average output power. The designed DI-DPA is identical to the SI-DPA without input power splitter. It demonstrates that the adjustment of power ratio between the main and the peak amplifiers associated with adequate bias points, improves all the power performances: linearity, PAE, oBo and GI. The DI-DPA reaches a 12.5 dB GI, a maximum Pout equal to 44dBm (3.5dB gain compression) with 45% PAE. Moreover, in the same previous bandwidth, 40% PAE with 4° of AM/PM variation are obtained at 6dBoBo and 36% PAE (AM/PM=3°) at 8dBoBo.

The paper introduces an adaptive gain algorithm in which the introduced gain is adaptive to noisy speech signal and frequency channels. The adaptive gain algorithm is a cascaded version of Signal-to-noise ratio based gain and insertion gain. In this paper two combinations of adaptive filtering and adaptive gain algorithms are put forward namely single channel cascaded NR scheme and multi channel cascaded NR scheme. The adaptive filter is implemented using either wiener or Kalman filter. Multi channel cascaded NR using Kalman filter shows consistent performance under all input and test conditions. Hence it can be considered as a practical solution for noise removal in monaural hearing aids.

International audience; Power Line Communications (PLC) is used for information exchange over the lines installed for delivering the electrical power. In-home PLC is a technology which delivers telecom services to every corner of a household through already existing electrical wiring. The in-home PLC channel offers multiple signal feed ports as, usually, it comprises of three wires: Phase, Neutral and Protective Earth. The measurements and results presented in this paper shows the impact of load impedances connected to the electrical network on insertion gain and capacity for Multiple Input Multiple Output (MIMO) PLC channel.

This paper presents a 220-245 GHz 4 way Butler Matrix chip in 0.13μm SiGe BiCMOS technology. The chip features four 230 GHz amplifiers with almost 9 dB of gain. A SP4T switch is integrated to select between the four outputs of the beamforming network. Finally, an amplifier used to compensate the losses of the SP4T is integrated. The chip exhibits 0 dB of insertion gain and draws 104 mA from 3.3 V supply mainly consumed by the amplifiers. The entire chip occupies 1.5 × 2.4 mm2.

This paper presents insertion gain predictions for both the differential mode (DM) and the common mode (CM) of an EMI filter. The proposed approach, essentially based on measurements, allows prediction of EMI filter performance for high-complexity converters without time-consuming simulations. The key idea is to use direct measurements to represent the complex system by an equivalent circuit in the frequency domain. The source impedance, which is the more complex part of this equivalent circuit because of its non-linear time variation, is carefully analyzed for continuous current mode (CCM) in boost configuration. This study shows that the source impedance is generally masked by external impedance and can be treated as a linear system. Experimental results for insertion gain prediction are included for second-order filters for both DM and CM on a three-phase SiC JFET Vienna/two-level converter.

This paper presents a digital hearing aid chip designed for Mandarin user to enhance speech quality and intelligibility. The hearing aid consists of an 18 subbands analysis and synthesis filter bank, insertion gain stage, and three channels wide dynamic range control for the new Mandarin-specific auditory compensation algorithm. A noise reduction block based on multiband spectral subtraction and enhanced entropy voice activity detection is also included to enhance quality. We reduce the power consumption of these algorithms through algorithmic and architecture optimization. In addition, for the data storage requirement, a low power SRAM that can operate at 0.6V and below is developed. Moreover, several strategies such as multi-clock domain, bypass mode, and voltage scaling are also adopted for power reduction. The chip measurement shows that the hearing aid consumes 314uW at 0.6V.

This paper presents a voltage controlled phase shifter in a 0.25 um SiGe BiCMOS technology for 60 GHz applications. Vector combination technique is adopted in phase shifter core. Continuous 360 degree phase tuning from 40 GHz to 70 GHz has been measured. The insertion gain of the complete test circuits is 4.6 dB and that of the phase shifter core is 7.6 dB. The phase shifter is best suited for 60 GHz phased array systems. To the authors' knowledge, this is the first phase shifter of this type for 60 GHz applications.

This paper presents the backplane effects for a balanced transmission line crossing two rectangular apertures in dual infinite ground backplanes. The FDTD method is used to determine the characteristics of the backplane insertion losses of the transmission line between the first backplane and the second backplane as the line length increases. The results show that the insertion gain is obtained from the half wavelength intervals for the total transmission line length. The backplane insertion loss and gain values vary depending on the length increase between dual conducting screens. As the length of the line increase both the insertion gain and loss at specific frequency ranges. The measurement of the insertion loss is performed to verify the theoretical analysis.

This paper presents the backplane effects for two-wire transmission lines with an unbalanced transmission line crossing the rectangular aperture in a infinite ground backplane. The FDTD method is used to determine the characteristics of the backplane insertion and return losses of the transmission line in accordance with the transmission line spacing and additional wire lengths. The results show that the insertion gain is obtained from the narrow spacing of the transmission lines and the insertion losses appear by the transmission line with the additional wire. The measurements of the return loss is performed to verify the theoretical analysis.

A selective area growth model was used to engineer a remote amplified modulator with an AlGaInAs multi-quantum well active layer. The selective mask layout was designed to fulfill special component requirements including +35 nm SOA gap detuning and low polarization dependence. The fabricated reflective device exhibits 10 dB maximum insertion gain and operates at 10 Gbit/s over 80 nm spectral range.

We integrated an AlGalnAs modulator-amplifier using semi-insulating buried hetrostructure and selective area growth. The reflective component exhibits insertion gain, operates at 10Gbit/s over 80nm and links bi-directional 10km SMF up to 60°C.

This paper describes a dual-bands low noise amplifier design for WCDMA and WiMAX applications. The low-noise amplifier (LNA) is implemented with the proposed dual-band matching network that consists of a high-pass and low-pass ladder. The LNA is fabricated in 0.5 um enhancement- mode pHEMT (E-mode pHEMT) technology for high linearity and low noise application. The measured noise figures (NF) and insertion gains (S21) are 1.2 dB and 16.1 dB at WCDMA band, 1.45 dB and 15.1 dB at WiMAX band. With 3-V supply voltage and 28.8-mW power consumption, the input third order intercept points (IIP3) are 6.5 dBm and 8.9 dBm for WCDMA and WiMAX, respectively.

RF mixer-filters made by micromachining composite metal and dielectric interconnect layers within foundry CMOS are a potential component in on-chip receivers. Through the electrostatic voltage-squared nonlinearity, mixer-filters down-convert to an intermodulation frequency set by the mechanical resonance enabling higher gain than resonant filters having a RF signal output. The research is leading toward resonant mixer-filters integrated with preamplifiers and having 0 dB insertion gain with sub-mW power

This paper proposes a multi-band low noise amplifier design for WMAN and WLAN applications. The target frequency bands include licensed bands of 2.3 GHz, 2.5 ~ 2.7 GHz and 3.5 ~ 3.7 GHz, and un-licensed bands of ISM 2.4 GHz and U-NII 5 GHz. The LNA adopts a band selection technique that uses a multi-tap inductor with complementary switch capacitor array. The measured NFs and IIP3s of the proposed LNA are 6.5 dB and - 3 dBm at 2.4 GHz, 7.6 dB and - 5 dBm at 3.5 GHz, and 8.5 dB and + 1 dBm at 5.2 GHz, respectively. The insertion gain S21's are 15 dB at 2.4 GHz, 17 dB at 3.5 GHz, and 15.4 dB at 5.4 GHz. Using a 0.18μm CMOS process, the multi-band LNA dissipates 14.6 mW at 2.4 GHz, and 27.7 mW at 3.5 and 5 GHz without output buffer from a 1.8-V supply voltage.

A solution for relatively inexpensive chip carrier for multi-port phase controlling MMIC's in the Ku band is presented in this paper. The basic aim of the chip carrier design is the achieving of high enough isolation between the relatively close situated 8 input and 2 output ports. First, the input ports are placed perpendicularly to each other. Second, fully grounded coplanar waveguide arrangement of the chip carrier embedding paths is used. The both, upper and bottom grounded metallization of the carrier are properly connected with optimized array of via holes. The input embedding signal paths on the carrier are additionally matched to the impedance of the single wire bonds with given lengths. Different types of interconnections to the antenna printed circuit board are also investigated and a lateral metallization is chosen due to its better manufacture reproducibility. The S-parameters of the embedding path of chip carriers on TMM10i substrate are estimated with custom designed chip phantoms. The measurement gives the following data: insertion losses -0.45 dB, return losses -22 dB, isolation better than -27.5 dB at the frequency 12.5 GHz. These results are very close to these obtained by 3D Ansofi HFSS simulator. On this base the conclusion is that the utilization of the considered chip carrier ensure acceptable RF performances practically for all packaged MMIC's, which are able to satisfy the dc and digital functionality test. The obtained statistical deviations for the MMIC parameters in the frequency range 12.2-12.7 GHz are /spl plusmn/ 0.5-0.6 dB for the insertion gain, /spl plusmn/ 2-3 dB for the return losses and /spl plusmn/ 5-10/sup 0/ for the insertion phase shift. The corresponding tolerances, which are connected to the own chip carrier parameters, are smaller - /spl plusmn/ 0.25 dB for IL and /spl plusmn/ 1.0 dB for RL.

An automated measurement setup for characterization of 10-signal port MMICs is described in this paper as an opportunity for fast, comparative and enough accurate 100-percent control of their important parameters: insertion gain, insertion phase, phase step and return losses. The particular application of the tested devices is phase control and signal summation in multi-layer antenna arrays in the Ku-band. A phantom verification of all the embedding paths combined with utilization of mixed measurement techniques (both frequency and time domain VNA options) is applied for the phantom parameter characterization. That allows better extraction of the reflected, as well as the transmitted S-parameters of the non-symmetrical 10-port test fixture used. The estimation of the measurement tolerances gives the following intervals for the standard deviation of the controlled parameters from the mean values caused by the measurement reproducibility: /spl plusmn/0.1 dB for the insertion losses and /spl plusmn/1.0 deg for the phase shift. These values are much smaller than the acceptable deviation for the MMICs parameters: /spl plusmn/0.55 dB and /spl plusmn/7.0 deg for the gain and phase, respectively. Therefore, the test procedure with the considered automated setup gives statistically significant results for a great number of controlled MMICs.

A predistortion type equi-path linearizer is created for a radio-on-fiber system based on W-CDMA; its main benefit is its simple optical circuit configuration. Experiments show that the phase of the third order intermodulation components of the laser diode is delayed by around 90 degrees from those of RF amplifier. To our knowledge, this is the first report to describe the phase delay. To counter this delay we place an additional phase shifters. The proposed design places a pre-amplifier between the linearizer and a laser diode for lower power consumption and better insertion gain at the linearizer. The experimental and calculated results agree well, and an over 20dB improvement in third order intermodulation components is obtained for the bandwidth of 60MHz. The linearizer works well in the temperature range of 10°C to 40°C with a simple control circuit.

We report a new type of high-performance RF-lightwave transmitter, which can provide >10 dB RF insertion gain at

A novel, nonblocking active 2*2 switch composed of distributed-amplifier-based splitters and combiners has been developed. The distributed amplifier architecture yields a broadband, compact, nonblocking switch that has greater than 0 dB insertion gain from 2 to 18 GHz. The conventional approach to nonblocking switching requires considerably higher circuit complexity and size to achieve the same level of performance. >

The design, fabrication, performance, and production results of a GaAs monolithic phase shifter, based on a vector modulator principle, are described. The device exhibited a typical root-mean-square (RMS) phase error of about 3 degrees and an RMS amplitude error of less than 0.30 dB across the frequency band of 7.0-10.5 GHz and over a linear controllable gain range of 15 dB. Typical insertion gain was 0 dB, input return losses were better than 15 dB and output return losses were better than 10 dB. The device is intended for application in a wideband active phased-array antenna. The analog control of the device allows the correction of the systematic phase errors and amplitude errors. Tests have demonstrated that through phase correction the RMS phase error was reduced to less than 0.7 degrees while the RMS amplitude error was still less than 0.30 dB. >

A novel concept resulting in a good insertion gain flatness in receiver applications is reported. The idea is based on inserting into a chain a device with an attenuation characteristic equal and opposite to the gain variation of the rest of the chain. An electronically tunable flatness corrector composed of coupled lines controlled by varactors has been realized in the Ku-band. This idea has been applied in a hybrid circuit used in a space telecommunications receiver. Insertion losses of 0.25 dB, dynamic correction of 1.5 dB, and input/output return losses of better than 15 have been measured. >

The booster instrumentation uses analog and digital fiber-optic links, designed to withstand at least 50 krads without performance degradation. The links use inexpensive and commercially available components that operate at a center wavelength of 820 nm. The analog link operates at 30 MHz over a 200-m fiber and can provide insertion gain. The digital link provides 60-ns timing pulses without the dispersive effects of coaxial cables. The optical fiber is a step-index hard clad silica type with a 200- mu m core. Component selection criteria, link design, installation, testing and performance for the optical links in the Booster instrumentation systems are presented. >

Experimental and theoretical studies of high-performance fiber-optic links are reported. For the experimental directly modulated link, the measured electrical insertion gain was -4.9 dB at a bandwidth of 1500 MHz, and 0.3 dB at a bandwidth of 200 MHz. For the experimental externally modulated link operating at a bandwidth of 800 MHz, the calculated electrical insertion gain based on actual device parameters is -1.0 dB, while at 150 MHz a gain of 6.0 dB is expected. Both links have no active amplification. The directly modulated links have higher noise figures because of the high relative intensity noise of the diode laser. >

An active image rejection filter applying actively coupled passive resonators is presented. The filter has very low noise and high insertion gain, which may eliminate the use of an LNA in front-end applications. The filter is applicable as a single block LNA and image rejection filter in cordless and mobile telephone systems working around 2 GHz, e.g. DECT and DCS-1800 systems. The GaAs MMIC chip area is 3.3 mm/sup 2/. The filter has 12 dB insertion gain, 45 dB image rejection, 6.2 dB SSB noise figure and consumes 13 mW power from a 3 V supply.

This paper reports on a 4th order HBT active bandpass filter based on a conservative 2-/spl mu/m GaAs HBT technology which possesses f/sub T/'s and f/sub max/'s of 24 GHz and 50 GHz, respectively. The MMIC operates at a center frequency of 6.45 GHz with a +0.25 dB insertion gain and a 1100 MHz -3 dB bandwidth. A lower-out-of-band rejection of -45 to SO dB is also obtained. The measured NF and input IP3 are 15.1 dB and -7.9 dBm, respectively. The corresponding P/sub 1db/ is -5 dBm. The compact 4th order bandpass filter MMIC is only 1.6/spl times/1.2 mm/sup 2/ and consumes 208 mW of dc power. This work represents the first fully RF (NF, IP3, P/sub 1dB/) characterized HBT MMIC active filter results so far reported. We believe that the HBT active filter MMIC design demonstrates compact size and feasible RF performance suitable for monolithically integrated DDFS, ADC anti-alias, and harmonic filter applications.

A compact four-channels high gain and high isolation receiver unit has been developed at Ka-band frequencies. A total of 48 input and output signals are present in the receiver unit: 15 RF signals, 16 differential control signals and 5 DC bias feeds. The receiver unit presents 30dB insertion gain, 7.5dB noise figure and over 32dB isolation between the transmitter and receiver paths with an overall transmission insertion loss of 2dB.

Coplanar 4-bit phase shifters for W-band operation at 94 GHz have been developed using PM-HEMTs as switching elements. The phase shifter MMIC uses double stub loaded lines and branch line couplers. A two-stage variable gain cascode amplifier was integrated with the phase shifter. This combination has insertion gain of 2-8 dB and occupies an area of 1.5/spl times/4 mm/sup 2/. A redesigned version of the phase shifter occupies 1/spl times/2.5 mm/sup 2/ chip area, and has a standard phase deviation of less than 2.1/spl deg/ for all phase states.

Summary form only given. In summary, a high-speed polarization insensitive broadband 1/spl times/8 LiNbO/sub 3/ fiber-optic switch module with gain has been demonstrated. It has an insertion gain of -4 dB, a polarization sensitivity of 0.2 dB and a good output uniformity. The fiber-optic switch is expected to have a switching time of subnanosecond when the traveling-wave electrodes with adequate impedance and velocity match are optimized for the Mach Zehnder switching elements.

We present in this paper a model of fibre-optic link at microwave frequencies which is implemented in a frequency-domain non linear simulator (MDS). Comparison between simulated and experimental results is made for the static response and the relative intensity noise (RIN) of the laser, and also the insertion gain and third order intermodulation of the link. The representative fibre-optic link exhibits a dynamic of 73 dB.MHz.

The design and construction of a simple 10-100MHz noise figure and insertion gain calibrator is described. This instrument, constructed from readily available components, tests the accuracy of Y factor based noise figure measurement and insertion gain to better than 0.2dB over the full dynamic range of the target instrument, (usually ~50dB). The limitations of the method and the corrections applicable at the low end of the gain range are shown. An example of re-adjusting an Eaton 7380 is given.

Quarter micron dual-gate MESFETs and pseudomorphic HEMTs connected as a cascode circuit have been fabricated and investigated. The devices exhibit a high output impedance and a very low feedback capacitance resulting in high voltage gain factors gm/gd up to 125 and a Cgs/Cgd ratio up to 45. The maximum stable gain obtained with dual-gate HEMTs is 23.5 dB 10 GHz and 19 dB at 20 GHz, the current gain cutoff frequency is 45 GHz. The cascode PHEMTs show a low noise figure of 1.1 dB with an associated gain of 22 dB at 10 GHz. These results represent the highest gain values and the best noise performance yet reported for dual-gate HEMT devices. With dual-gate MESFETs a dynamic range of more than 35 dB can be obtained for the insertion gain/loss up to 40 GHz by applying a DC voltage swing of 4 V at the second gate electrode. Thus these elements are very promising for gain controllable amplifiers for both low noise and high gain as well as for switching applications.

An initial study at Avantek has established that static accelerated life tests on GaAs FET devices predict about an order of magnitude longer life than active accelerated life tests (tests at elevated temperatures with normal operating bias applied). In order to obtain reliable data, it is necessary to ensure that the devices do not oscillate while under test. To avoid oscillations the drain and source of the FET must be terminated in impedances which are controlled from DC to Fmax. For many of the devices tested Fmas was as high as 80 GHz. A test fixture with 50-ohm ceramic microstrip lines connected to the source and drain proved successful. The packaged GaAs FET and one end of each ceramic microstrip line was attached to a temperature-controlled heated stage. The GaAs FETs used in these tests were fabricated with AuGe/Ni/Au ohmic contacts and TiW/Au overlay metal. An identical layer of TiW/Au was also used for the Schottky barrier gate. They were then her-metically sealed in metal ceramic packages. The failure criterion used to define end of life was a 1-dB degradation of S21 (insertion gain in 50-ohm system) measured at 6 GHz. Insertion gain, S21 was measured with bias conditions which were typically optimum for low noise so long as this current was below Idss. If after stress, Idss was below the current which was previously optimum for noise figure, then measurements would be made at Idss. The average activation energy of the Arrhenius curve of this failure mode was 1.

D.O.D. Directive 3222.3 with its clearly stated objectives (Section IV) of operational and built-in design compatibility necessitates a fresh approach to certain inadequate MIL STD's. One of them is in particular need of revision. MIL STD 220A, with its 50? reference, is based on assumptions contrary to the facts which are: 1) Interfacial impedances change with frequency, time, and location and can be nearly anywhere on the Smith Chart; 2) Interfacial resonances in the stopband, and eigen and interactive resonances in the passband, render the conventionally predicted performance of the filter illusory. Hence, new, more realistic criteria for filter testing are necessary: I. Compatibility: The test method must be a qualification test and must be able to permit selection of the more insensitive filter: insensitive meaning that in the broad area about the cutoff frequency the filter is relatively unaffected by interface changes. II. Predictability: The filter test method must permit a selection of a filter to be effective as stipulated minimally by the control plan prior to installation of the system and independent of changes in the system. III. Reliability: The filter must not be destroyed by insertion gain in the so-called passband. IV. Practicability: Filters meeting the specs must be economical and practical. V. Simplicity: The test method should be reasonably simple and brief. From the various solutions which have been proposed, two try to overcome fundamentally the limitations inherent in MIL STD 220A: (a) the in situ measurement (b) the worst case measurement.