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To fulfill the future need of ultra-low-power applications such as Internet-of-Things (IoT) technologies [1], steep-slope transistors are indispensable. Negative capacitance FET (NCFET) is one of the most promising steep-slope devices because it may possess sub-kT/q swing and high on/off current ratio simultaneously [2]. For scaled devices especially under low voltage operation, statistical variation is one ma­jor concern. The random variation may stem from intrinsic variations and discrete interface charges [3], [4]. The impact of the interface charge can also be an indication of the bias temperature instability (BTI) responsible for the time-dependent transistor degradation [5]. The research related to the impact of interface traps on the NCFET is still lacking and merits investigation. In this work, through atomistic TCAD simulation, we investigate the interface discrete trap induced variability for negative capacitance FinFETs (NC-FinFETs).

Using the concept of design space, we have investigated and compared the subthreshold characteristics of UTB NCFETs with Ge/Si channel. Our results indicate that high permittivity channel is more suitable for NCFET design because of the high C ch . Furthermore, as channel length shrinks, the optimal SS of the NCFET becomes smaller due to the drain coupling (C DIBL ). In other words, GeOI NCFETs can achieve lower SS than the Si counterpart due to their higher C ch and C DIBL .

Dielectric-loaded surface plasmon polariton (DLSPP) is a potential candidate for nanoscale optical elements with sizes much smaller than the diffraction limit and extremely low loss. In this work, we will combine the convenience of fiber based devices and the tight confinement of DLSPP waveguide, and then propose a nanofiber-loaded structure for the DLSPP application. Through the finite element method (FEM) modeling, we demonstrated the hybridization between hybrid surface plasmon polariton modes (HSPPs) and nanofiber modes, and analyzed the generation of hybrid plasmon polaritons (HPPs) super-modes. We also showed the existence of higher order HSPP, which is helpful to reduce the bending loss of DLSPP structure. Due to its polarization dependent transmission loss, we demonstrated one of its applications as polarizer experimentally.

This paper describes a study on non-wet issue encountered in flip chip assembly process of high-density flip chip ball grid array (FCBGA) packages with eutectic Sn/Pb solder interconnects. A nonwet occurrence is more obvious in large-die flip chip (die size >16mm) with high I/O counts (>1000). Thermal-mechanical mismatch between die and substrate shows a role in affecting soldering condition of the die solder bump and substrate SOP. Positive evaluation results, involving: 1) new flux material with increased percentage of solid content or modified activator and 2) plasma treatment on substrate prior to FC assembly, indicate that a more effective approach is needed to improve bump solderability in large die flip chip devices

IC packaging has always required that its components have little or no ionic contamination. This is necessary to avoid any corrosion issues within the package. This, in turn, has pushed the materials suppliers for the packaging industry to ensure that their products are free of contamination. Suppliers of materials ranging from leadframes and substrates to die attach adhesives and molding compounds have measured and reported their ionic contamination levels. They have, however, used their own specific methods and there has, up to now, been no standard for these tests. One of the reasons for a lack of standards is the fact that some of the materials such as die attach and mold compound have contamination levels that can be measured with respect to unit volume or weight of the material. Leadframes and substrates, on the other hand, have surface contamination and so the contamination levels are measured over their surface area. Yet another reason for a lack of standards is the variety of preparation methods employed within the industry. In this study, we measure the contamination levels in a range of IC packaging materials. These include varieties of leadframes, substrates, die attach and encapsulants. Methods for comparison are discussed while the specific details for sample preparation are given.

Flip-chip packages can achieve high interconnect speeds, high-density and be made in thinner dimensions. Despite these advantages, the demand for flip-chip packages is still relatively low when compared to packages using wire bonding. This is due to the requirement for bumped dice for these packages as well as capital expenditure for new equipment dedicated to flip chip packaging. In any case, the positive benefits are expected to drive the industry towards flip chip technology and are expected to take off and grow in the years to come. As this happens, problems unique to flip chip packaging are set to emerge. Unlike traditional packaging, flip chip packaging has more interfaces that are interacting with one another. The ability of these interfaces to stay reliable under various stress conditions is critical to the success of the package. One material that has more interfaces to contend with then any other material within the flip chip package is the underfill. The interfaces that the underfill attaches to include the die surface, solder bump and the solder mask. This paper looks at the change of contact angle over time for three underfills on the die and the solder mask surfaces. This change is also measured for varying temperatures. This is then correlated with the underfill viscosity at those temperatures. Certain time and temperature based relationships are derived. The properties of the three underfills are also discussed and their performance for varying durations in humidity and thermal shock cycling are analyzed.