59 results on '"Hatanaka M"'
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2. TSV process solution for 3D-IC
3. TSV process solution for 3D-IC.
4. VLSI design of OFDM baseband transceiver with dynamic spectrum access.
5. Implementation of OFDM baseband transceiver with dynamic spectrum access for cognitive radio systems.
6. Value creation in SOC/MCU applications by embedded non-volatile memory evolutions.
7. Quartz crystal element for angular rate sensor.
8. A quantitative analysis of stress induced excess current (SIEC) in SiO/sub 2/ films
9. Study on magnetic properties of triaminobenzenes toward charge-transfer organic ferromagnets
10. Molecular orbital study on cationic states of triphenylene and 1,3,5-tris(diphenylamino)benzene as a design of charge-transfer organic ferromagnet
11. H/sub 2/O-TEOS plasma-CVD realizing dielectrics having a smooth surface.
12. Helical etch channels in synthetic quartz crystals.
13. Novel electron injection method using band-to-band tunneling induced hot electrons (BBHE) for flash memory with a P-channel cell.
14. New erase scheme for DINOR flash memory enhancing erase/write cycling endurance characteristics.
15. Suppression of hot carrier effects by laterally graded emitter (LGE) structure in BiCMOS.
16. A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancy
17. A novel CBi-CMOS technology by DIIP process
18. ZrBO dielectrics for TSV production process.
19. Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.
20. A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy.
21. A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates.
22. A 24-b 50-ns digital image signal processor.
23. A 400 K-transistor CMOS sea-of-gates array with continuous track allocation.
24. A high-speed 64K/spl times/4 CMOS DRAM using on-chip self-timing techniques.
25. A 70 ns 256K DRAM with bit-line shield.
26. A beam-index TV receiver for consumer application.
27. A CMOS Dual Port Memory with Serial Read/Write Function for Graphic Systems.
28. A 70ns 256K DRAM with bitline shielding structure
29. A 3.3 V-only 16 Mb DINOR flash memory
30. Implementation of PSK demodulator for digital BS/CS broadcasting system
31. Quartz crystal element for angular rate sensor
32. Helical etch channels in synthetic quartz crystals
33. Novel electron injection method using band-to-band tunneling induced hot electrons (BBHE) for flash memory with a P-channel cell
34. A computer aided accurate adjustment of cellular radio RF filters
35. A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea-of-gates
36. An Over-Erasure Detection Technique for Tightening Vth Distribution for Low Voltage Operation Nor Type Flash Memory
37. Row-redundancy scheme for high-density flash memory
38. Suppression of hot carrier effects by laterally graded emitter (LGE) structure in BiCMOS
39. A 3.3 V-only 16 Mb DINOR flash memory.
40. A 47ns 64KW × 4b CMOS DRAM with relaxed timing requirements.
41. A novel CBi-CMOS technology by DIIP process.
42. A CMOS sea-of-gates array with continuous track allocation.
43. Row-redundancy scheme for high-density flash memory.
44. A high programming throughput 0.35 /spl mu/m p-channel DINOR flash memory.
45. An Over-Erasure Detection Technique for Tightening Vth Distribution for Low Voltage Operation Nor Type Flash Memory.
46. Implementation of PSK demodulator for digital BS/CS broadcasting system.
47. New technique to decrease dislocations in synthetic quartz crystal.
48. New bit line architecture for ultra high speed SRAMs-T-shaped bit line and its real application to 256 k BiCMOS TTL SRAM.
49. Submicron CBiCMOS technology with new well and buried layer formed by multiple energy ion implantation.
50. A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea-of-gates.
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