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An accurate characterization of the neutron fields at spallation sources is crucial for many applications based on neutron irradiations, such as radiation damage tests that need a precise dose estimate. In this work, we present the neutron flux measurements performed with the multi-foil activation technique in the ROTAX and ChipIr beamlines of the ISIS spallation source, characterized by moderated and unmoderated spectra, respectively. We selected many different activation reactions to cover a wide energy range, from thermal to very fast neutrons up to about 100 MeV. By applying a Bayesian unfolding algorithm, we demonstrate the effectiveness of this technique in measuring the neutron flux intensity and energy spectrum with precision and accuracy. [ABSTRACT FROM AUTHOR]

Single-event (SE) performance of the guard-gate flip-flop (GG-FF) and conventional D-FF designs is evaluated at the 16- and 7-nm FinFET technology nodes. The heavy-ion test results show that at the 16-nm node, the GG-FF shows better SE performance for low-linear energy transfer (LET) particles and similar performance for high-LET particles compared with D-FF design. However, at the 7-nm node, the GG-FF shows better SE performance than the D-FF across a wide range of particle LET values. This behavior is due to the higher number of short SE transient (SET) pulses for high-LET particles at the 7-nm node. The heavy-ion test results are used to estimate the number of short SET pulses as a function of particle LET values. [ABSTRACT FROM AUTHOR]

The sensitivity of vertical-channel 3-D NAND flash memories to wide-energy spectrum neutrons was investigated. The effects of neutron exposure on a 3-D floating gate (FG) cells were studied in terms of threshold voltage shifts and raw bit error rates. The neutron failure rates obtained in the accelerated tests were extrapolated to field conditions at sea level and aircraft altitudes. The results are compared with previous data on 3-D nand flash devices irradiated with heavy ions, as well as data on planar FG cell technologies. [ABSTRACT FROM AUTHOR]

Neural networks are becoming an attractive solution for automatizing vehicles in the automotive, military, and aerospace markets. Thanks to their low-cost, low-power consumption, and flexibility, field-programmable gate arrays (FPGAs) are among the promising devices to implement neural networks. Unfortunately, FPGAs are also known to be susceptible to radiation-induced errors. In this paper, we evaluate the effects of radiation-induced errors in the output correctness of two neural networks [Iris Flower artificial neural network (ANN) and Modified National Institute of Standards and Technology (MNIST) convolutional neural network (CNN)] implemented in static random-access memory-based FPGAs. In particular, we notice that radiation can induce errors that modify the output of the network with or without affecting the neural network’s functionality. We call the former critical errors and the latter tolerable errors. Through exhaustive fault injection, we identify the portions of Iris Flower ANN and MNIST CNN implementation on FPGAs that are more likely, once corrupted, to generate a critical or a tolerable error. Based on this analysis, we propose a selective hardening strategy that triplicates only the most vulnerable layers of the neural network. With neutron radiation testing, our selective hardening solution was able to mask 40% of faults with a marginal 8% overhead in one of our tested neural networks. [ABSTRACT FROM AUTHOR]

In previous works, we have demonstrated the importance of dynamic mode testing of SRAM components under ionizing radiation. Several types of failures are difficult to expose when the device is tested under static (retention) mode. With the purpose of exploring and defining the most complete testing procedures and reveal the potential hazardous behaviors of SRAM devices, we present novel methods for the dynamic mode radiation testing of SRAMs. The proposed methods are based on different word address accessing schemes and data background: Fast Row, Fast Column, Pseudorandom, Adjacent (Gray) and Inverse Adjacent (Gray). These methods are evaluated by heavy ion and atmospheric-like neutron irradiation of two COTS SRAMs of 90 nm and 65 nm technology. [ABSTRACT FROM PUBLISHER]

We study the response of NAND Flash memories to neutron and alpha particle exposure, on both Single- and Multi-Level Cell architectures manufactured in sub 30-nm technologies. We analyze the error rates and identify the relative importance of neutrons and alphas in the terrestrial environment and at aircraft altitudes, with both low-alpha and ultra-low-alpha materials. The efficacy of error correction codes is illustrated. Scaling trends are then discussed and modeled in single-level and multi-level cell devices. [ABSTRACT FROM PUBLISHER]

Single Event Burnout and Gate Rupture are catastrophic failures due to cosmic rays that can occur simultaneously. It is shown that negatively biasing the gate leads to a substantial increase of SEB cross section in particular when the collector voltage is closer to the safe operating area of the device. [ABSTRACT FROM PUBLISHER]

While single bit upsets on memories and storage elements are mitigated with either the use of redundancy and/or error correction codes, Multiple-Cell-Upsets (MCU) may become a significant threat to the integrity of systems when the corrupted cells belong to the same word. In this paper, we identify four types of MCUs as they were recorded during several irradiations under an atmospheric-like neutron beam (ISIS facility). An analysis is done on the underlying reasons of occurrence of each MCU type, as well as their shapes and sizes in order to classify them. The results of this work concern a commercial 90 nm SRAM that was tested under an atmospheric neutron beam in static and dynamic mode. It is shown that, when the memory is in dynamic mode, not only the typical MCUs that involve a few flipped cells may appear but also large clusters of upsets are possible to occur with hundreds or even thousands of cells being affected. [ABSTRACT FROM PUBLISHER]

A higher Degree of Parallelism decreases the code execution time. However, a higher scheduler strain is necessary to manage the increased number of parallel processes, which have the countermeasure of increasing the graphics processing unit (GPU) cross section. This hypothesis is confirmed by extensive neutron irradiation testing to study how the Degree of Parallelism affects GPU reliability. Moreover, the cache distribution forced by different Degrees of Parallelism is proved to influence the application error rate. Finally, the Mean Executions Between Failures metric is introduced to evaluate the amount of data computed correctly by the GPU on a practical application. [ABSTRACT FROM PUBLISHER]

In this paper we assess the neutron sensitivity of Graphics Processing Units (GPUs) when executing a Fast Fourier Transform (FFT) algorithm, and propose specific software-based hardening strategies to reduce its failure rate. Our research is motivated by experimental results with an unhardened FFT that demonstrate a majority of multiple errors in the output in the case of failures, which are caused by data dependencies. In addition, the use of the built-in error-correction code (ECC) showed a large overhead, and proved to be insufficient to provide high reliability. Experimental results with the hardened algorithm show a two orders of magnitude failure rate improvement over the original algorithm (one order of magnitude over ECC) and an overhead 64% smaller than ECC. [ABSTRACT FROM PUBLISHER]

Neutron radiation experiment results on matrix multiplication on graphic processing units (GPUs) show that multiple errors are detected at the output in more than 50% of the cases. In the presence of multiple errors, the available hardening strategies may become ineffective or inefficient. Analyzing radiation-induced error distributions, we developed an optimized and experimentally tuned software-based hardening strategy for GPUs. With fault-injection simulations, we compare the performance and correcting capabilities of the proposed technique with the available ones. [ABSTRACT FROM AUTHOR]

We introduce a new hardware/software platform for testing SRAM-based FPGAs under heavy-ion and neutron beams, capable of tracing the bit-flips in the configuration memory back to the physical resources affected in the FPGA. The validation was performed using, for the first time, the neutron source at the RAL-ISIS facility. The ISIS beam features a 1/E spectrum, which is similar to the terrestrial one with an acceleration between 107 and 108 in the energy range 19-100 MeV. The results gathered on Xilinx SRAM-based FPGAs are discussed in terms of cross section and circuit-level modifications. [ABSTRACT FROM AUTHOR]