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The principle of two common base/gate millimeter-wave power detectors is analyzed and validated by experimental results. The detectors have been designed for automatic level control and built-in-test millimeter-wave applications. Closed-form expressions are derived for the transfer characteristic as well as for the noise behavior of each detector. The circuits are fabricated in a BiCMOS 55 nm ( ft/{f\max } = 320 GHz/370 GHz) process from STMicroelectronics. Each detector occupies an area of 80\,\times\, 80 \mu \m^2 and exhibits a relatively high input impedance at 60 GHz. Measurements show a detection dynamic range larger than 38 dB and a flat response over the 50–66 GHz bandwidth, for both detectors. Common-base detector shows a wider linear detection range than that of the common-gate one. Theoretical computation and computer simulation show that, for square-law detection, the minimum detectable input power (for \SNR= \10~dB) is around - \41~dBm for the common-gate detector against - \50~dBm for the common-base one. In their nominal bias conditions, the detectors' power consumption, under 1.2 V supply voltage, is 90 \mu \W for low input power and it increases to about 800 \mu \W for 8.5 dBm input power. These performances are beyond the current state-of-the-art of millimeter-wave detectors. [ABSTRACT FROM AUTHOR]

The vertical shrinkage of the advanced CMOS processes thicknesses makes electrostatic discharge (ESD) issues become more significant. RF and millimeter-wave (mm-wave) circuits are very sensitive to the ESD components’ capacitive parasitic effect. Surface area is a key factor as well in an ESD protection circuit for mm-wave applications. This paper presents silicon-verified ESD solutions, which fulfill physical dimensions, ESD robustness, and broadband frequencies requirements. [ABSTRACT FROM PUBLISHER]

This paper presents the application of the state space approach to analyze stability and robustness of multiloop linear low dropout (LDO) regulators. Because of the increasing complexity of the LDO architecture, the stability study consisting of an open-loop ac analysis is more and more difficult to apply. In this paper, we demonstrate how a state matrix decomposition of a system allows the stability analysis in closed loop to be performed where the open-loop ac analysis failed. Based on this technique, a methodology of design, a time response criterion, and a Monte Carlo analysis are proposed. The efficiency of this approach is illustrated comparing the classical open-loop ac study with the state matrix decomposition analysis of a complex innovative architecture LDO. The results are verified experimentally. [ABSTRACT FROM AUTHOR]

High-performance integrated slow-wave coplanar waveguides (S-CPW) are compared with conventional coplanar waveguides (CPW) fabricated in a 65-nm High-Resistivity-SOI (HR-SOI) CMOS technology. As expected, S-CPW demonstrates better performance at millimeter-wave frequencies in term of higher effective dielectric permittivity, which is due to the patterned floating shield inserted between the transmission line and the substrate. In addition, S-CPW shows a lower attenuation constant despite of the added metallic patterned floating shield on HR substrate. For demonstration purpose, both low- and high- characteristic impedance S-CPW and CPW are characterized. For 28- \Omega S-CPW and 65-\Omega S-CPW, the effective dielectric permittivity is improved by a factor of 6 and 2, respectively. Meanwhile, attenuation constants of slow-wave structures are lower than 0.9 dB/mm and 0.57 dB/mm at 60 GHz, compared to CPW ones which are as high as 1.5 dB/mm and 0.95 dB/mm, respectively. Furthermore, the loss distribution for the S-CPW structure is detailed by varying the patterned floating shield length for both standard Bulk and HR-SOI substrates. [ABSTRACT FROM PUBLISHER]

This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several g m-enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic g m of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP3 is -12 ∼dBm for an input compression point of -21 ∼dBm. [ABSTRACT FROM AUTHOR]

A hot carrier ageing model previously validated on a one-stage 60-GHz power amplifier (PA) is demonstrated to be able to predict the degradation of the characteristic parameters for multistage high-performance millimeter-wave (mmW) PAs. The increase in the threshold voltage, the decrease in the transconductance, and the output conductance of the MOSFETs caused by hot carriers leads to a degradation in performance of the PAs. Consequently, by using this ageing model, the mmW PA lifetime can be extracted. A new PA is then designed, taking into account the ageing effects, and is shown to be reliable during ten years. This amplifier exhibits a power gain of 20 dB, an output 1-dB compression point of 12.5 dBm with 6.6% power-added efficiency, and a saturated output power of 16 dBm at 60 GHz. [ABSTRACT FROM PUBLISHER]

A D-Band power source implemented in the STMicroelectronics BiCMOS 55 nm technology and dedicated to on wafer characterization in millimeter-wave band frequency is presented. The circuit consists in multiplying by four a low frequency signal by cascading two frequency doublers. Two intermediate power amplifiers optimized at the second and fourth harmonics respectively are implemented after each doubler. A high-pass filter implemented before the second amplifier performs the rejection of the first and second harmonics to obtain a pure fourth harmonic output frequency. The measured peak output power is 10 dBm at 140 GHz with a −3 dB bandwidth of 24 GHz and a DC power consumption of 0.61 W. The total chip area is $1.7 \times 1.35$ mm2. [ABSTRACT FROM PUBLISHER]

Taking full advantage of the high resistivity substrate and underlying oxide of silicon-on-insulator (SOI) technology, a high-performance CMOS single-pole double-throw (SPDT) T/R switch for Bluetooth class-II applications has been designed and fabricated in a partially depleted 0.25-µm SOI process. To compare the influence on losses and isolation of the substrate resistivity, the switch has been integrated above standard and high resistivity (20 Ω·cm and 1 kΩ·cm) substrates. The switch over the standard resistivity substrate exhibits 1 dB of insertion loss and 45 dB of isolation at 2.4 GHz. With the high resistivity substrate, the overall performances are strongly improved until 0.7-dB insertion loss and a 54-dB isolation at 2.4 GHz. At 5 GHz, the switch over the high resistivity substrate keeps insertion loss and isolation at 1 and 46 dB, respectively. In both cases, the measured 1-dB input compression point is 12 dBm. The targeted Bluetooth class-II specifications have been fully fitted. [ABSTRACT FROM AUTHOR]

In this letter, a traveling-wave single-pole double-throw (SPDT) switch using slow-wave coplanar waveguides is implemented in a 65-nm triple-well CMOS process. For performance improvement, double-well body-floating technique is used. The p-well layer and deep n-well layer of nMOSFET being, respectively, biased to -1.4 and 2.0 V, the measured SPDT exhibits an insertion loss of 2.8 dB and an isolation of 20 dB at 60 GHz. A measured input 1-dB compression point (ICP1dB) of 17 dBm is obtained at 35 GHz (16.3 dBm at 60 GHz by simulation). The total chip size is only 0.42 mm^2 (780 \mum\times\,540 \mum) including all testing pads. [ABSTRACT FROM PUBLISHER]

The effects of RF hot-carrier stress on the characteristics of 60-GHz power amplifiers (PAs) on a CMOS 65-nm process are investigated, for the first time, in this letter. A reliability study is made on a one-stage PA to validate an aging model and the degradation explanation. A drop of 16% of the gain, 17% of the 1-dB output compression point (OCP1dB), and 17% of the Psat are measured at 60 GHz after 50 h of stress under Vdd = 1.65 V with Pin = 0 dBm and Vdd = 1.9 V with Pin = -10 dBm at 60-GHz frequency. [ABSTRACT FROM AUTHOR]