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Performance Improvement Versus CPW and Loss Distribution Analysis of Slow-Wave CPW in 65 nm HR-SOI CMOS Technology.

Authors :
Tang, Xiao-Lan
Franc, Anne-Laure
Pistono, Emmanuel
Siligaris, Alexandre
Vincent, Pierre
Ferrari, Philippe
Fournier, Jean-Michel
Source :
IEEE Transactions on Electron Devices; May2012, Vol. 59 Issue 5, p1279-1285, 7p
Publication Year :
2012

Abstract

High-performance integrated slow-wave coplanar waveguides (S-CPW) are compared with conventional coplanar waveguides (CPW) fabricated in a 65-nm High-Resistivity-SOI (HR-SOI) CMOS technology. As expected, S-CPW demonstrates better performance at millimeter-wave frequencies in term of higher effective dielectric permittivity, which is due to the patterned floating shield inserted between the transmission line and the substrate. In addition, S-CPW shows a lower attenuation constant despite of the added metallic patterned floating shield on HR substrate. For demonstration purpose, both low- and high- characteristic impedance S-CPW and CPW are characterized. For 28- \Omega S-CPW and 65-\Omega S-CPW, the effective dielectric permittivity is improved by a factor of 6 and 2, respectively. Meanwhile, attenuation constants of slow-wave structures are lower than 0.9 dB/mm and 0.57 dB/mm at 60 GHz, compared to CPW ones which are as high as 1.5 dB/mm and 0.95 dB/mm, respectively. Furthermore, the loss distribution for the S-CPW structure is detailed by varying the patterned floating shield length for both standard Bulk and HR-SOI substrates. [ABSTRACT FROM PUBLISHER]

Details

Language :
English
ISSN :
00189383
Volume :
59
Issue :
5
Database :
Complementary Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
74556224
Full Text :
https://doi.org/10.1109/TED.2012.2186969