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The reliability of the transformer differential protection is under threat from multiple interferences, including the inrush condition, the current transformer saturation condition, and the arc fault condition. For improvement, a new method is proposed to discriminate fault conditions and other non-fault conditions. Firstly, the proposed method identifies the unidirectional inrush via unidirectional index, since only it exhibits unidirectional characteristic. Then, the remaining signals are classified by the quartering-based similarity index. The quartering-based similarity index is obtained by quartering segmented fitting to overcome the drawback of overall fitting. Simulation results indicate that the proposed method is able to effectively avoid misjudgments caused by aforementioned interferences. Actual experimental tests, field data tests, and comparison analyses demonstrate its engineering adaptability and superiority.

This study focused on comparing the performance of three high impedance fault detection techniques for the case of a distribution network to select the technique that is best suited for detecting faults in this network. The three most common techniques; discrete Fourier transform, discrete wavelet transform, and the power spectrum among other techniques were selected for the research work based on literature. The distribution network was modelled in MATLAB/Simulink, along with the High Impedance Fault condition. These fault detection techniques were modelled and applied separately to the distribution network under different operating conditions: high impedance fault, load switching, and normal operation. The suitability of these techniques for the distribution network is evaluated by comparing them in terms of accuracy, processing time, and fault detection margin. The power spectrum technique was found to be the most suitable technique for detecting high impedance faults on a distribution network, with a 100% accuracy, a shorter processing time, and a larger fault detection margin.

This paper proposes a time-domain-based protection scheme for radial and loop microgrid systems with inverter-based resources (IBRs), such as solar photovoltaic (PV) systems and type-4 wind turbines. The protection scheme is designed to function during both grid-interconnected and grid-isolated modes. The proposed scheme provides an ultra-high-speed sub-cycle directional element aided with low bandwidth communication between relays. Like directional comparison schemes, relays identify whether faults are in-zone or out-zone. The directional element is based on time-domain superimposed quantities and Park’s transformation algorithms. Specifically, the element calculates the superimposed positive-sequence direct component of transient energy during faults. Superimposed voltage and current quantities are calculated using delta filters and decoupled double synchronous reference frame (DDSRF) filters. The proposed filtering method improves the reliability of the superimposed directional element when IBRs are the main source of fault current. The protection scheme is evaluated on a modified IEEE 34-bus distribution system simulated using an electromagnetic transients program.

Hybrid DC circuit breakers (HDCCBs) have excellent performance in terms of breaking speed and low losses and have become the mainstream technology for dc fault isolation in dc grids. However, because of the breaking limitation of the solid-state branch in HdcCBs, the existing HdcCBs are still weak in breaking high current. Although the breaking ability can be improved by series and parallel devices, the cost will increase rapidly, and it is very difficult to share current by paralleling a single type of device. This article proposes a novel HdcCB topology that combines two types of power electronic devices in solid-state branches to meet the requirement of a large breaking capacity in dc grids. The structure and breaking principles of this novel topology, which aims to break high current, are introduced. The design methods of the key parameters are presented. Then, the current breaking ability of the novel topology is verified by developing a prototype completing a 10 kV/60 kA breaking test in 3 ms. Finally, this novel topology is compared with other dc circuit breakers at the same breaking level, which shows that this novel topology has obvious advantages in cost and volume with fewer devices. [ABSTRACT FROM AUTHOR]

In this article, a postfault control technique is proposed for a rotor field-oriented induction motor (RFO-IM) drive fed from a cascaded H-bridge multilevel (CHB-ML) converter. The control strategy is to vary the magnitude and phase shift of the injected fundamental common mode voltage (FCMV) according to the motor’s operating condition. The addition of the proposed FCMV with the reference phase voltages, not only ensures maximum line voltage in the postfault operating condition but also shares equal power among the remaining healthy cells of the converter. Moreover, in the postfault operation, a detailed analysis is performed on both motor and converter, and an integrated control is presented to maintain the command speed and load torque of the RFO-IM. This includes the mathematical equation explaining the new operating point of the motor for different fault configurations, traversal of operating point, and the variation in power factor of each leg of the converter in postfault conditions. From the above analysis, the dynamic FCMV is calculated from the new operating point of the stator current components in the current dq-plane and the fault configuration of the CHB-ML converter. The proposed control technique is validated using simulation and experimental results conducted on a 3-hp IM. [ABSTRACT FROM AUTHOR]

When a recloser detects fault currents in electric power distribution lines, it breaks the line and then restores the line after several fault tests. To check whether fault remains, the recloser performs CO operations (opening the contacts after reclosing them for a while). In this operation, the fault currents flow into the line, potentially causing damage to equipment connected to the line. Therefore, reducing the current-carrying time during the fault test is desirable, but this reduction is difficult because of the slow actuation mechanism of reclosers. In this article, a novel actuation mechanism combining a permanent magnetic actuator (PMA) and a solenoid actuator (SA) is proposed. During the CO operations for the fault tests, the proposed mechanism can rapidly break the closed contacts by hitting the moving contact with the SA. To increase the energy efficiency of the actuation mechanism, a distinctive PMA driving method is also proposed; it weakens the strong holding force of the PMA using assistive magneto-motive force (MMF). The structure and configuration of the proposed mechanism are explained. The performance of the mechanism and the effectiveness of the driving method are studied through cosimulations. Finally, a prototype is developed, and its practicality is verified through experiments. [ABSTRACT FROM AUTHOR]

The multiport dc/dc converter with input independent output series structure is simple and efficient for photovoltaic (PV) applications. Through the cascade of sub-modules (SM), the converter has a high step-up ratio to connect MVdc bus. However, it has many ports which increase the risk of short-circuit faults. Therefore, this article proposes a fault ride-through (FRT) topology for multiport converter. When low-voltage ports are short-circuited, they can be isolated by blocking the switches of their own. The FRT topology can support the output voltage of faulty SMs to avoid the disconnection from MVdc bus. Other healthy ports can still generate power to MVdc bus. When the medium-voltage port is short-circuited, the FRT topology can quickly clear the fault current to prevent devices from being damaged. Due to the zero voltage switching, the proposed topology has higher efficiency. For medium-voltage fault, the FRT topology has faster fault clearing speed because more capacitors are reused. Finally, the proposed topology is verified by simulation and experiment. [ABSTRACT FROM AUTHOR]

In this article, a novel multiple three-phase PM assisted synchronous reluctance machine with delta windings is proposed for enhanced fault tolerance. The delta connected windings offer an additional degree of freedom of the phase currents. Hence, this machine drive could provide higher torque under phase open-circuit condition. More importantly, the delta windings inherently contain zero sequence current path and could help reducing the turn fault current in the event of the most challenging turn short-circuit fault. Owing to the zero sequence current, the residual flux linkage of the fault turn is more effectively nullified leading to lower fault current. The proposed machine performance together with fault tolerant capability under various fault scenarios are investigated and compared with the star connected winding machine by detailed finite element simulation and experimental tests. It shows that the two machines have the same performance under healthy condition whilst the delta winding machine exhibits higher fault tolerance. These advantages are achieved simply by changing the winding connections without any extra cost. Thus, it is more favorable for the fault tolerant applications. [ABSTRACT FROM AUTHOR]

A flexible dc grid is important for supporting large-scale new energy integrations. To ensure the stable operation of the dc grid, a dc circuit breaker (DCCB) is needed for fault isolation. At present, the cost of DCCBs is high, and the breaking capacity is limited. This limitation can be effectively solved through the coordination of fault current limiters (FCLs) and DCCBs. In this article, a coordinated interruption topology of an magnetic coupling FCL (MCFCL) and hybrid DCCB is proposed. A coordinated interruption strategy based on magnetic coupling current-limiting and energy dissipation is proposed to improve the dynamic performance of the FCL and reduce the energy dissipation and breaking time of the DCCB. A two-stage mathematical model of coordinated interruption is established, and its control principle is analyzed. Furthermore, the influence of the inductance and resistance of the MCFCL secondary side, coupling coefficient and rated voltage of the arrester on the coordinated interrupting process is researched. On this basis, parameter optimization and economic analysis are carried out. Finally, a scaled test for the coordinated interruption of the DCCB and MCFCL was carried out, which verifies the feasibility of the coordinated interruption strategy based on magnetic coupling current-limiting and energy dissipation. [ABSTRACT FROM AUTHOR]

DC circuit breaker (DCCB) is one of the most important technologies for safe and reliable operation of dc grid. And the hybrid DCCB (HCB) is obviously promising in high-voltage application area, because it combines both the advantages of mechanical DCCB and solid-state DCCB. At present, insulated gate bipolar transistors (IGBTs) are generally used for configuring the main breaker branch in the HCB. Compared with IGBTs, thyristors have the merits of ability to bear higher surge current, higher reliability, and lower cost, thus being more economical and reliable when used to replace IGBTs. Right now, several topologies of thyristor-based HCBs have been proposed, but the economy, reliability, control complexity, as well as the operation performance, can still be improved. In this article, a novel passive thyristor-based HCB is proposed. Compared with existing IGBT-based HCBs, the proposed HCB has significant advantages on economy and reliability, due to the application of thyristors for replacing IGBTs. In addition, in the proposed scheme, the required thyristors count is reduced and the additional power supply for capacitor precharging is saved, so the investment and control complexity are both cut down. The feasibility and superiorities of the proposed HCB are validated with scaled-down experiment test and 500-kV-level simulation case study. [ABSTRACT FROM AUTHOR]

Medium voltage dc system has fast rise rate in the event of a short-circuit fault. To avoid high-peak fault current, it is necessary to configure dc circuit breaker with fast operation. Solid-state dc circuit breaker has short breaking time and high reliability, which is suitable for Dc system. In this letter, a novel oscillating-commutation solid-state dc circuit breaker based on compound integrated gate-commutated thyristors (IGCTs) is proposed. By combining IGCTs with different advantages, such as high current breaking and high withstand-voltage capability, the proposed dc breaker has the advantages at less breaking time, high performance, low cost, and small volume. The working principle of the proposed scheme is described in detail, and an 8 kV prototype with 7 kA current breaking ability is built to verify its feasibility. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC)-based solid-state transformers (M-SSTs) show promise in hybrid ac/dc distribution grids where there is need for a medium-voltage dc (MVdc) interface. It can be used to interconnect several distribution networks with different voltage forms and levels and enable flexible power flow among them. In an M-SST, the MVdc short-circuit fault is a critical issue due to the rapidity of the fault current, which can cause device damage and power failure of the low-voltage (LV) grids. Aiming at addressing this issue, this article proposes a fault-mode control strategy applied to a hybrid M-SST topology for uninterrupted power supply of its LV ports. The topology consists of a hybrid MMC with both half- and full-bridge submodules and isolated bidirectional dc–dc converters. Through the proposed control, the fault current is eliminated when an MVdc short-circuit fault occurs. The hybrid M-SST can keep uninterrupted power interaction between the MVac port and the LVdc port during the fault, thereby improving power supply reliability. Moreover, an improved capacitor voltage balance control and an optimized modulation scheme are developed and included in the uninterrupted operation scheme to maintain the harmonic performance of the ac port. The feasibility and effectiveness of the proposed topology and control are verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

This article proposes a new thyristor-based dc solid-state circuit breaker (SSCB) named Y-type. Main contributions focus on a new complementary commutation circuit including a capacitor–capacitor pair, which features three remarkable advantages. First, a fast commutation is achieved using a countercurrent pulse injection by the capacitor–capacitor pair structure. Second, metal-oxide varistors (MOVs) are disconnected from the power line when SSCB is off, which solves the reliability issue due to the MOV degradation and enhances the voltage utilization rate of the main switch. Third, benefiting from the capacitor–capacitor pair structure, reliable reclosing and rebreaking are obtained for practical applications. Experiments are conducted on a 400 V/120 A prototype to validate the proposed Y-SSCB. The peak voltage on the main and auxiliary thyristors reaches 773 and 400 V, respectively. Also, the peak voltage on the auxiliary capacitors pair reaches 740 and 400 V. The Y-SSCB achieves a fast reaction time of 80 μs in interrupting 120 A short-circuit fault current. [ABSTRACT FROM AUTHOR]

DC series arc faults are known as a great threat to photovoltaic (PV) systems. Due to component aging and the high level of dc voltage, the occurrence of dc series arc fault is a serious concern in PV generation units. This article deals with driving effective dc series arc models from the original Nottingham arc model using the recorded practical data in a PV system. The original Nottingham arc model has three constant parameters and suffers significant inaccuracy for modeling the series arc faults. To avoid the inaccuracy in the modeling, at first, a Nottingham model is developed that is relevant to voltage and current of the fault with three parameters including one constant model order for exponents of the current and two time-series coefficients. Also, to further improvement in the model's accuracy, a two-fold Nottingham model is proposed that is relevant to voltage and current of the fault with five parameters including two constant model orders for exponents of the current and three time-series coefficients. Finally, a full-time-variant Nottingham model is proposed that mathematically contains three time-series parameters including one time-variant model order of the current exponent. In the full-time-variant Nottingham model, the optimal parameters corresponding to each sliding window of data are utilized. In all the proposed models, the arc coefficients are estimated using a new formulation using the least-squares error technique. Verifying the effectiveness of the proposed models through actual data, the accuracy of the proposed models is compared with the original Nottingham model. [ABSTRACT FROM AUTHOR]

This paper presents the DC fault transient study of a meshed DC grid with high-temperature superconducting (HTS) HVDC cables to integrate offshore wind power. A four-terminal meshed DC grid model with a ±100 kV DC voltage rating is developed. DC circuit breakers (DCCBs) are implemented in the DC grid to deal with DC cable faults. To conduct the fault transient study, the fault scenarios with different fault locations and protection delays are studied. The sensitivity study versus different DC fault locations reveals that the faults on the faulted cable will not cause the quenching of healthy cables. The sensitivity study considering different DC fault protection delays demonstrates that the HTS cables have a current-limiting effect and the long delay of DC fault protection does not result in large fault current and the quenching of healthy cables. Extensive simulations in PSCAD/EMTDC validate the founding. [ABSTRACT FROM AUTHOR]

The single-phase to ground fault (SPGF) is very common in power grids. To decrease the fault’s influence on the power supply’s reliability, the neutral point is usually grounded via the Petersen coil, significantly reducing the outage rate. Nevertheless, this coil would weaken the fault current and make the faulty line identification much more difficult. To address such an issue, an identifying method for the faulty line is proposed in this paper based on the detection of an extremely low frequency current(ELFC), after analyses are made on the electrical signal’s characteristics when the fault exists based on a common physical model of a medium-voltage distribution system. Then, to coordinate with this method, a set of devices are developed to accurately measure the ELFC and ensure feasibility. At last, a simulation and an experiment are conducted, and the results prove this method’s validity in the identification of a faulty line. [ABSTRACT FROM AUTHOR]

The article analyses design options for a practical 2-10 kV, 1-2 kA LC DC Circuit Breaker module. The impact of multiple series break points with the ultra-fast disconnector is explored in depth using analytical model and 5 kV, 4-break hardware prototype. The experimental testing demonstrates that the arc voltage increases proportionally with each breaking point, and this increases current that can be internally commutated. Further analysis of the impact of delays between break points is presented. Modeling and testing with 4 different capacitors of 1-10 kV concludes that larger capacitances increase commutating current, but relationship is complex and non-linear. Parallel connection of breaking points is also analysed. Successful breaking of DC fault current is demonstrated on hardware for multiple cases including 930 A with 800 $\mu$ F, 6.5 kV, capacitor using a 4-break disconnector. The tested DC CB is of mechanical type, which inserts a capacitor in series in a very short time of around 290 $\mu$ s, and full contact separation is achieved 1.5 ms after the trip signal. It is recommended that the module design should primarily consider maximizing the number of break points in series. [ABSTRACT FROM AUTHOR]

The current limiting function enables the solid-state circuit breaker (SSCB) to have proper protection coordination. It allows sustained overcurrent for a certain period while preventing the fast fault current increase in dc systems. For the conventional method of using switches alone to limit the current, the high loss results in a short withstand time and low current limiting capability of the SSCBs. In this letter, a control strategy is proposed to utilize the energy absorption component to handle the major part of the energy during the current limiting stage to increase the current limiting capability for series-connected SSCB switching cells. The proposed method is experimentally verified to have more than 3X current limiting withstand time compared to the conventional control strategy in a case study. [ABSTRACT FROM AUTHOR]

In this article, online short-circuit estimation of permanent magnet synchronous motors (PMSMs) are presented, which is essential for postfault ac drive operations. For this purpose, initially, the PMSM model with interturn short-circuit fault (ITSC) is extended to cover motors with saliency. By utilizing ITSC model voltage equations and voltage reference equations, the amplitude and phase relationship between short-circuit current and the phase reference voltage is established. In the next step, second harmonics in the reference voltage and feedback current are used to extract the short-circuit current information. In order to efficiently use ac drive microcontroller bandwidth, the proposed short-circuit current estimation method is executed after the ITSC fault is detected, not continuously. Instead of running the proposed short-circuit current estimation continuously, it is reasonable to run it after an ITSC fault detection to efficiently use ac drive microcontroller bandwidth. Therefore, two intermediate steps, a simple ITSC fault detection and severity estimation algorithms are proposed as well. The proposed technique can estimate the fault current and severity without the knowledge of fault location and valid for all PM motors. The findings are experimentally tested using two PMSMs to demonstrate the effectiveness and practicability of the proposed estimation technique. [ABSTRACT FROM AUTHOR]

Despite the high performance of high-voltage direct current circuit breaker (CB) technology, its high cost restricts its further development. Thus, this article proposes a high-efficiency protection circuit for solid-state switches (SSs) that integrates semisoft switching and voltage limiting functions. The protection circuit also does not resonate with the system inductance which in turn does not affect the reclosing operation of the CB. The novel SS scheme reduces the cost and simplifies the layout of the SS. The special constraints for the parameter design of power electronics, gaps, and metal oxide varistors (MOVs) are proposed in this article for the first time, and a parameters design method that solves the transient power shock and voltage spike problems during the large current breaking process under multiple constraints is formed. Finally, an SS prototype is developed to verify the feasibility and the strong surge and turn-off ability of the novel SS and to test the robustness of the series-connected gapped-MOV circuits. [ABSTRACT FROM AUTHOR]

The multiterminal dc (MTDC) grid plays an important role in large-scale power transmission and renewable energy integration owing to its excellent performance. However, there are still some problems existing in the MTDC grid, such as difficult fault current interruption and current flow control, which impedes its development. Currently, the mentioned two problems can be separately solved by hybrid dc circuit breaker (HCB) and current flow controller (CFC). However, when configured separately, they are expensive and have large footprints. Therefore, this article proposes a multiport hybrid dc circuit breaker (MHCB) with current flow control capability. The HCBs near the same dc bus are first integrated into a single MHCB and then novel CFCs are embedded into the MHCB to replace the load commutation switches. Compared with the existing MHCBs, the proposed topology shows advantages in the aspects of implementation cost, power loss, and operation speed. The operation principle is analyzed and the basis for parameter design is given in detail. The effectiveness of the proposed topology is verified by extensive simulations and experiments. Besides, the proposed MHCB is compared with the existing solutions. [ABSTRACT FROM AUTHOR]

The current-limiting performance of the smoothing reactor is weak. The traditional saturated core-type fault current limiter (TFCL) is better, but will cause the dc circuit breaker (DCCB) to endure high overvoltage, energy absorption and also increase the current fall time. When DCCB recloses on the permanent fault, the whole dc system will face a harmful second shock that cannot be solved effectively by TFCL. To solve the above problems, a secondary active limiting fault current limiter (SAFCL) topology is proposed. It can reduce the DCCB overvoltage and energy absorption greatly. Meanwhile, it can store fault energy and uses it to active limit the current when the DCCB recloses on the permanent fault. The secondary active current limiting effect is better than the first and the DCCB breaking electric stress is lower than the first. First of all, the topology and principle of the SAFCL are introduced. The main electromagnet parameters are then analyzed. The performance of different FCLs are simulated comparatively to verify the superiority of the SAFCL. Final, the experiment is carried out, the comparison with simulations verifies the feasibility of the SAFCL. [ABSTRACT FROM AUTHOR]

Unique fault behaviors of renewable energy sources (RESs) may lead to the misoperation of traditional pilot protection. To cope with this issue, this article proposes a new pilot protection method using the improved Euclidean distance. For normal operation or external faults, the currents on both ends are completely opposite, so the Euclidean distance of current absolute values on both ends is equal to 0. However, it will be much larger than 0 for internal faults because transient currents on both ends will have a big difference at this time. Therefore, internal and external faults can be detected reliably. In order to facilitate the setting calculation, the Euclidean distance is normalized, and a stability factor is introduced to avoid invalid calculation results. The proposed method can be applied to different RES types and different fault ride through strategies. Meanwhile, it can withstand larger fault resistance and noise interference. Compared with other methods using the RES fault currents, this approach can operate correctly without any additional criteria when the circuit breaker recloses on a permanent fault or RESs output a low power. PSCAD simulation and real-time digital simulator experiment verify this method. [ABSTRACT FROM AUTHOR]

The current-limiting inductors are usually installed in the multi-terminal dc grid to limit the fault current rising speed. However, they will increase the energy dissipation pressure and fault isolation time of the dc circuit breaker, which puts forward higher requirements on the capacity of arresters in hybrid dc circuit breaker and the heat dissipation of grid equipment. Therefore, an improved integrated hybrid dc circuit breaker is proposed in this brief for applications in the multi-terminal dc grid. Compared with the fault isolation solution based on existing integrated hybrid dc circuit breakers, the proposed breaker has slightly higher cost of semiconductor switches but significantly reduced arrester capacity requirement and faster fault isolation speed by bypassing the inductance components. Extensive electromagnetic simulations and physical experiments verify the effectiveness of the proposed device. [ABSTRACT FROM AUTHOR]

In this article, proof of concept of interturn short circuit (ISC) detection and shorted turns current reduction with d-axis current injection along with torque compensation is shown. This article evaluates the feasibility of implementing the detection and compensation of an ISC in an interior permanent magnet synchronous machine fed by a two-level voltage source inverter (VSI). First, the proposed method detects the ISC fault using a current observer capable of detecting a specific disturbance related to the ISC. Then, once the ISC is detected, the possibility of compensating for an ISC is evaluated. With a two-level VSI, the options for fault compensation are somewhat limited; however, a significant reduction in the shorted turns current can be achieved by adequately injecting d-axis current to cancel out the magnetic flux from the permanent magnet. Moreover, a small q-axis current can be injected with minimum flux to use the saliency torque. Experimental results obtained from a prototype manufactured specifically for ISC testing proof the feasibility of the proposed technique. [ABSTRACT FROM AUTHOR]

Global electricity generation by renewable energy sources and the electrification of the transportation system are gaining more importance to mitigate climate change. The dc system plays a significant role in these developments. To protect dc systems, dc circuit breakers with advanced technology are required that are fast and reliable. Various solid-state dc circuit breakers, such as $Z$ -source and $T$ -source circuit breakers, have been presented in the literature to meet the dc system demand; however, these topologies suffer from limitations such as high conduction loss, complexity in design, no physical isolation, and presence of negative current flow in load during reclosing. To overcome the aforementioned limitations, a bidirectional solid-state dc circuit breaker (BD-SSCB) that detects the overload or short-circuit faults and responds instantaneously to mitigate the fault current has been proposed in this article. The controllable shutoff function is much needed in applications where sudden load change occurs continuously during the normal operation, such as varying acceleration of an electric vehicle. The proposed BD-SSCB is validated using spice simulations and hardware experiments with varying system parameters for a system rating of 400 V/10 A. [ABSTRACT FROM AUTHOR]

This article presents a new method for estimating the fault location in a voltage-source-converter-interfaced dc system. The proposed dc fault location estimation method evaluates the distance from the fault point to the dc line terminal by estimating the line inductance; hence, it is designated as $L$ location. Since the fault impedance usually only includes resistance, the proposed $L$ location is less affected by the variation of fault resistance. In addition, the ripple caused by the distributed capacitive discharge is excluded from the dc line current when the proposed $L$ location is applied in the dc system with the distributed-parameter transmission line. The cubic curve-fitting method is used to reconstruct the current signal based on the least squares method. The effectiveness of the proposed $L$ location is verified with an OPAL-RT-based multiterminal dc (MTDC) system and experimental point-to-point and MTDC systems. The comparison with the impedance estimation, the voltage-traveling-wave-based location, and the differential and directional protection substantiates the integral performance of the proposed method [ABSTRACT FROM AUTHOR]

Varistors are widely used in dc circuit breaker (DCCB) application as fault energy absorption elements, which is not an application the varistors are originally designed for. The fault energy stress adversely impacts the varistor lifetime, thus affecting DCCB reliability and performance. This article presents two methods for choosing the appropriate varistor type and arrangement in a DCCB by linking 1) varistor lifetime and 2) DCCB component- and system-level parameters. The first method uses a set-based design approach with random Latin hypercube sampling to narrow down viable solutions. In comparison, the second method relies on a point-based design approach and proposes an integer programming problem to optimize varistor lifetime. Both procedures are applied to the selection of varistors in 1) a 12 kV DCCB rated for 2-kA nominal current and a peak fault current of 15 kA and 2) a reduced-scale 1.2-kV DCCB hardware prototype, using publicly available varistor data. The article shows the possibility of design for varistor lifetime in DCCB applications, and concludes that both selection procedures provide consistent, reasonable, and verifiable results. However, the results also pinpoint the significant gaps and call for future work on impulse stress versus lifetime relationships for DCCB varistors. [ABSTRACT FROM AUTHOR]

Flexible direct current (dc) distribution networks are the development trend for the future distribution system. However, the protection and control of these networks are vulnerable to complicated dc faults, accurate fault analysis is required. In this article, we propose a three-stage transient fault analysis method to improve the accuracy of fault characteristic calculation for the voltage source converter based dc distribution network with multi distributed generators, which can unify and simplify the calculation process of different transient fault stages. An impedance parameter decoupling approach is proposed based on the dc line parameters, which can avoid the influence of the coupling impedance on fault response. The decoupled equivalent fault circuits are established for accurate fault analysis with flexibility and independence. In addition, a three-stage fault analysis is proposed, which is able to unify the calculation process. Finally, numerical simulations based on PSCAD/EMTDC have been carried out, which well demonstrates the effectiveness of the proposed impedance decoupling approach and the accuracy of the proposed method for fault analysis. Compared with the traditional fault analysis without decoupling, the proposed method stands out the conciseness and correctness. [ABSTRACT FROM AUTHOR]

When a fault occurs on the dc side of the voltage source converter based high voltage direct current (VSC-HVDC) transmission system, the fault current rises quickly due to the low damping of the dc system. Using a dc fault current limiter (DC-FCL) to limit the rise of the fault current can significantly reduce the breaking requirements of the DCCB. A topology of a bidirectional active dc fault current limiter (BA-FCL) based on coupled inductor is proposed in this paper. No expensive full-controlled power electronic devices are used in this topology. Only a few half-controlled power electronic devices are used to achieve active control of the current limiting unit. Compared with many topologies of current limiter at present, the fault current limiting effect of BA-FCL is improved significantly while the cost, volume, topology complexity, and control complexity are reduced. The stress analysis and parameter design of the proposed current limiter are carried out. Finally, the simulation case study and hardware experiment are implemented to verify the good economy and current limiting performance of the proposed topology. [ABSTRACT FROM AUTHOR]

Due to the complex structures and fault conditions, accurate fault sensing of the underground distribution cables is a difficult task. The distribution automation system (DAS) and fault indicator system (FIS) are only applicable to the severe faults. In addition, the current DAS and FIS are all based on the centralized data processing system (CDS), increasing the communication pressure and data processing time of the main station. Considering the advantages of edge computing, this paper investigates using the grounding line currents to sense the fault in distribution cable networks. First, an edge computing based fault sensing system (ECS) is designed. The equivalent time-domain distribution cable models considering multi-conductor mutual couplings are then established in both normal and fault cases. The time-domain features of the cable grounding line currents prior to and after the fault are analyzed to create the fault detection criterion. Combining the network topology, locations of the measurement units (MUs), and direction factor of the ground line current, a space matrix based algorithm is created to achieve fault cable section location at edge. Finally, a distribution cable network is created by PSCAD/EMTDC. Various simulations are conducted to validate the effectiveness and robustness of the algorithm. [ABSTRACT FROM AUTHOR]

Current transformer (CT) saturation is one of the dominant causes of relay protection devices’ malfunctions, which pose a threat to the safe operation of the power system. To address this problem, we propose a hybrid physical model- and data-driven method. The method firstly detects the CT saturation and then compensates it to reproduce the real waveform. Considering the multi-factor and strong nonlinearity of CT saturation, a data-driven model, namely the Fully Convolutional Network (FCN), is built to detect the operation status of CT. As for the compensation, a physical model of short-circuit current is used for its conciseness and universality. Through tactfully integrating the data model and the physical model, the proposed method is endowed with two major merits: the arduous adjustment of universal thresholds and parameters in existing methods is avoided, and the deficiency in generalization and interpretability of the data-driven method is assuaged. Simulation and experimental results verify the effectiveness of the proposed method. Furthermore, its application potential to future protection is explored. [ABSTRACT FROM AUTHOR]

Piezoelectrically actuated fast mechanical switches provide a low-loss conduction path in hybrid circuit breakers for protecting medium-voltage direct-current systems. As the desired actuation speed approaches the driving limit of a piezoelectric actuator, excessive vibration starts to dominate its underdamped travel curves, resulting in insulation failures and delayed switching in the fast mechanical switch. To improve the underdamped travel curves into critically damped travel curves, several switching motion control schemes with active damping filters are proposed in this paper. The switching motion controllers are based on an electromechanical model of a fast mechanical switch with experimentally identified parameters. According to hardware implementation tests, the proposed closed-loop control schemes optimized the switch travel curves with a 56% reduction in the undershoot and a 75% reduction in the settling time. Equipped with the critically damped travel curves, the piezoelectrically actuated fast mechanical switch is better suited for sequential submodule operations to reduce the interruption time, the peak current and the fault energy to be absorbed in hybrid circuit breakers. [ABSTRACT FROM AUTHOR]

Due to limited amplitude and controlled phase of current supplied by inverter-interfaced renewable power plants (IIRPPs), the IIRPP-side distance protection of lines connected to IIRPPs fails to detect the fault location accurately, so it may malfunction. The composite sequence network of a line connected to an IIRPP during asymmetrical faults is analyzed, and an adaptive distance protection based on the analytical model of additional impedance is proposed in this study. Based on open circuit property of negative-sequence network at the IIRPP-side, the equivalent impedance of power grid and current flowing through fault point are calculated in real-time using local measurements, which are substituted into the analytical model of additional impedance to calculate fault location. In the case of negative-sequence reactive current injection from IIRPPs during asymmetrical faults, the error of calculating fault point current from local measurements is analyzed and corrected to ensure reliability of the proposed protection. The proposed protection alleviates the effect of fault resistance in a system with weak sources. In addition, the proposed protection can adapt to different grid codes (GCs), the operation mode change of the power grid, and the capacity change of the IIRPP. PSCAD/EMTDC test results verify the effectiveness of the proposed protection. [ABSTRACT FROM AUTHOR]

The classical electromagnetic time reversal (EMTR) fault location method in power systems requires multiple simula-tions in the backward step, assuming different guessed fault loca-tions along the line. This process can be time consuming especially when a high location accuracy is desired, as it may require a significant number of guessed fault locations. To cope with this issue, the concept of EMTR in mismatched media has recently been introduced, allowing reducing the backward simulations to a single run and, thus, substantially improving the computation efficiency of the EMTR-based fault location technique. In this paper, we present a detailed study of the mismatched-media-based mirrored minimum energy property. This property has been applied in a few recent studies but never been theoretically studied and rigorously demonstrated. First, we infer a transfer function that relates the fault source to the voltage along the line resulting from back-injecting the time-reversed transients measured at a given observation point. We present a theorem according to which, at the fault switching frequency and its odd harmonics, the mirror-image point of the fault location with respect to the line center corresponds to a local minimum of the squared modulus of the transfer function. Then, it is proved that the mirrored minimum energy property is a corollary of this theorem. Based on these theoretical findings, we propose an algorithm that utilizes the reversed-time voltage energy as a fault location metric in the frequency domain. We further advance a data-driven strategy to maximize the computation efficiency of the fault location procedure. The applicability and robustness of the proposed frequency-domain fault location metric are numerically and experimentally validated. [ABSTRACT FROM AUTHOR]

The full-cycle discrete Fourier transform (FCDFT) is commonly used to estimate phasors in numerical relays because of its immunity to harmonics and accurate identification of a decaying dc component (DDC) in a fault current. For fast protection of power systems, it is necessary to speed up the phasor estimation by using a data window below one cycle. The conventional least squares (LS) methods below one cycle approximate the DDC as the first several terms of the Taylor series expansion, which degrades the phasor-estimation accuracy. This paper proposes an LS method that uses Fourier analysis for approximation of the DDC to speed up phasor estimation without accuracy degradation. The phasor-estimation accuracy of the proposed method is investigated for the data-window length in simulations using synthetic data of fault currents containing DDC, harmonics, and measurement noise. The phasor-estimation speed is also investigated with respect to the delay of the antialiasing filter in the numerical relay. The proposed method is compared with the conventional LS and FCDFT methods in simulations using synthetic fault-current data. The feasibility of the proposed method is demonstrated through the phasor estimation of simulated transmission-line faults. [ABSTRACT FROM AUTHOR]

The mixture unidirectional solid-state circuit breaker (SSCB) based on transistor-based devices [i.e., IGBT-based line commutation switch (LCS)] and the thyristor-based devices can combine their respective advantages, however, the conduction loss and cost may increase significantly when expanding to a bidirectional topology because the number of IGBTs had to be doubled with the expansion of unidirectional LCS structure to bidirectional LCS structure composed of two groups of IGBTs in reverse series. In this letter, a full-bridge mixture bidirectional SSCB (FB-MSSCB) requiring only one unidirectional LCS is proposed, the required number of IGBTs can be reduced by at least half compared with other mixture bidirectional SSCB topologies in the same voltage and current level applications. As a result, the FB-MSSCB has advantages of more economic design and higher efficiency, the conduction loss can be reduced by at least 23.3% in 10 kV MVdc system, while retaining other advantages of mixture bidirectional SSCB, such as the ability to actively interrupt bidirectional fault currents, without introducing additional thyristors, charging power supply, and charging strategy. The working principles and designing guidelines is presented in detail. The feasibility and effectiveness are verified by experiment results and comparative analysis. [ABSTRACT FROM AUTHOR]

The hybrid modular multilevel converter (HMMC) composed of half-bridge (HB) and full-bridge (FB) submodules (SMs) is an alternative to the FB-modular multilevel converter (MMC) with lower loss and cost. However, the HMMC's maximum reverse-biased voltage (RBV) is lower than the FB-MMC, so does the dc fault clearing capability (DCFCC). Reduced RBV will prolong the fault clearing time, especially when the dc side inductance is large. In this letter, an auxiliary circuit is proposed for HMMCs, which can change the fault current paths and enable both HB- and FB-SMs to participate in the fault clearing. Thus, the maximum RBV of the HMMC is increased to be equal to an FB-MMC. Moreover, the proportion of FB-SMs can be reduced. With the auxiliary circuit, the DCFCC of the HMMC is enhanced with the reduction of the power losses and semiconductor costs. Simulations and scaled-down experiments validate the proposed method. [ABSTRACT FROM AUTHOR]

Inverter-interfaced renewable energy sources (IIRESs) are typically controlled during fault conditions to meet fault ride-through (FRT) requirements, e.g., reactive current generation (RCG) requirements specified by grid codes (GCs). However, fault currents generated by inverters are different from the traditional sources, i.e., synchronous generators. Consequently, phase selection methods (PSMs) used by protection relays could suffer from erroneous fault type classification. This paper develops a dual current controller (DCC) that regulates the inverter's negative- and positive-sequence currents to simultaneously meet phase selection and RCG requirements. First, the negative-sequence-current angle is obtained based on the angles of both zero- and positive-sequence currents to enable a correct operation for phase selection. Then, the positive-sequence current angle is adjusted to reach a trade-off between RCG requirements and phase selection achieved by the negative-sequence current. Lastly, the reference currents of the IIRES are generated in the stationary frame without violating the inverter's current limits. The proposed DCC supports the grid voltage by meeting the RCG requirements and enhancing the grid reliability and resilience by enabling correct phase selection. Comprehensive time-domain and real-time simulation verify the precise operation of the proposed DCC under various fault conditions and GCs. [ABSTRACT FROM AUTHOR]

The dc circuit breaker plays an important protection role in the dc distribution systems. Hybrid dc circuit breaker (HCB) offers low conduction losses and reasonably fast response times. In this article, a high power density, modular, and scalable power electronic interrupter (PEI) design is introduced for medium-voltage (MV) HCB platforms. Following this concept, the single low-voltage module is first investigated in terms of the high pulse current ratio and the voltage clamping circuit. After the comparison and test among different devices, a compact module with 1.7-kV discrete IGBTs are selected as main switches. While the voltage clamping circuit is carefully designed to guarantee no tail current bump and sufficient turn-off voltage margin. Next the whole system with series modules is optimized on the aspects of the turn-off strategy, power supply structure, and layout of modules. An improved staged turn-off scheme is proposed, which can not only reduce the peak current and total metal oxide varistor (MOV) energy, but also help balance the MOV energy distribution. A 12-kV and 1-kV breaking capable PEI was demonstrated based on the proposed PEI design, achieving a peak power density of 7.4 kW/cm3, much higher than the IGBT module-based solution. The breaking capability and effectiveness of the modular PEI is demonstrated in a 6-kV MVDC HCB device. [ABSTRACT FROM AUTHOR]

One of the major challenges in evacuating power from the offshore renewable energy source is reducing the number of equipment involved in the energy conversion process. In the strategy presented in this article, the output of a permanent magnet synchronous generator coupled with a wind turbine is converted to a low voltage DC by an AC–DC converter and then directly connected to a Medium Voltage Direct Current (MVDC) corridor using a new fault tolerant soft switched high gain DC–DC converter. During the fault in the MVDC corridor, the DC–DC converter is blocked forcing the fault current to zero, the faulty MVDC corridor is bypassed using the simple DC disconnectors, and then the DC–DC converter is connected to the healthy MVDC corridor. In this article, the efficacy of the proposed scheme is discussed in detail and substantiated through extensive simulation studies done in PSCAD/EMTDC. The theoretical and simulation analysis is also verified by experimental results. [ABSTRACT FROM AUTHOR]

The operation of multimicrogrids (MMGs) can cause significant impact on power system network, especially changes in level and direction of fault current. The fault current level may exceed rating of existing directional overcurrent relays (DOCRs) that lead to sympathetic tripping or fail to trip DOCRs in the network. It is expensive and extremely challenging to upgrade or replace the existing DOCRs in the network. If not properly addressed, this issue may hinder the deployment of MMGs in to the network. Hence, this article proposes a robust protection scheme for DOCRs coordination in MMGs without replacing existing DOCRs in network. First, the proposed scheme calculates optimal settings of DOCRs in all stand-alone microgrids of MMG during islanded mode. Then, optimal values of fault current limiters are obtained using calculated optimal settings. The main advantage of proposed scheme is that it provides one set of DOCRs settings valid for all operating modes of MMG. In this work, the DOCRs coordination problem is formulated as nonlinear problem and solved using proposed hybrid approach symbiotic organisms search (SOS) and nonlinear programming (NLP). The initial solution is determined by SOS and final solution is obtained using NLP. Further, the proposed scheme is examined during gird connected and islanded modes in two different configurations (series and parallel) of MMG, which are not stated in previous literature. Finally, simulation results are validated using numerical relay and real time digital simulator, which are interfaced through voltage and current amplifier to execute hardware-in-loop test bed. [ABSTRACT FROM AUTHOR]

High voltage direct current (HVdc) power transmission systems do not encounter any natural zero crossing unlike the ac systems, and hence, the dc circuit breakers employed should be fast-acting and reliable to ensure safe operation. Circuit breakers (CBs) that have fast response time with lower energy loss dissipation are required for subsea HVdc transmission systems. This article investigates the performance of various CB topologies, including ultrafast coupled inductor hybrid CB (CIHCB) topology without and with the integration of resistive-type superconducting fault current limiter (R-SFCL) for a 100-kV, 100-MW HVdc transmission systems. It is found that the addition of R-SFCL with 1.7-ms response time decreases the peak current through the breaker and, hence, the power dissipated in the CB during short-circuit fault conditions. Thus, the rating of CB can be significantly decreased with the proposed topology. Furthermore, a comparison of power loss in CIHCB with the existing topologies, such as mechanical CB, resonant CB, and HVdc-hybrid CB, are also presented in this article. [ABSTRACT FROM AUTHOR]

High voltage DC transport at long distances represents an opportunity for wider use of superconductors. In particular, the second generation of high temperature superconductor tapes produced in form of coated conductors (CC) offers a unique solution for protecting a high-capacity connection against fault currents. In the resistive superconducting fault current limiter (R-SFCL), the CC tape would emerge as a substantial resistance in case of overcoming its critical current, Ic. Non-uniformity of Ic along the CC length is a common issue requiring attention. Because of highly nonlinear current/voltage dependence, the spot with critical current Icmin < Ic could transform into the hot spot with rapid rise of local temperature. Due to its small dimension, it would not create an observable voltage at the device terminals, thus may escape attention of a quench detection system. We have investigated the mechanism of hot spot creation at the DC currents between Icmin and Ic, and the analytical formulas have been derived predicting the limits of stable operation. Now we extend the analysis to the case of the limitation event, when for a fraction of second the current exceeds also the Ic. It is desirable that the temperature rise happens along all the conductor length, leading to a quick reduction of transported DC. Numerical modelling has been utilized to analyze such an event, and a simplified analytical model has been developed to predict the range of currents causing the formation of hot spots. [ABSTRACT FROM AUTHOR]

Numerous research efforts are devoted to attain high performance and strong fault tolerance for the machine drives in safety critical applications, though the two aspects are conflicted in most cases. In this paper, a novel triple 3-phase PMA-SynRM with star-delta connected windings is proposed. The star-delta winding could produce a higher fundamental magneto-motive force and lower spatial harmonics than the conventional star winding. Therefore, it exhibits higher torque, lower torque ripple and lower iron loss, enhancing the healthy performance. In addition, the coils whose turn fault current is the highest are arranged in the inner delta part which provides circulating current path. It is demonstrated that the proposed winding solution reduces the fault current by 55% and the fault turn copper loss by 65%. Hence, the machine's fault tolerance is significantly improved. The machines with the star winding and star-delta winding are studied by detailed finite element calculation and experimental tests under various operation modes. Both the simulation and test results confirm that the proposed star-delta winding machine owns higher performance and stronger fault tolerance than the conventional star winding machine. Thus, it becomes a more competitive candidate for the high reliability drives. [ABSTRACT FROM AUTHOR]

This article proposes a novel ultra-fast self-powered bidirectional solid-state circuit breaker (SSCB) with voltage overshoot suppression that uses gallium nitride switches with very low conduction losses. This SSCB can be used in low and medium ac/dc networks for both short-circuit protection and overcurrent protection. An exhaustive methodology for RCD snubber design applied to SSCBs is provided. A comprehensive review of the technical literature is presented exhibiting that the proposed SSCB reduces conduction losses and detection time in comparison with other similar SSCBs. The performance features of the proposed SSCB are verified through the functional tests that are carried out employing a hardware-implemented prototype. Experimental results confirm that our proposal is able to detect and process the short-circuit failure in 282 ns; the authors have not found any faster results in the literature. [ABSTRACT FROM AUTHOR]

High-voltage direct current (HVDC) circuit breaker development and deployment strongly depend on the testing process, which ensures that the HVDC circuit breakers will satisfy design requirements. This article presents an HVDC circuit breaker test bench circuit configuration that can provide controllable large output currents to simulate different fault conditions for the current breaking test and high output voltage for the dielectric withstand test. The current breaking test circuit is based on multiple cascaded power converters connected in parallel to provide the necessary output current capability. Each cascaded power converter is composed of multiple cells that are operated by a phase-shifted pulsewidth-modulated signal for greater controllability and higher quality of the output waveform. The dielectric withstand test circuit is a simple high-voltage source with a low power rating that can also be used to charge the test bench and the internal circuitry of the circuit breaker that is to be tested. The proposed test bench ensures that fault conditions can be replicated accurately and offers greater flexibility by being able to test mechanical, semiconductor-based, or hybrid HVDC circuit breakers with different current and voltage ratings on the same hardware without any changes. The idea and the operating principle of the proposed test bench are verified experimentally on a downscaled system that consists of three cascaded power converters connected in parallel with three cells per cascaded power converter and with a total equivalent switching frequency of 92.5 kHz. [ABSTRACT FROM AUTHOR]

DC circuit breakers (DCCBs) play a significant role in obtaining the reliability and stability of DC power systems. Selective and fast isolating of faults minimizes the power supply outages to end electricity users and protects the power converters implemented in the DC system. During the last decades, DCCBs have been deeply investigated in industry and academia. There has been impressive progress in terms of efficiency, response time, power-density, lifetime, and electrical operating ratings. Introducing wide bandgap (WBG) devices further has motivated researchers to propose more efficient and novel topologies. This paper provides a point of reference and a background review for DCCBs from novel aspects, fulfilling absent parts in the literature. The elaborated subjects include current commutation circuitry, DCCBs trip-curves developments, newly added functions to DCCBs, as well as marketing analysis. The advancements of DCCBs are surveyed and development needs are recognized. This paper aims to identify the future research needs of DCCBs for emerging DC power systems. [ABSTRACT FROM AUTHOR]

This article proposes a fault detection scheme for modular multilevel converter-based multiterminal dc (MMC-MTdc) girds based upon a resistive-type superconducting fault current limiter (RSFCL). By analyzing the characteristics of the currents through the faulted and healthy lines in an MMC-MTdc system, the theoretical foundations of the scheme are established. This yields a fault detection scheme with fault identification, fault pole discrimination, and high-resistance tolerance abilities. Extensive simulations confirm that the proposed detection scheme can identify the metallic short circuit fault within 1 ms, with the ability to promptly detect faults with high resistance in less than 3 ms taking the communication delay into consideration. This method does not cause any mal-operation of dc circuit breakers as a result of faults on adjacent lines and power order changes. The proposed scheme has immunity to noise and provides full-length protection of the protected transmission line. Simulation results show significant suppression of both the amplitude and the rate-of-rise of the fault current during the fault detection process, which enhance the reliability and stability of the protected grid. [ABSTRACT FROM AUTHOR]

This article investigates the relationships between the pole-to-pole fault current and the topology in the bipolar voltage sourced converter (VSC)–high-voltage dc (HVdc) grid. Based on the improved high-frequency equivalent model, it is found that the pole-to-pole fault current value is significantly influenced by the grid topologies, which is different from the situation in symmetrical monopole dc grid. It is also found that only the adjacent converters and the subadjacent converters of the fault lines will impact the fault currents, while the other converters with longer electrical distances basically have negligible contribution to the fault current. According to above mechanism, the simplified index is also proposed in this article to evaluate the fault current level of dc grid efficiently when its topology varies. The proposed index can make evaluations by simple calculations between different topologies and avoid solving complex differential equations one by one when pole-to-pole fault occurs at different lines. Based on the practical evaluation index, the genetic algorithm is used to optimize the dc grid topology to limit the fault current level. Finally, the simulation verification is performed based on the six-terminal bipolar VSC–HVdc grids, and some suggestions on topology design are given. [ABSTRACT FROM AUTHOR]