Search

This paper presents the design of a 6-bit Ku-Band phase shifter implemented in 0.13um CMOS technology. The RC polyphase filter and inductors are used as the load of a differential amplifier to achieve high gain of the phase shifter. And it can suppress the phase error of IQ signal caused by non-ideal differential signal and this function is verified by simulation. The whole phase shifter adopts the actual components based on 0.13um CMOS technology. The results show that the maximum rms phase and gain errors are 3° and 0.46 dB for 64 states at 10-20 GHz. And the maximum voltage gain exceeds 11dB at 15GHz.

In this paper, a broadband high-efficiency power amplifier (PA) with a Class-J mode matching network is proposed. The output power can be improved by employing a stacked structure, additionally, the Class-J theory provides a superior method to broaden the operating frequency range among X-band with high efficiency. And the output matching network is simplified especially, exploiting the wideband nature of continuous mode Class-J PA. The circuit is fabricated in a 130 nm standard CMOS process. The power added efficiency (PAE) is greater than 20% over the range of 8.1~11.1 GHz and reaches the maximum value of 29.7%, the power gain reaches more than 12 dB over this frequency range. The saturated output power is 20.2 dBm when the input power is 5 dBm.

In this work, we propose and demonstrate a multi-layer 3-dimensional (3D) vertical RRAM (VRRAM) PUF with in-cell stabilization scheme to improve both cost efficiency and reliability. An 8-layer VRRAM array was manufactured with excellent uniformity and good endurance of >107. Apart from the variation in RRAM resistance, enhanced randomness is obtained thanks to the parasitic IR drop and abundant sneak current paths in 3D VRRAM. To deal with the common issue of unstable bits in PUF output, in-cell stabilization is proposed by first employing asymmetric biasing to detect the unstable bits and then exploiting reprogramming to expand the deviation to stabilize the output. The bit error rate is reduced by >7X (68X) for 3(5) times reprogramming. The proposed PUF features excellent resistance against machine learning attack and passes both National Institute of Standards and Technology (NIST) 800-22 and NIST 800-90B test suites.

RRAM suffers from poor retention with short-term memory time when using low compliance current for programing. However, the short-term memory time exhibits ideal randomness, which can be exploited as an entropy source for physically unclonable function (PUF). In this work, we demonstrated a novel PUF utilizing the stochastic short-term memory time of oxide-based RRAM. The proposed PUF was implemented on a 256Kb HfO 2 /WO x bilayer RRAM test chip in 0.13μm logic process. The RRAM PUF is capable of regenerating >1020 times after 10 years@115°C and the bit error rate (BER) remains

This paper presents an 8 to 12 GHz broadband power amplifier with high linearity and efficiency. Large signal linearization methods are employed to improve the linearity. Sweet point control method is adopted to reduce the intermodulation products, meanwhile the active feedback technique is used to improve the 1-dB compression point. Moreover, an improved broadband matching network is proposed to expand the bandwidth of the power amplifier. The power amplifier is designed in 130 nm CMOS process. Post simulation results show that the power amplifier has an average power gain of 10.6 dB, a max power added efficiency of 29.6%, an output compression point of 13.5 dBm at center frequency, whereas the DC power consumption is only 19.2 mW.

A X-Band linearized low noise amplifier is presented in a 130 nm CMOS process. The modified post-distortion technique is employed to reduce the extra power consumption and improve the linearity. In this design, the LNA with an unsaturated auxiliary NMOS transistor achieves the suppression of the nonlinearity. Two-stage common source network is used to enhance the gain and achieves X-band bandwidth in the proposed LNA. With low extra 0.07 mW power consumption of the post-distortion network, the simulated results of the implemented LNA show that IIP3 has been boosted to −5~3.55 dBm in the range of 8–12 GHz. The LNA has a peak gain of 14.3 dB and a minimum noise figure of 1.86 dB. It consumes a total 5.79 mW power consumption from a 600 mV supply voltage. The total chip area is 0.69 mm2.

Due to the difference between MMC-HVDC and LCC-HVDC control characteristics and the mutual influence of parallel connection, its power modulation strategy is different from that of LCC-HVDC. Coordinated control strategy of parallel system of MMC-HVDC and LCC-HVDC is analyzed. The methods of power distribution, rate distribution and reactive power control of power limit function are described. Combined with RTDS simulation research of modulation function of Luxi back-to-back HVDC system, the control characteristics of power limitation function of the parallel system under the condition of AC fault at the rectifier side are analyzed in view of the exposed defects. The coordination method of the power limit function, the high voltage crossing control function and the rate distribution optimization is proposed. The simulation results show that the optimized parallel system can perform the power limiting function according to the correct timing and rate.