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This preliminary case-study report summarizes 5-years of research on the contrasting soiling conditions in the tropical, subtropical, and semi-arid climates in Brazil. This paper presents a methodology to quantify the soiling ratio (SRatio) and soiling rate (SRate) in PV modules of thin-film cadmium telluride (CdTe) and polycrystalline silicon (p-Si) through measurements from monitoring soiling stations installed in different climatic zones in Brazil. In these studies, the meteorological data and the electrical and thermal parameters of the photovoltaic modules have been collected and analyzed, and a mathematical model was developed to determine the soiling ratio (SRatio) and soiling rate (SRate) for each site (in compliance with the IEC 61724–1 monitoring standard and IEC 62670–3). The SRatio for short-circuit current (SRatioI sc ) and maximum power (SRatio Pmax ) data from the PV modules were evaluated and compared with objective of characterizing the uniformity of the soiling deposition process and to monitor any associated issues with non-uniform thermal effects. Non-uniform soiling is dicussed associated with framed modules and with effects of precipitation. Finally, other parameters are discussed for these climate conditions.

Based on the investigation data of Jiaozhou Bay in May, August and October, 1992, the variation of PHC content in the surface and bottom layers and the deposition process were studied. According to the definition and model of Content Change Angle of Dongfang Yang, the calculation results show that in the surface water, the Content Change Angle of Dongfang Yang is - 0.34° from May to August, and 0.28° from August to October. In the bottom water, from May to August, the Content Change Angle of Dongfang Yang is - 0.91°, and from August to October, the Content Change Angle of Dongfang Yang is 0.22°.According to the scale of time and space, in May, the oil spills transported PHC content to Jiaozhou Bay, but in August, there was no PHC content from any sources. From May to August, PHC content decreased slowly and to a relatively low level. In October, open seas currents transported PHC content to Jiaozhou Bay. From August to October, PHC content increased slowly and to a higher level. After PHC content passed through the water body, from May to August, the settling PHC content in bottom increased slowly and the increase was relatively small. From August to October, the settling PHC content in bottom increased a little slowly. Therefore, the author puts forward the change process of the material content transported from sources in water bodies: when materials are transported to a water body from sources, the material content in the surface of the water body will rise faster than that in the bottom, and the material content in both the surface and the bottom will start to rise slowly. When materials are not transported to a water body from sources, the material content in the bottom of the water body will decline faster than that in the surface of the water body, and the material content in both the surface water body and the bottom water body will begin to decline slowly.

The presence of chlorine ions can accelerate the degradation of Au-Al wire bonds. The chlorine-containing particles and the city water used for cleaning inside the packaging line are the possible sources of chlorine ions. It is speculated that the water carrying chlorine ions intruded into the encapsulated devices and resulted in bonding pad corrosion during the reliability test (uHAST: 110°C/85%RH). The design variation of pads, including the layout and the deposition process, may be responsible for such high failure rate of reliability.

Organometallic perovskites are under intense study for use in photovoltaic cells. We present investigation results of the electrical properties of the perovskites thin films. The films were grown by physical vapor deposition (PVD) technique on transparent (glass) and semiconductor (n-type silicon) substrates kept at room temperature during the deposition process. After the deposition process samples was stored in vacuum. Electrical properties such as the temperature dependent conductivity were tested using 4 point probe method the KEITHLEY 4200-scs system.

We investigated the effects of post-annealing process temperature on the device characteristics and stabilities of the oxide thin-film transistors (TFTs) using the In-Ga-Zn-O (IGZO) active layers prepared by atomic-layer deposition process. The fabricated IGZO TFTs exhibited a high saturation mobility of 12.0 cm2/Vs and a subthreshold swing of 0.20 V/dec after the annealing at 150 °C. The density of tail and deep states for the ALD-IGZO TFTs annealed at 150 °C was estimated to be 7.3×1017 in the mid-gap region. The threshold voltage shifts for the TFTs annealed at 150 °C were estimated to be −3.5 and −2.3 V under the positive and negative bias temperature stress tests at 60 °C for 104 s, respectively.

We presented the development and characterization of high-k stack HfO 2 /Al 2 O 3 capacitor, fabricated directly on chip. The capacitor is based on nanolaminate material directly grown by plasma-assisted Atomic Layer Deposition (ALD)in a single reactor chamber. The deposition process was performed at a single temperature (250°C). We tested the various numbers of layers in the stack, compared the electrical and material characterizations. Using the optimal deposition conditions, we obtained a structure with nanolaminates of single thickens 5 A, capacitance density of 1.10−12 F.μm−2 and leakage current density of $1.10^{-9}$ A.cm−2.

Metal hard mask TiN was induced as patterning film due to less ULK damage, but TiN tiny particle can make metal line open which is unacceptable. In this paper, the ramp mode of DC power during TiN deposition process was analyzed for tiny particle reduction. TiN as-dep defect scan results showed that DC power with slower ramp rate at ignition and pump down step can reduce tiny particle obviously. According to hard mask AEI defect scan results, metal open defect related with TiN film cannot be found.

The wafer non-uniformity of WAT and yield within wafer (WIW) and wafer to wafer (WTW) is a major and everlasting problem, which is mainly caused by rapid thermal process and Spacer-2 Nitride deposition process. In this paper, we develop a simple method to remove nitride film on wafer backside with H 3 PO 4 treatment while protecting wafer front pattern completely by utilizing two different films. The excellent uniformity WIW and WTW can be acquired by utilizing this method, which is extremely promising for wafer thermal uniformity improvement and wafer edge yield enhancement.

Here we report on the production of highly gas permeable Parylene HT through a cryogenic deposition process. The unique combination of biological and chemical inertness of Parylene, and gas permeability of this porous variant make it interesting for cell culture and biology-on-a-chip applications. The dependence of porosity, density, and permeability on the deposition temperature allows for tunable control of material properties. Culture of HEK-293 cells on cryogenically deposited Parylene HT demonstrates viability for biological applications.

Novel damage control integration process technology has been developed through development of new low-damage MgO deposition process, low-damage RIE process, and low temperature SiN-cap process. Application of the developed damage control integration process technology to MTJ fabrication enabled us to demonstrate an improvement of TMR ratio, thermal stability factor, and switching efficiency. Moreover, it is shown that the endurance of the fabricated MTJs is over 1010, although thermal stability factor drastically increased. Finally, with the developed 37-nm p-MTJ technology and the damage control integration process technology, 128Mb density embedded STT-MRAM was fabricated. By using our 128Mb density STT-MRAM, 14ns write speed at $V_{\text{dd}}$ of 1.2V was successfully demonstrated. This result will contribute to low power MCU/IoT chip solution and so on.

The effects of silicide-blocked (SAB) oxide and contact etch stop layer (CESL) on the retention characteristic of one-time programming (OTP) nonvolatile memory (NVM) are experimentally evaluated through various deposition process conditions. The OTP retention is characterized after a baking condition of 250°C for 4 hrs. Our results suggest the NH3 and SiH 4 gas base deposition process effectively make improvements on OTP data retention. And the thicker the SAB film, the better the data retention.

The paper deals with the analysis and viscosity measurements of five commonly available silver based nano-inks at different temperatures. The kind of solvent, dimension of nano-particles and temperature play a key role for the viscosity of nano-inks. For the controlling of the deposition process of nano-inks by inkjet printing technology, knowledge of the rheological properties of applied nano-inks are necessary. It is really difficult to preserve the stable temperature in the printing nozzle during the deposition process, for this reason the voltage signal which is controlling the piezo-elements in the nozzle has to be modified due to the viscosity changes. For this reason, this paper offers the practical results from the viscosity measurements, which were done by rheometer MCR 502 Anton Paar. Furthermore, the paper offers the comparative study of the viscosity measurements of different kind of silver based nano-inks. The twin gap method was applied due to achieving of high accuracy of measurements. As the preliminary results show, the viscosity of silver based nano-inks has the strong dependence on the temperature.

A novel inkjet-like thick-film deposition process has been developed which also enables printing thick films onto conformal surfaces. This paper presents wideband bowtie antennas printed using silver ink onto Perspex cylinders.

This work presents a template matching-based approach tackling image drift during Electron Beam induced Deposition of nano-granular metal structures. An automation sequence including a drift compensation routine is implemented using a self-developed software framework. A template matching algorithm simultaneously processing multiple templates adapts to the continuously changing image periodically acquired by the scanning electron microscope during the deposition process and thus avoids blurred depositions due to template matching errors.

A chronic NPN Bipolar ICEO leakage failure mode on a BiCMOS (B+) process was revealed to be caused by marginality in the CMOS oxide spacer film deposition process. It has been shown that residual carbon in the PETEOS spacer oxide film generated defects at the collector/base interface. These defects prevented epitaxial growth of the base region. The defects and ICEO leakage were eliminated by modifying the process conditions during the termination of the PETEOS oxide deposition.

Unique defect related to the tighter process margins on STI HDP process was investigated. The root cause was Si surface damage due to smaller top width of HDP. The defect was improved by HDP deposition process optimization derived relationship between ion incident angle and sputtering rate during deposition process. It was elucidated that HDP process is important for not only gap filling capability but also HDP physical profile control to obtain robustness process establishment.

A new coating system for the deposition of sensors and thin-layers directly onto components of arbitrary size has been invented at the Institute of Micro Production Technology. This system allows for thinner sensors without any carrier substrate and with a higher measuring accuracy. Within this paper, the basic setup and the functional principle of the new coating system is presented. The deposition process sequence is described and the system is characterized concerning layer homogeneity and evacuation time.

Although a high speed PLD (Pulsed Laser Deposition) method is attractive in order to obtain thick film rare-earth permanent magnets such as Nd-Fe-B and Pr-Fe-B films applied to miniaturized devices [1] [2], the fundamental mechanism of the deposition process is still unclear. In this study, we focused on the preparation of Fe-Co films by using the PLD because a Fe-Co film has a simple binary-alloy-based composition. This contribution reports the relationship between the laser energy density (LED) of the PLD method and various values such as surface morphology, compositions and magnetic properties in PLD-fabricated Fe-Co films.

A CIGS deposition process based on sputtering and utilizing a stainless steel substrate is at particular risk for incorporating Cr and Fe contamination into the absorber film. This is a 5 year study of impurity and device performance data from the development of such a process. We have found a significant Voc benefit from reducing Cr in the CIGS while Fe had no effect on Voc. Use of higher purity sputter target material was a significant factor in reducing the contamination level of the CIGS films.

Power short (PS) bin failure due to Al bridging in bond pad regions originated from Al whisker, caused severe yield loss in advanced technology nodes. A comprehensive study on circuit design impact on Al whisker bridging issue was carried out and it was found that increasing Al metal spacing reduced Al whisker bridging. Furthermore, through optimization of process, the novel Al high power deposition recipe demonstrated that power short failure caused by Al whisker could be completely eliminated. The two proposed solutions provide a guideline to solve Al whisker for more advanced technology nodes.

Copper electrodeposition for on-chip interconnection has been widely described in the semiconductor industry. Most copper plating chemistries currently used for copper interconnects are acidic, involving special additives that provide bottom up fill of the narrow structures[1]. However, as copper interconnects continue to be scaled down in order to improve device performance within a minimum area, conventional acidic bath chemistries have shown limitations, due to the non-uniform coverage of the copper seed layer obtained with physical vapor deposition (PVD). In fact, acidic copper plating baths require a perfectly continuous copper seed layer in order to achieve void-free filling, which is mainly due to poor nucleation density of the acidic bath on resistive under layers (e.g., the barrier layer). Several years ago, a cobalt liner was widely studied as an additional layer to promote copper seed layer coverage on the barrier layer by improving copper wetting[2,3]. It resulted in a thin, continuous and conformal copper layer that facilitates the repair of discontinuities and the formation of a robust seed layer favorable to void-free copper filling. Also, geometry shrinking created high line resistance and the trend toward copper line failure. Interface quality between the copper and dielectric barrier then appeared to be vital, justifying again the introduction of a cobalt layer to ensure chip reliability, especially electromigration. Nevertheless, next generation interconnects will tend to adopt new integration schemes with increased copper volume inside the features in order to decrease RC delay. Additionally, aggressive critical dimensions (CD) will require a greater suppressing effect of the copper plating chemistries to avoid premature closure of the trenches / vias. In order to achieve void-free filling of advanced node copper interconnects, novel and innovative plating chemistries have to be developed. The conventional acidic three-component bath (accelerator, suppressor, and leveler) used for decades must be reinvented in order to improve the suppressing effect and bottom up efficiency, and to prevent any pinch-off during the gap fill of very aggressive and narrow trenches ( [1] P.C. Andricacos, C.Uzoh, J.O. Dukovic, J. Horkans, and H. Deligianni, IBM, J. of Res. And Dev., vol. 42, 1998, 567. [2] T. Nogami, et al., ‘CVD Co and its application to Cu damascene interconnections’, Interconnect Technology Conference (IITC), 2010, 1. [3] T. Nogami et al., ‘CVD-Co/Cu(Mn) integration and reliability for 10 nm node’, Interconnect Technology Conference (IITC), 2013,1

We obtained high-quality PECVD-SiN films deposited under 120°C using organosilane precursor. The SiN film has low hydrogen content and low BHF etching rate. In addition, SiN film properties did not change after pressure cooker test (PCT: 120°C, 0.2 MPa, 6 hours). The low-temperature deposition process for SiN films hold promise for improving 3DIC manufacturing process.

For Cu interconnects technology, the effects of barrier thickness and process optimizations are very important to electro-migration (EM) reliability. The microstructure of Cu electrochemical plating is highly with respect to characteristic of underlying barrier and Cu seed layers. Non-enough barrier thickness, we found early failure in single via test structure degrading EM lifetime. Furthermore, significant occur void formation site induce poor EM lifetime from non-optimized barrier deposition process. We conducted failures analyses and studied failure root causes. From investigation results, both failure analyses and generation mechanism are reported.

This paper reports the first step towards simultaneously operating the n = 2 and n = 3 pairs of modes in a disk resonator for two independent measurements of angular rate. A model based approach is adopted to estimate the resonator imbalance parameters and an iterative mass perturbation technique is developed to simultaneously reduce the frequency mismatch of the n = 2 mode pair as well as the n = 3 mode pair. At the termination of mass deposition process, each pair of modes exhibits a residual frequency mismatch of approximately 100 mHz.

An upgrade kit for the 200 mm Applied Materials Epi Centura was released. The retrofit includes an alignment tool for the setup of the process kit, a motorized lift as well as a new susceptor design. The hardware parts were installed in an APCVD (Atmospheric Pressure Chemical Vapor Deposition) production tool and tested in a production environment. The upgrade kit enables a reduction of the total range (max-min value) of the epi film thickness profile and a stable repeatability of the deposition process. A qualitative assessment of the new hardware during the production of an electrical device was carried out by analyzing sigma values of a PCM (Process Control Monitoring) parameter which is highly sensitive to variations in the epi thickness. The sigma of the PCM parameter from several lots, processed prior to the retrofit of the chamber and processed in the same chamber in the retrofitted state were compared and a reduction of the sigma value was observed when using the upgrade kit for the epi deposition.

A specific issue based on fluorine interaction on SiCN and SiOC layers is presented in this paper. Beyond this issue, the main subject of this paper is to show how this issue can be detected. A fault detection program monitors the deposition process and allows to control different parameters in real time to prevent such an issue as the fluorine interaction on SiCN and SiOC layers.

In this paper the bandgap variation have been studied as a function to the deposition temperature, annealing temperature and water ratio. High temperature during deposition or annealing has yielded in a low bandgap, while increasing water concentration has increase it. I-V characteristics for different thicknesses demonstrates a better Isc for a thicker sample. Conversion efficiency at a higher temperatures gave a better response towards the midrange of the UV spectrum. High temperature response in these cells can be considered as an advantage over that of conventional solar cells. We concluded that deposition parameters play a very important role in the optical and electrical characteristics of TiO2 nano materials, theses results reflected positively in producing TiO2 solar cells.

Two methods currently used to induce surface roughness that promotes the growth of AlN tilted grains to fabricate shear mode resonators have been investigated. The first one involves the use of a rough substrate to provide tilted facets on which the AlN grains will grow with a certain angle. The second method is based on using a thin non-piezoelectric AlN seed layer that exhibits high populations of {10·3} and {10·2} planes. The influence of the power applied to the Al target and the total gas pressure during the deposition process of the AlN seed layer has been studied and correlated with the k2shear of the resonators. The best fabricated devices show a shear mode resonance frequency at around 1.45 GHz, a k2shear up to 3.64% and a Qshear above 230 when operating in air, which reduces to 108 when operating in liquid.

The focus of this paper is to investigate two different techniques to improve the optical properties of pH-sensitive nanolayers coating deposited using Layer-by-Layer (LbL) method. The two approaches studied in this work are: addition of salt into the polyion solutions and/or the use of different drying methods. As a case study, pH sensitive nanolayer coatings using Neutral Red as pH sensitive molecule and poly (acrylic acid) [PAA] as cross-linker are deposited on either a bare silica optical fiber or a glass slide using different salt concentrations and drying techniques. The optical properties of each coated sensor are measured and compared. It is shown that both methods can optimize the deposition process and improve the sensor sensitivity.

In this study, we demonstrate the ZnO nanorods (NRs) and nanocombs (NCs) by simple galvanostatic electrochemical deposition process. The ZnO nanostructures act as high ultra-violet (UV) sensing material due to high aspect ratio. The photoluminescence (PL) spectra and time-dependent photo response of the ZnO nanostructures grown on Au/Si has exhibited good optical properties. At room temperature, NCs showed good response with change 8% its resistance, few second's response time and fully recovery. Inversely, in high temperature ZnO NRs indicated better response than NCs with change of 20% of its resistance. The dependence photoresponse on temperature demonstrated clearly how surface-defects affect on UV response of ZnO nanostructures.

The a-Si:H deposition process is systematically investigated in intrawafer and wafer-to-wafer experiments. Photonic ring resonators were studied within-chip and chip-to-chip, showing ±1.2nm resonance peak variations and deviations of 0.25% (intrachip) and 0.9%(interchip) for group index and FSR.

High aspect ratio through-Si vias (2 µmφ, AR 15) have been filled without voids on coupon scale by using an electroless deposited Cu seed layer on ALD-Ru. The total Cu overburden, which is ELD and filling Cu, was about 700 nm. In addition, the electroless Cu bath showed good stability during 2 hours with controlling pH to stabilize the deposition process. These results show the feasibility of electroless deposition in TSV processing.

This paper presents an assessment of aspects that influences asphaltene precipitation and deposition. This research, attempts to understand the mechanism of asphaltene precipitation and deposition, parameters affecting the precipitation and deposition process, the effect of asphaltene precipitation and deposition on oil reservoir characteristics and performance. In addition, the research involves examining the existing thermodynamic models of asphaltene precipitation and deposition in porous media, reversibility of asphaltene precipitation and deposition, asphaltene deposition removal methods, and modeling and simulation of asphaltene by conventional simulators. Since this study is a comprehensive summary of the mentioned topics and contains all the essential information of asphaltene and its precipitation process, it therefore can be used as a reference for further exploration of this specialized field. The probability of asphaltene precipitation and deposition occurring during any EOR techniques and its effects on reservoir performance should be anticipated at earlier stages of any development project. Also it is believed that through a more comprehensive understanding of the mechanisms that lead to deposition in the first place; asphaltenes deposition if cannot be prevented fully may at least be controlled and managed.

Although CIGS technology has not yet demonstrated large volume commercial success, ongoing investment in manufacturing facilities is being made because of its outstanding potential. It is clearly not straightforward to transfer a high performance laboratory process to a manufacturing line. Manufacturing issues such as throughput, yield and materials utilization are not typical metrics in developing lab scale processes, and new ways of meeting these demands of the manufacturing line while keeping the lab scale performance must be found. We are developing a large area roll-to-roll piloting facility whose primary objective is to meet these demands. In support of this objective we are conducting lab-scale experiments which are guided by commercialization driven parameters. The deposition process which we favor is a 2-step process using solid Se which we designate as 2SSS. Our approach is to make side-by-side comparisons of films and devices made with this process and the ideal co-evaporation process and to demonstrate equivalent properties with a more manufacturable process. In this paper we report results on effective incorporation of Ga. We demonstrate that film properties are equivalent to those produced by co-deposition, and in particular that the processing time and use of raw materials is the same. A key finding is that selective precursor films can be configured to reduce the formation of volatile Ga x Se y species responsible for the loss of Ga and excessive use of Se.

Parylene films deposited on liquid surface induce film tension that changes the liquid shape. We observed that the force acting on the surface of Parylene-C encapsulated liquid bodies increased continuously during Parylene deposition process and reached final values of magnitude more than 700µN/mm for a 1µm thick film, 20 times larger than the surface tension of the encapsulated liquid. This surface force can only be attributed to the tension of the Parylene films. This founding requires that in design of Parylene encapsulated liquid structures, Parylene film tension must be considered as the main factor that determines the structures' final shape.

We present an efficient algorithm for the detection of voids which potentially emerge during deposition process simulation. The application of modern level set techniques and data structures enables the fast determination of connected components directly from the implicit level set representation without the need of an additional surface extraction. The algo- rithm exhibits optimal linear scaling with surface size and is demonstrated on an example, where an isotropic etching process followed by conformal deposition is simulated.

The formation mechanism of micro three-dimensional spiral structure is discussed. Simulations of deposition ions trace in deposition process, which is the key of forming micro three-dimensional spiral structure, are performed. It is found that the deposition ions trace is of a helix shape. The simulation results correspond well with the deposit structure obtained in the test. It is found from the simulation results that the distribution of electromagnetic field in discharge channel has a considerable influence on the deposition structure and movement of deposited particles.

The printed circuit board (PCB) technology is developing in the aspect of small size, lightweight, high density and high stability, so it makes strict requirement to the electrochemical deposition technology in the PCB manufacturing. This paper shows the mechanism of electrochemical deposition in the PCB manufacturing in detail, including the electroless plating technology and the electroplating technology, briefly introduces the process of PCB manufacturing with the combination of this two kinds of technology, introduces the development and research progress of electroless plating technology and electroplating technology in detail, proposes some problems in electrochemical deposition process, finally introduces some improvements of electrochemical deposition in the aspect of the stability of plating solution, the composition of plating solution and some practical advanced technique.

In control practice for the electroless nickel plating through holes board, the pH-index is controlled in dependence on the metal turnover, while the nickel percentage is kept at constant level. In this paper, the state of the process is estimated by several electrochemical parameters by which the required pH-index and nickel percentage is evaluated in dependence on the current state. The desired parameters of the product - thickness of the plating film and phosphorous content - are ensured by supervisor control of the pH-index and nickel percentage at target set-points tracked from the chemical equilibrium of the system. The bath loading, which has a strong effect on the deposition process, is estimated and its variation compensated by control.

Maintaining product measurements and tool parameters within tolerance limits is insufficient, if a semiconductor manufacturer desires to remain competitive. National Semiconductor Corporation, South Portland, Maine (NSME) manufactures a variety of semiconductor products with a diverse mixture of process flows. For chemical vapor deposited (CVD) films, it is a challenge to maintain each unique deposition process on-target for film thickness, while not wasting valuable resources and process time running qual wafers to validate adjustments to those processes. NSME uses proprietary software to respond to minute deviations (in some cases, less than 1%) from target film thickness by automatically making small adjustments to process recipe deposition times for individual process chambers. While constantly minimizing thickness deviation from target, these adjustments are performed in a way that minimizes tool impact.

As an alternative to plasma sensors, high performance VI probe was evaluated in a plasma enhanced Ti deposition process. Its utilization was focused on finding any reasonable differences between good and bad chambers classified in terms of end of line yield data. Some differences of delivered power and time trace current signal between chambers were found, which well matches the good and bad chamber classification. Also, a fault detection and classification algorithm to handle huge amount of raw VI-probe data was evaluated. The algorithm estimates deviation of TiCl4 content in plasma occurs right after preventive maintenance, which might be considered as a chamber conditioning procedure. Despite requiring additional evaluations, the combination of VI-probe and well-developed algorithm might be a feasible solution where conventional plasma sensors can not be applied.

We investigated the deposition process reproducibility of extremely-thin (

Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during the physical deposition process. Only the multi-layer model is able to simultaneously match the experimental data on drive current vs. etch-stop layer stress, poly pitch, source/drain recess, and spacer stress.

The authors have followed a unique path to a next-generation field emitting display (pFED) using an emitter formed from micron-sized graphite particles coated with a nanoscale silica insulator. The emitter is fully oxidised as part of the deposition process and so is immune to the sealing problems that plague CNTs. pFED improve with sealing.

The magnetron sputtering deposition process to metallize the high aspect ratio (deep/diameter) blind microvias was used. In this technique it is innovative that magnetron sputtering deposition process can be used with self-sustaining mode. This mode allows to deposit of very clear (without any labour gas particles) electro-conductive layers (Radzimski et al., 1998). Typically, the thickness of deposited layers is about few micrometers and with success it can be used as electro-conductive connections. However, the thickness of connections can be grown in electroplating processes to decrease its resistance. In the paper the results of first trials of electro-conductive base-layers growing are presented. The big advantage of magnetron sputtering deposition technique is possibility of increasing the aspect ratio of micro-connections in PCBs (printed circuit boards) even several times. This technique was used successfully for metallization of high aspect ratio blind microvias. It was proved that investigated process can be useful in HDI (high density interconnections) PCBs manufacturing.

In the present article, the production process of the photocathodes for the TESLA Test Facility (TTF) at DESY Hamburg and the Photo Injector Test Facility at DESY Zeuthen (PITZ) is reviewed in order to highlight key elements for the final photocathode performances. Since the first photocathode production in 1998, we have continuously collected relevant parameters of the cathode plugs and deposition process. These data are now critically analyzed in view of an optimization of the photocathode performances for the next generation of high brilliance sources.

In this paper, we present studies of plasma-enhanced chemical vapor deposited silicon nitride in which photoluminescence imaging was used to characterize our deposition process. A showcase of different processing issues such as equipment design, processing conditions, and manual handling is presented. We also demonstrate how photoluminescence imaging can be particularly useful for process monitoring, diagnoses, and development. An increase in implied Voc of up to 25 mV was achieved through the use of PL imaging as a diagnostic tool.