Search

Advances over the last decades in electronic design automation (EDA) for the design of digital integrated circuits (ICs), have led to the development of a robust set of tools and methodologies that automate almost all low-level phases of the digital design workflow. In contrast, analog IC design remains a mostly handmade, time-consuming and knowledge-intensive process. The amount of design iterations can be heavily cut down by the use of realistic value tables through the $g_{m}/I_{D}$ design technique; however, the process still remains time-consuming and error-prone, with an end result of limited applicability beyond the scope of the initial specifications. The slice-based design methodology, first introduced in this paper, is a new approach to analog IC design, suitable for implementation in EDA tools, that aims to reduce the amount of time and expertise required from the user. This methodology, inspired by the $g_{m}/I_{D}$ design technique, is based on the use of pre-designed circuit cells, which can be connected in parallel to scale important performance metrics. Although not limited to any particular fabrication process, the present paper explores the application of the proposed design methodology to CMOS technologies, and in the context of a particular target application: low-noise charge-sensitive amplifiers (CSA) used for instrumentation in particle physics experiments. The methodology was successfully applied and validated through the design, fabrication and testing of a CSA with configurable noise performance.

High-performance single-transistor current source is crucial to analog design in advanced CMOS processes. Various approaches to enhance the output resistance of single-transistor current source are studied in this brief in the view of adaptive control. Then a novel compact implementation is proposed, and used to build a fully differential OTA with improved dc gain and common-mode rejection in a 55 nm CMOS with a supply of 1.1 V. [ABSTRACT FROM AUTHOR]

This brief presents a linearization method for the voltage-to-current (V-to-I) stage of voltage-controlled oscillators (VCOs). A floating-gate transistor is utilized at the VCO’s input stage as a low-overhead method for V-to-I linearization. The resulting VCO is a ring oscillator with an extended linear voltage-to-frequency range. The ring oscillator VCO (RO-VCO) has also been included in a VCO-based analog-to-digital converter (VCO-ADC) to showcase how the linearization technique can be leveraged to improve system performance. The measured results from the linearized RO-VCO are compared to current state-of-the-art designs, and the VCO-ADC is compared to a standard architecture. The circuits were fabricated in a standard $0.35~\mu \text{m}$ complementary metal-oxide-semiconductor (CMOS) process. [ABSTRACT FROM AUTHOR]

In this article, a new CMOS voltage follower, with class AB output, derived by merging the super follower and the flipped voltage follower, is introduced. The resulting cell exhibits lower output impedance than its predecessors. Expressions for the behavior of the proposed follower are derived and verified by circuit simulations in Eldo using the C5N CMOS process models available through The MOSIS Service. The conducted analysis shows an improved performance of the presented circuit with respect to the flipped- and super followers. To prove the principle, a test cell was fabricated in the mentioned technology and characterized. Measurement results show quasi-symmetric rising and falling edges and a gain–bandwidth product of 32 MHz with a load capacitance of 47 pF. The power consumption of the cell is $138~\mu \text{W}$ with 2-V supply. Résumé—Dans cet article, un nouveau suiveur de tension CMOS, avec une sortie de classe AB, dérivé de la fusion du super suiveur et du suiveur de tension inversé, est présenté. La cellule résultante présente une impédance de sortie inférieure à celle de ses prédécesseurs. Les expressions pour le comportement du suiveur proposé sont dérivées et vérifiées par des simulations de circuits dans Eldo en utilisant les modèles de processus CMOS C5N disponibles via le service MOSIS. L’analyse effectuée montre une amélioration des performances du circuit présenté par rapport aux suiveurs super et inversé. Pour prouver le principe, une cellule d’essai a été fabriquée dans la technologie mentionnée et caractérisée. Les résultats de mesure montrent des fronts montants et descendants quasi-symétriques et un produit gain-largeur de bande de 32 MHz avec une capacité de charge de 47 pF. La consommation en puissance electrique de la cellule est de 138 $\mu$ W avec une alimentation 2 V. [ABSTRACT FROM AUTHOR]

The envelope tracking (ET) design methodology is routinely adopted to improve the efficiency of radio frequency power amplifiers (PAs). One shortcoming of state-of-the-art ET PAs is that their supply modulators are usually designed and optimized for a single communications standard. They are either incompatible in modern communication devices where multiple communications standards are used, and/or the efficiency unoptimized when the devices operate in standards other than the designed standard. To circumvent this shortcoming, a novel supply modulator for multistandard communications is proposed. The proposed design embodies a proposed dual-mode Sigma–Delta control block and an adaptive biasing Class AB amplifier, which allows the supply modulator self-adjusting its operation and optimizing the efficiency according to the application. A prototype supply modulator IC is designed and fabricated using a 180 nm CMOS process. Based on measurements, the proposed supply modulator features the highest static efficiency of 91% and the highest 3 dB backoff static and dynamic efficiency compared to the state-of-the-art supply modulators. When tracking 40 MHz LTE-A envelope signals, the prototype supply modulator achieves a high efficiency of 85% at 1.8 W output power, and the efficiency remains high >80% for a wide range of output power, from 0.5 to 1.8 W. [ABSTRACT FROM AUTHOR]

High-throughput recordings of small current are becoming more common in biosensor applications, including in vivo dopamine measurements, single-cell electrophysiology, photoplethysmography, pulse oximetry, and nanopore recordings. Thus, a highly scalable transimpedance amplifier design is in demand. Half-shared amplifier design is one way to improve the scalability by sharing the non-inverting side of the operational amplifier design for many inverting halves. This method reduces silicon area and power by nearly half compared to using independent operational amplifiers. In this paper, we analyze the scalability of a simple half-shared amplifier structure while investigating the tradeoff of increasing the number of inverting half amplifiers sharing a single non-inverting half. A transimpedance amplifier is designed using the half-shared structure to minimize the size per amplifier. The transimpedance amplifier is based on a current integration of a capacitor. The noise analysis of the integration amplifier is a challenging task because it does not reach a steady-state, thus, being a non-stationary circuit. For frequency analysis, a conversion method is discussed to estimate the noise characteristic in the simulation. The array design of 1024 transimpedance amplifiers is fabricated using a standard 0.35 μm process and is tested to confirm the validity of above analysis. The amplifier array exhibits high linearity in transimpedance gain (7.00 mV/pA for high gain and 0.86 mV/pA for low gain), low mismatch of 1.65 mV across the entire 1024 amplifier array, and extremely low noise. The technique will be crucial in enabling the fabrication of larger arrays to enable higher throughput measurement tools for biosensor applications. [ABSTRACT FROM AUTHOR]

We describe a supply modulator comprising a proposed delay-based hysteresis controller, proposed wideband class-AB amplifier, and class-D amplifier for an envelope tracking (ET) power amplifier (PA). We investigate the power dissipation and optimization method of the supply modulator for wideband applications taking into consideration the propagation delay, and show that a controller with zero threshold current not only improves the bandwidth of the supply modulator but also reduces its power dissipation. Based on our investigations, we propose a delay-based hysteresis controller embodying a novel high-speed current comparator whose reference current (threshold current) is zero, thereby achieving higher power-efficiency and simpler hardware. We further propose a class-AB amplifier, which features a high bandwidth and accurately controlled quiescent current. The proposed supply modulator features simultaneously the wide bandwidth (40 MHz), high output power (2.5 W), high peak efficiency (91%), high output voltage swing (3 V), and low output ripple noise (4 mVrms) at 3.6-V supply. The ET PA embodying our proposed supply modulator achieves a high power-efficiency of 41.4% at 28.5-dBm peak output power and 34.4% at 3-dB backoff—a significant >1.6× improvement over the radio frequency PA without the supply modulator. [ABSTRACT FROM AUTHOR]

A voltage-controlled current amplifier/attenuator in a standard 0.35- ${\mu }\text{m}$ CMOS technology is presented. It is based on the resistive mirror method, using non-saturated MOSFETs. An open-loop design with no compensation capacitors provides a high stability and a small occupied chip area of 0.0126 mm2. A current gain dynamic range of 513 (54.2 dB), a gain-bandwidth product of 1.78 GHz at the largest current gain of 35.9 dB, and a maximum power consumption of 250 ${\mu }\text{W}$ with a single supply voltage of 1.3 V are achieved. In addition, an AC current source has been designed, integrated on the same chip, and used as the input of the proposed voltage-controlled amplifier/attenuator. [ABSTRACT FROM AUTHOR]

This paper is devoted to local parametric fault diagnosis of nonlinear analog integrated circuits designed in a bipolar and CMOS technology. An algorithm is proposed that allows estimating values of the considered set of the parameters. The algorithm exploits a diagnostic test performed in a dc state, leading to output voltages measured in the circuit. Each of the output voltages is a parameterized function. A system of overdetermined equations fitting the parameterized functions to the data points is created. An efficient iterative method is developed for solving this overdetermined system of nonlinear equations exploiting the idea of the normal equation and a homotopy concept. It is implemented in the manner that allows operating with the functions not given in the explicit analytical form, which commonly occurs in real nonlinear circuits. For illustration, two examples are given, including a circuit with bipolar transistors and a CMOS circuit designed in a nanometer technology. They reveal the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the medium resistive input benefit of CTIP ADCs. The resetting integrator allows the architecture to be implemented with a feedforward compensated op-amp using low-voltage CMOS processes. This paper has been verified by simulation results of a CTIP ADC with 1.2-V supply voltage designed in TSMC's 65-nm CMOS technology. [ABSTRACT FROM AUTHOR]

Design and implementation of CMOS channel select filters for digital video broadcasting-handheld integrated direct-conversion receivers are presented. The filters are designed to fulfill selectivity requirements with optimized power consumption. The proposed filters are based on the current amplifier and the transresistance amplifier offering alternatives for current-mode and voltage-mode signal processing, respectively. Adopting one active element per biquad allows optimization of the power consumption, and hence, leads to significant improvement over the available solutions. The two filters were fabricated in a standard 0.18- \mu \textm CMOS technology and experimental results are provided. [ABSTRACT FROM PUBLISHER]

An architectural performance comparison of bandgap voltage reference variants, designed in a 0.18~\mu \text m CMOS process, is performed with respect to single event transients. These are commonly induced in microelectronics in the space radiation environment. Heavy ion tests (Silicon, Krypton, Xenon) are used to explore the analog single-event transients and have revealed pulse quenching mechanisms in analogue circuits. The different topologies are compared, in terms of cross-section, pulse duration and pulse amplitude. The measured results, and the explanations behind the findings, reveal important guidelines for designing analog integrated circuits, which are intended for space applications. The paper includes an analysis on how pulse quenching occurs within the indispensable current mirror, which is used in every analog circuit. [ABSTRACT FROM AUTHOR]

This brief presents a 120-MS/s continuous-time delta-sigma analog-to-digital conversion with a dual-slope-based time-interleaved quantizer in a 0.18- \mu\mboxm complementary metal–oxide–semiconductor process. Excess loop delay of two sample clocks is compensated using the time information made available through interleaved channel coupling. As a result, one full clock cycle is afforded to digital-to-analog conversion dynamic element matching (DEM) operation, allowing for a digitally synthesized DEM block. [ABSTRACT FROM PUBLISHER]

A 12-bit pipelined analog-to-digital converter (ADC) uses a first-stage integrator-based open-loop residue amplifier and integrator nonlinearities are foreground calibrated. In the remaining traditional closed-loop stages, gain errors and memory errors are background calibrated. Separate reference voltages are used in the first three ADC stages to reduce interstage coupling. A 0.25- \mu\mboxm CMOS prototype dissipates 140 mW and occupies an active area of 5 mm 2. At 40 megasamples/s (40 MS/s) , the calibration improves the spurious-free dynamic range from 51.2 to 95.1 dB and the signal-to-noise-plus-distortion ratio from 43.7 to 69.0 dB. [ABSTRACT FROM PUBLISHER]

Various class AB two-stage op-amps with high and approximately symmetrical slew rate and very simple architecture are introduced in this brief. A current replicating branch with scaled-down transistors in combination with adaptive loads is used to implement a push–pull output stage with maximum output current several times higher than the bias current. Postlayout simulation and measurement results are presented and verify a 400%–500% slew rate and 80%–100% GB enhancement with only 5% additional quiescent power dissipation and 20% silicon area increase. [ABSTRACT FROM AUTHOR]

A 6-bit, 1-GS/s subranging analog-to-digital converter (ADC) implemented in 65-nm CMOS is developed. The same capacitor DACs (CDACs) are used to sample the analog signals, thereby eliminating the errors between the coarse and fine decisions that occur when two different samplers are used to capture the signal. Both decisions use the same comparators, and a digitally assisted calibration circuit compensates for the errors in the different threshold levels used for the two decisions. This calibration eliminates redundant comparators, and thus, reduces the area. Reference voltages generators, which are implemented using resistor ladders in conventional subranging ADCs, are eliminated thanks to the use of the CDACs together with interpolation in the comparators. This solves two problems related to the resistor ladder, namely, the trade-off between the settling time and the static-current consumption and signal dependent on-resistance of switches connected to intermediate potential nodes. A test chip fabricated in 65-nm CMOS technology operates at 1 GS/s with SNDR of 32.8 dB. Its active area is 0.044 mm^2, and its power consumption is 9.9 mW at a 1.1-V supply voltage. [ABSTRACT FROM AUTHOR]

Process variation is an obstacle in designing reliable CMOS mixed signal systems with high yield. To minimize the variation in voltage gain due to variations in process, supply voltage, and temperature for common transconductance-based amplifiers, we present a new compensation method based on statistical feedback of process information. We develop the background theory of the scheme and present its performance across process corners. We further apply our scheme to two well known amplifier topologies in the TSMC 65 nm CMOS process as design examples—an inductive degenerated low-noise amplifier (LNA) and a common source amplifier (CSA). Measured results over 100 chips of the LNA show that our compensation technique reduces variation in gain by a factor of 3.7\times compared to the baseline case. The CSA exhibits similar reductions in gain variation across 88 measured chips. We also present measured results demonstrating how our technique alleviates voltage gain variations caused by temperature and supply voltage changes. [ABSTRACT FROM PUBLISHER]

Mismatch can be difficult to monitor in a production test environment as it can be small and, therefore, it requires precise, time-consuming, costly measurements. This paper describes a four-transistor test structure for measurement and characterization of MOS transistor mismatch that self-amplifies the effect of mismatch, thereby generating a large and easily measurable dc output voltage. Test and design aspects of the structure are detailed, and several additional applications of the new structure are described. [ABSTRACT FROM AUTHOR]

An integrated CMOS controller with fast maximum power point regulation for module-integrated automotive solar converters with nine solar cells per string is reported. It provides the 530-kHz switching signals for the module-integrated converter whereby the mean output current of the module is maximized. The on-chip “perturb and observe” algorithm bases on a quasi-analog principle and performs more than 1000 tracking cycles/s at a power consumption around 560 μW. In order to maximize the precision, the duration of the measurement intervals is automatically adjusted to the output current. Due to the use of a very small shunt resistance of 1 mΩ for the current measurement, the insertion loss is small and the circuit complexity is kept low. Between 0.25- and 5-A photocurrent, the tracker achieves a tracking efficiency better than 99.5%. [ABSTRACT FROM AUTHOR]

A built-in technique to measure internal DC voltage levels used for the calibration of radio frequency (RF) mixers is presented in this paper. According to a common alternate test approach, RF mixer calibration is based on the prediction of the circuit's performance characteristics that requires the acquisition of a set of DC voltage observables obtained from specific nodes of the mixer operating in homodyne mode. These observables, however, often correspond to internal nodes where direct access is not always possible. Furthermore, accurate calibration might require a relatively large set of voltage observables whose direct access would lead to a waste of resources and to increased cost. The proposed built-in technique provides digital readings for the DC levels at all nodes of interest through a single interface by exploiting the use of a voltage acquisition circuit implemented by a simple analog to digital converter, which consists of a ring-type voltage controlled oscillator and a counter. A reading correction method to minimize the uncertainty introduced by process variations and device mismatches in the acquisition circuit itself is also described. The efficiency of the proposed technique has been validated by its application to the calibration procedure of a typical differential RF mixer designed in a 0.18-\mum CMOS technology. Simulation results have been obtained and assessed, both for the proposed built-in voltage measurement technique and for the direct voltage measurement approach, in favor of comparison. [ABSTRACT FROM PUBLISHER]

This paper introduces extended correlated double sampling (ECDS) as a new gain-calibration technique in pipelined analog-to-digital converters (ADCs). The proposed calibration simultaneously improves the effective dc gain and increases the maximum output swing of the opamps with given overdrive voltages. Furthermore, ECDS is immediate, thus avoiding the long convergence time associated with many background calibration schemes. This characteristic makes it desirable for applications where the ADC is on only briefly, such as wireless sensor networks (WSNs). An 11-bit 40-MS/s prototype pipelined ADC has been fabricated in 0.25-\mu \m CMOS to demonstrate the proposed calibration technique. The active die area is 3.8 \mm^2, and the analog power dissipation is 85 mW from a 2.5-V supply. With a 72-kHz input frequency, ECDS improves signal-to-noise-and-distortion ratio from 40.1 to 63.4 dB and spurious-free dynamic range from 41.8 to 75.7 dB. [ABSTRACT FROM PUBLISHER]

A digitizer designed to read out column-parallel charge-coupled devices used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined analog-to-digital converter and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The analog-to-digital converter multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the imager. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The analog-to-digital converter exhibits 188 \muV-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65-nm CMOS process. The digitizer will be applied to the development of a proof-of-principle 2D, 10 Gigapixel/s X-ray detector. [ABSTRACT FROM PUBLISHER]

We report three 850 nm, vertical-cavity surface-emitting laser (VCSEL)-based optical links using 90 nm complementary metal-oxide-semiconductor (CMOS) circuits that achieve new records in speed and power efficiency. Two receiver (RX) circuit designs explore the tradeoffs between speed, power, and silicon area. The two RXs are first tested with a simple transmitter (TX), delivering full-link power efficiencies of 1.37 pJ/bit at 15 Gb/s and 3.6 pJ/bit at 25 Gb/s. An improved TX using feed-forward equalization (FFE) and an advanced VCSEL is then introduced. The link using the FFE TX achieves full-link power efficiencies of 1.5, 2.0, and 3.8 pJ/bit at 22.5, 25, and 28.5 Gb/s, respectively. [ABSTRACT FROM PUBLISHER]

This brief presents an ultralow-power class-AB operational amplifier (OpAmp) designed in a low-cost 0.18- \mu\m CMOS technology. The proposed circuit uses transistors biased in the subthreshold region for low-voltage low-power operation. For a 0.8-V single supply, this OpAmp has 51-dB open-loop gain, 57-kHz unity-gain frequency, 60^\circ phase margin, and 65-dB common-mode rejection ratio for 8-pF loads with a power consumption of only 1.2 \mu\W. Experimental results illustrate performances such as a 0.14-\V/\mu\s slew rate and a 750-mV linear output swing, demonstrating its correct functionality. [ABSTRACT FROM AUTHOR]

A prototype 10-bit 80-MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.25-\mum CMOS process is described. The prototype uses a combination of time-interleaved and lookahead operations to allow one clock period for comparator regeneration, reducing the bit error rate (BER) due to comparator metastability by a factor between 10^4 and 10^6. Also, the front-end sample-and-hold amplifier (SHA) previously used to provide a 1/2 clock period of regeneration time for the first-stage comparators in a lookahead pipelined ADC is eliminated refid="ref1"/, refid="ref2"/ , reducing the power consumption and the input-referred noise. The analog power dissipation is 72 mW from a 2.5-V supply. At a sampling rate of 80 MS/s, the prototype achieves a peak signal-to-noise-and-distortion ratio of 58.3 dB for an input frequency of 80 kHz. Also, for a comparator bias current of 100 \muA, extrapolations from measurements show that the BER is <10^-15 errors/sample. [ABSTRACT FROM AUTHOR]

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS analog-to-digital converter (ADC) for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate gain mismatches within channels. Moreover, the channel offset mismatches are calibrated through the digital- controlled corrective current sources embedded in the track-and-hold amplifiers of each sub-ADC. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm^2 chip area and consuming 40 mW at 2.2 GS/s from a 1 V supply. Measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate. The effective number of bits (ENOB) is 6.0 bits at Nyquist rate, and the figure-of-merit (F.O.M.) is 0.28 pJ/conv.-step. This prototype has also been integrated into a gigabit self-healing wireless transceiver SoC. [ABSTRACT FROM AUTHOR]

This paper deals with the susceptibility to RF interference (RFI) of common CMOS voltage comparators. Approximate nonlinear analysis and time-domain computer simulations are carried out to highlight the causes of the false commutations induced by the disturbances superimposed onto the nominal input signals. Through these investigations, it is shown that the response of voltage comparators to RFI depends on the comparator initial state. This effect is also confirmed by the results of measurements carried out on a CMOS voltage comparator embedded in a test chip. Based on this, a new voltage comparator that avoids false commutations induced by high-frequency disturbances is proposed. [ABSTRACT FROM AUTHOR]

Analog filter banks befit remote audio- and vibration-sensing applications, which require frequency analysis to be performed with low-power consumption and with moderate-to-high precision. The precision of a filter bank depends on both the signal-path precision (i.e., dynamic range) and also the parameter precision (e.g., accuracy of the center frequencies). This brief presents a new bandpass filter for audio-frequency filter banks and provides a procedure for designing this filter. The filter is used in a 16-channel filter bank which has been fabricated in a 0.35-\mu\m CMOS process. This filter bank has a dynamic range exceeding 62 dB and consumes only 63.6 \mu\W when biased for speech frequencies. The filter bank's parameters are set via floating-gate current sources. This brief shows how to use these floating gates to obtain a versatile filter bank that can be precisely reprogrammed to arbitrary filter spacings and frequency weightings, with a parameter accuracy exceeding 99%. [ABSTRACT FROM PUBLISHER]

We report here on the design, fabrication, and characterization of highly integrated parallel optical transceivers designed for Tb/s-class module-to-module data transfer through polymer waveguides integrated into optical printed circuit boards (o-PCBs). The parallel optical transceiver is based on a through-silicon-via silicon carrier as the platform for integration of 24-channel vertical cavity surface-emitting laser and photodiode arrays with CMOS ICs. The Si carrier also includes optical vias (holes) for optical access to conventional surface-emitting 850 nm optoelectronic devices. The 48-channel 3-D transceiver optochips are flip-chip soldered to organic carriers to form transceiver optomodules. Fully functional optomodules with 24 transmitter + 24 receiver channels were assembled and characterized with transmitters operating up to 20 Gb/s/ch and receivers up to 15 Gb/s/ch. At 15 Gb/s, the 48-channel optomodules provide a bidirectional aggregate bandwidth of 360 Gb/s. In addition, o-PCBs have been developed using a 48-channel flex waveguide assembly attached to FR4 electronic boards. Incorporation of waveguide turning mirrors and lens arrays facilitates optical coupling to/from the o-PCB. Assembly of optomodules to the o-PCB using a ball grid array process provides both electrical and optical interconnections. An initial demonstration of the full module-to-module optical link achieved >; 20 bidirectional links at 10 Gb/s. At 15 Gb/s, operation at a bit error ratio of <; 10- 12 was demonstrated for 15 channels in each direction, realizing a record o-PCB link with a 225 Gb/s bidirectional aggregate data rate. [ABSTRACT FROM PUBLISHER]

The effect of applying feed-forward equalization (FFE) on the transmitter side is studied for three different full optical links. In contrast to all previous works, the FFE settings are optimized for a complete link, rather than just the vertical-cavity surface-emitting laser output. The approach results in dramatic improvements in total link performance: >; 6 dB in sensitivity, 3X in timing margin, and 2X in power efficiency at 15 Gb/s, and a record 5.7 pJ/bit at 20 Gb/s. [ABSTRACT FROM PUBLISHER]

This paper describes a new analog-to-digital converter based on the traditional dual-slope ADC operation. With a small modification to the discharging phase of the dual-slope ADC, first-order quantization noise shaping is achieved. This quantizer is used in a second-order loop filter and results in an overall third-order quantization noise shaping. To remove the need for any extra active element, this quantizer is merged with the active adder. In this fashion, the multi-bit flash ADC is removed and hence the loading of the active-adder is reduced to a single continuous-time comparator. Furthermore, to alleviate the speed of the counting-clock and the common-mode biasing accuracy requirements, a bi-directional discharging scheme is proposed. As a proof of concept, the second-order loop filter with the proposed quantizer is fabricated in a 0.18 \mu\m CMOS technology and achieves over 78 dB SNDR with an oversampling ratio of 24 and 50 MHz sampling speed. The power consumption is 2.9 mW from a 1.5 V power supply. [ABSTRACT FROM AUTHOR]

A 4 GHz third-order continuous-time \Delta\Sigma ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 \mm^2 including the modulator, clock circuitry and decimation filter. [ABSTRACT FROM AUTHOR]

A MOS-input operational amplifier has a reconfigurable input stage that enables trimming of both offset and offset drift based only on single-temperature measurements. The input stage consists of a MOS differential pair, whose offset drift is predicted from offset voltage measurements made at well-defined bias currents. A theoretical motivation for this approach is presented and validated experimentally by characterizing the offset of pairs of discrete MOS transistors as a function of bias current and temperature. An opamp using the proposed single-temperature trimming technique has been designed and fabricated in a 0.5 \mum BiCMOS process. After single-temperature trimming, it achieves a maximum offset of \pm 30\ \muV and an offset drift of 0.33 \mu V/^\circC (3\sigma) over the temperature range of -40^\circC to +125^\circC. [ABSTRACT FROM PUBLISHER]

A new supply modulator architecture for robust performance against the battery voltage variation is presented. The resulting modulator is an optimized power management integrated circuit (PMIC) for an envelope tracking (ET) power amplifier (PA). The basic topology of the PMIC is based on a hybrid switching amplifier combining a wideband class-AB buffered linear amplifier and a highly efficient switching-mode buck converter in a master–slave configuration. The additional boost converter regulates the supply voltage of the linear amplifier, while the supply of the buck converter is directly coupled to the battery. The proposed supply modulator achieves max/min efficiencies of 76.8/69.3% over the entire battery voltage range. The ET PA is operated at 4.5 V, providing higher output power, efficiency, and gain than at nominal 3.5-V design. The robust performance of the proposed PMIC is demonstrated. [ABSTRACT FROM PUBLISHER]