Search

The development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and digital signatures. Unfortunately, most current researches have focused on the performance of the SHA-256 accelerator but not on a system level, in which the data transfer between the external memory and accelerator occupies a large time fraction. In this paper, we solve the state-of-art problem with a novel SHA-256 architecture named the multimem SHA-256 accelerator that achieves high performance at the system on chip (SoC) level. Notably, our accelerator employs three novel techniques, the pipelined arithmetic logic unit (ALU), multimem processing element (PE), and shift buffer in shift buffer out (SBi-SBo), to reduce the critical path delay and significantly increase the processing rate. Experiments on a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) show that the proposed accelerator achieves significantly better processing rate and hardware efficiency than previous works. The accelerator accuracy is verified on a real hardware platform (FPGA ZCU102). The accelerator is synthesized and laid out with 180 nm complementary metal oxide semiconductor (CMOS) technology with a chip sized $8.5\,mm \times 8.5\,mm$ , consumes 1.86 W, and provides a maximum processing rate of 40.96 Gbps at 80 MHz and 1.8 V. With FPGA Xilinx 16 nm FinFET technology, the accelerator processing rate is as high as 284 Gbps.

This paper presents the design of a compact double-loop sub-6-GHz dual-band MIMO quad-antenna system for 5G laptops. To meet the market demand for laptops with a high screen-to-body ratio, the sub-6-GHz dual-band MIMO quad-antenna system is realized to have a low-profile height of only 3 mm. To make the MIMO quad-antenna system suitable for laptops with a narrow bezel, the four antenna elements are printed on the same FR4 substrate, which is mounted on the upper edge of and coplanar with the display ground plane of a laptop. The four antenna elements have the same double shorted loop structure and the same size of $15\times $ 3 mm2. In the loop structure, a meandered path is embedded in one of the two shorted-end sections, and a series chip capacitor is embedded in the other. The low-frequency resonance mode can be adjusted by varying the meandered path, and the high-frequency resonance mode can be tuned using the meandered path and the series chip capacitor. The four antenna elements are aligned in the same direction with an end-to-end gap of 5 mm so that satisfactory isolation can be achieved without any additional isolation elements. The MIMO quad-antenna system, although measuring only $75\times $ 3 mm2 with the three gaps included, can cover 3400–3800 and 4800–5000 MHz for 5G dual-band operations. The measured isolations between the four antenna elements are larger than 10 dB, the envelope correlation coefficient (ECC) values calculated from the measured radiation patterns are all below 0.27, and the measured radiation efficiencies of all four antenna elements are over 42%.

This study reports and experimentally demonstrates a programmable on-chip photonic processor towards different RF receiver configurations. The Si3N4 processor is built by interconnecting independent subunits such as simple and complex Mach-Zehnder interferometers and Ring resonators. The design, fabrication, and characterization of a dedicated chip are described. As a proof of concept, it can be used as a reconfigurable filter with distinct frequency response. More importantly, a thorough RF receiver related passive processor including out-of-band suppression, carrier-sideband routing, channelization filtering, as well as I-Q mixing prior to an optical detection stage. This is effective proof of a programmable integrated processor encompassing most passive filtering and routing subunits for broadband photonic RF receiver.

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky barrier (SB) FinFETs for sub-10-nm gate length. The study has three subsections. First, two-transistor (2T) and 4T and-or-invert (AOI)/or-and-invert (OAI) gates with select bits that allow multiple logic functions are introduced. Second, the use of WFE to create ultracompact reconfigurable logic circuits of fundamental operations (0, 1, OR, AND, NAND, NOR, and XOR) are explored via novel 2T, 3T, and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multistage circuits, such as compact full adders, are also modeled via TCAD simulations. Power $\times $ delay product (PDP) figures and dc gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact 1-bit arithmetic logic unit (ALU), which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, addition, and subtraction) with three select bits using only 26 SB-FinFETs, saving a substantial amount of power and chip area. The tradeoffs between the number of metal work-functions used in the designs, circuit complexity, and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET-based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using $\times 3$ to $\times 10$ less power and between $\times 2$ and $\times 15$ less area than static CMOS counterparts. Although they suffer greater delays ( $\times 2$ – $\times 5$ ), the overall PDP performance remains comparable to conventional CMOS.

3D Stacked Integrated Circuits (SICs) offer a promising way to cope with the technology scaling; however, the test access requirements are highly complicated due to increased transistor density and a limited number of test channels. Moreover, although the vertical interconnects in 3D SIC are capable of high-speed data transfer, the overall test speed is restricted by scan-chains that are not optimized for timing. Reduced Pin-Count Testing (RPCT) has been effectively used under these scenarios. In particular, Time Division Multiplexing (TDM) allows full utilization of interconnect bandwidth while providing low scan frequencies supported by the scan chains. However, these methods rely on Uni-Directional Signaling (UDS), in which a chip terminal (pin or a TSV) can either be used to transmit or receive data at a given time. This requires that at least two chip terminals are available at every die interface (Tester-Die or Die-Die) to form a single test channel. In this paper, we propose Simultaneous Bi-Directional Signaling (SBS), which allows a chip terminal to be used simultaneously to send and receive data, thus forming a test channel using one pin instead of two. We demonstrate how SBS can be used in conjunction with TDM to achieve reduced pin count testing while using only half the number of pins compared to conventional TDM based methods, consuming only 22.6% additional power. Alternatively, the advantage could be manifested as a test time reduction by utilizing all available test channels, allowing more parallelism and test time reduction down to half compared to UDS-based TDM. Experiments using 45nm technology suggest that the proposed method can operate at up to 1.2 GHz test clock for a stack of 3-dies, whereas for higher frequencies, a binary-weighted transmitter is proposed capable of up to 2.46 GHz test clock.

In high-temperature reverse-bias test of an insulated-gate bipolar transistor module, the problem of self-heating in chip resulting from power loss arises with high frequency. To address this problem, the law of the variation in leakage current with temperature for the reverse-bias state of a device is derived and utilized to establish a temperature calibration curve, with which the online measurement of the insulate-gate bipolar transistor module chip temperature can be implemented directly by real-time monitoring of device leakage current in high-temperature reverse-bias test. The method we proposed solves the problem of large measurement error in chip temperature obtained by traditional thermal resistance calculation method. In addition, real-time chip temperature can be monitored without introducing additional test circuit or HTRB interruption experiment. To demonstrate the effectiveness of the proposed method, the switching small-current temperature measurement method is used to make comparison, and the experiment result indicates that the temperature of the chip in the blocking test can be obtained with high precision by using the leakage current measurement method presented in this work.

This study proposes a split-type pressure sensor based on differential capacitance that can be applied to in-situ accurate pressure testing in high-temperature environments. The sensor is mainly composed of a high-temperature resistant chip and a high-temperature resistant encapsulation structure. The chip is made of a ceramic substrate and presents a differential capacitance structure that can withstand high temperatures and effectively restrain the temperature drift. The encapsulation presents a split-type structure, in which the chip and the test circuit board are placed at the front and back ends of the sensor, respectively. Therefore, the front end of the sensor can work in the high-temperature area for in-situ testing, while the back-end temperature remains below 60°C all the time, which ensures normal operation of the circuit board. Finally, the test results show that the pressure sensor's temperature drift coefficient is only 6.6% within the temperature range of 25°C-400°C. The sensor's sensitivity can reach 9.27 mV/kPa and the maximum repeatability error is less than 2.2% at 400°C, which shows that the proposed sensor has a higher working temperature and higher precision than the existing pressure sensors.

Recent development on 3D flash memories largely promotes the wide application of Solid-State Drives (SSDs) by providing larger capacity from vertically-stacked layers. However, there exist speed variations across different layers because of manufacturing process variations or physical designs, which induces new challenges to fully explore the advantages of existing SSDs, e.g. the parallel structure. This paper investigates the effect of speed variation on the parallel performance of SSDs. To balance chips’ workloads, traditional method selects chips in a round-robin way. As chip queue time can be estimated by some main factors, the chip also can be chosen in a greedy way. However, because of the layer speed variation, queue time estimation model should be modified. This paper first establishes a new queue time estimation model with the awareness of the flash layer information. Then the model is used to estimate the chip queue time and to direct write requests into the chip with the least queue time. The key idea is to largely reduce queue time of each write, thus reducing the average SSD response time. Finally, this new request redirection method is evaluated on SSDsim with real world workloads. Experimental results show that our model can estimate the queue time more accurately and our new request redirection method can improve 8.3% of write queue time on average under the situation of 4 times speed variation among 16 layers.

We have proposed a 128-channel silicon-based optical phased array (OPA) chip with an overall antenna, and a large two-dimensional scanning range of 104.0° × 17.6° was achieved.

Microfluidic chips with the function of hydrodynamic focusing is widely used in the field of cell electroporation, droplet formation, drug screening and particle enrichment. Due to the small channel size of microfluidic chip, the existing processing methods have the defects of high fabrication cost or low dimensional consistency, the drawback is particularly prominent at small fabrication quantity. In this study, hydrodynamic focusing microfluidic chip was successfully fabricated by Liquid Crystal Display (LCD) mask photo-curing method with high efficiency and precision, the mechanism of curing parameters on the accuracy of microstructure was investigated, the hot pressing process was proposed to realize the bonding of cured photosensitive resin and glass substrate. By analyzing the focusing width of typical cross structure channel, a hydrodynamic focusing chip was designed. The effects of exposure time and single layer thickness on whole curing time was studied, the factors affecting the surface roughness were investigated, and the dimensional accuracy control method was proposed. The effect of bonding pressure on cured resin temperature was calculated and tested. The focusing width was verified by theoretical calculation and experiment. The mechanism for the inconsistency between the experimental focusing width and the theoretical focusing width was analyzed. The research proposed a solution of microfluidic design, fabrication, bonding and testing, which could provide a theoretical and methodological support for the efficient fabrication of microfluidic chips.

This article presents a quarter-rate source-synchronous PAM-4 receiver for energy-efficient chip-to-module communication. A novel single-stage multiple peaking continuous-time linear equalizer (MP-CTLE) using feedback enabled multiple peaking scheme for both high-frequency equalization (HF-EQ) and low-frequency equalization (LF-EQ) is proposed to improve the BER performance and overall energy efficiency. The LF-EQ of the MP-CTLE eliminates the need for many DFE taps in SR/VSR applications to save power and area. A 1-tap feedforward equalizer (FFE) is used to further compensate for the high-frequency loss. We also use a ring oscillator based wide bandwidth phase-locked loop (WBW-PLL) as the multiphase clock generator (MPCG) in the clock and data recovery loop to save power with acceptable phase accuracy. Fabricated in 40-nm CMOS technology, the prototype receiver chip achieves error-free operation up to 52 Gb/s PAM-4 with superior bit efficiency of 0.126pJ/bit/s/dB while compensating 7.3-dB channel loss at 13GHz. With the proposed single-stage MP-CTLE, the receiver extends the error-free operation from PRBS-7 to PRBS-9. The BER bathtub curve at $10^{-6}$ is improved from 0.018 UI to around 0.1 UI.

This paper proposed a light-emitting diode (LED) automatic lighting system for plant factories. This system can achieve the simultaneous effects of automatic dimming and seven-segment mixing; the light intensity and color can therefore be adjusted according to the properties of the plants to increase crop harvest. The operation method comprises detection of the light source through a photosensitive diode CdS, and sending the analog value obtained from the light intensity to the single chip dsPIC30F4011 for analog-to-digital conversion. This single chip stores the digital value in the internal pulse width modulation (PWM) register and outputs it to the dimming circuit to achieve the effect of automatic dimming. In addition, the operator can also connect to the system using smartphone Bluetooth and an ATmega328 single chip and manually select the color of the light source through the human–machine interface. The ATmega328 chip receives the operating signal and transfers it to the dsPIC30F4011, which automatically changes the PWM output channel to achieve seven-segment light mixing.

Future many-core systems need to address the dark silicon problem, where some cores would be turned off to control the chip’s thermal and power density, which effectively limits the performance gain from having a large number of processing cores. Task migration technique has been previously proposed to improve many-core system performance by moving tasks between active and dark cores. As task migration imposes system performance overhead due to the large wake-up latency of the dark cores, this paper proposes a prediction-based early wake-up (PEW) to reduce the dark cores’ wake-up latency during task migration. A window-based online ridge regression (RR) is used as the prediction model. The prediction model uses the past window’s thermal, power, and core status (i.e., active or dark) to predict the future core temperatures at run-time. If task migration is predicted in the next control period, the proposed PEW puts the dark cores in a power state with low wake-up latency. Thus, the proposed PEW reduces the time for the dark cores to start executing the tasks. The comparison results show that our proposed PEW reduces the completion time by up to 7.9% and 4.1% compared to non-early wake-up (NoEW) and a fixed threshold wake-up (FEW), respectively. It also shows that the proposed PEW increases the MIPS/Watt by up to 5.5% and 2.3% over NoEW and FEW, respectively. These results show that the proposed PEW improves the many-core system’s overall performance in terms of reducing dark cores’ wake-up latency and increasing the number of executed instructions per Watt.

This paper presents design, mathematical analysis, and measurement of low noise single-stage transimpedance amplifier (TIA) with scalable bandwidth using 130 nm bipolar complementary metal-oxide-semiconductor (BiCMOS) silicon-germanium (SiGe) process. Common-emitter (CE) shunt-shunt feedback topology with active inductor peaking has been used in the design for improving noise, gain and driving capability of TIA by decreasing the input and output impedance, respectively. The use of active inductive peaking in CE shunt-shunt feedback topology has resulted in a new TIA configuration with better performance. The circuit has been optimized for low noise by adopting the proposed design technique. Validity of the mathematical analysis and design for the proposed TIA has been established with the help of simulations as well as measurement results. The measurement results of Ku-band TIA (10 MHz to 14 GHz) have demonstrated a transimpedance gain of $53.2~dB\Omega $ , input-referred current noise of 16.8 pA/ $\sqrt {Hz}$ with power consumption of $9.8~~mW $ . The design architecture is adaptable for higher frequency bands, which has been demonstrated by designing another TIA covering K- and Ka-bands (10 MHz to 35 GHz) with transimpedance gain of 33.4 dB $\Omega $ , input-referred current noise of 29.4 pA/ $\sqrt {Hz}$ with power consumption of $28.1~~mW $ in the post-layout simulation results, and occupies same chip area as that of 14 GHz, i.e., $0.1\times 0.21\,\,mm^{2}$

The advent of mini-light-emitting diodes (mini-LEDs) represents a recent advancement in display technology. The biggest advantage of mini-LEDs over traditional backlight LED panels is that the LED array facilitates the local dimming of light intensity. This paper presents a large-view-angle (LVA) GaN-based mini-LED chip with batwing angular light distribution. By placing a translucent layer on the mini-LED, the angular light-intensity distribution can be modified from the Lambertian type to that resembling a batwing using translucent sublayer pairs. Compared to conventional mini-LEDs, the proposed mini-LED chip requires fewer LEDs and a shorter light-diffusing distance to maintain good uniformity without additional lens packaging. Further, the increased sublayer pair count in the translucent layer affords an increase in the radiation half-power angle from 137.5° to 173.2°. This increases the half-power angle of the mini-LED array from 47.4% to 89.1%. The findings of this study demonstrate significant potential for use in the development of ultrathin backlight panels, which are finding commercial utility in modern television designs. This work should provide the applications solution in mini-LED backlit and wide color gamut RGB backlight display.

We propose a coupled-tolerant subwavelength photonic racetrack resonator (PRR) on the silicon-on-insulator (SOI) platform, in which a subwavelength grating (SWG) PRR is coupled to a symmetrical SWG bus waveguide. The material equivalent refractive index can be manipulated by the SWG characteristic and thus an additional fabrication degree of freedom can be achieved. The resonant characteristics can be improved significantly by controlling the pillar size and increasing the interaction length between SWG racetrack and bus waveguide (RBW). The simulation results show that the PRR has a high-quality factor and large extinction ratio around 1550nm. Two groups of SWG and strip waveguide (SW) PRRs are fabricated. The fabrication tolerance is tested when fabrication error is changed from 0 to 20 nm and the quality factor is more than 7000 in de-ionized water. The testing results show that the tolerance in SWG-PRR has a 2.0-fold improvement than that in the SW-PRR. Then a fabricated SWG-PRR is employed to monitor different concentration glycerol injected on the chip. An optimal quality factor of 9500 around 1550 nm and bulk sensitivity of 412± 0.5 nm/RIU are achieved. Therefore, the structure is a potential candidate for label-free sensing in medical diagnosis and environmental monitoring.

In this paper, we propose a multi-chip architecture based on parallel frame rendering suitable for real-time ray tracing in dynamic scenes. In multi-chip architecture with the commonly used screen partitioning method, the acceleration structure data, such as a tree, updated in a dynamic scene must be transmitted to each chip. In the proposed frame division method, a tree build and ray tracing are performed on the same chip, and each frame is allocated to a predesignated multi-chip. Thus, the proposed method can achieve scalable performance improvement not only of ray tracing but also of a tree build. We implemented a multi-chip architecture on three field-programmable gate array (FPGA) boards and built 12 ray-tracing cores in the FPGA chip of each board. This configuration means that the inter-chip operates using the frame division method, while the inner chip operates using the screen partitioning method. The results of experiments showed that the proposed multi-chip architecture improved frames per second (FPS) performance by an average of 2.83 times compared to a single-chip architecture.

This paper presents a wearable optical health monitoring device embedding a monolithic sensor chip with newly designed pixels, and an optical module optimized for photoplethysmography (PPG). The monolithic optical sensor at the heart of this device implements an array of novel pixels designed specifically for PPG and featuring a quantum efficiency (QE) as high as 85%. The sensor readout chain, as well as the logic circuits, implements low power design techniques leading to only 60 $\mu \text{A}$ current consumption at 122 Hz operation frequency, including digital communication. Thanks to the high QE and optical module optimization, medical grade PPG recordings are enabled with less than 10 $\mu \text{A}$ emitter current. The optical sensor is embedded in an ergonomic ring device together with system electronics in order to enable in-field test of beat detection accuracy on 7 subjects. The ring device detects correctly 97.87% of the beats on a total of 72.21 hours of recording. The inter-beat interval (IBI) estimation from these recordings features a mean absolute error (MAE) as low as 8.10 ms. This performance is achieved with less than 70 $\mu \text{A}$ current consumption at the level of the PPG module.

The electronics world is very well described in two distinct but dependent interdisciplinary areas, namely hardware and software. Arithmetic operations are very vital building blocks of an electronic system. An algorithm is a systematic arrangement that helps develop a sophisticated electronic system, including hardware and software aspects. Addition, subtraction, multiplication, and division are critical elements of arithmetic implementation in the electronic system, but fewer efforts have been made to implement division than other arithmetic operations, even though the number of transistors on a chip is increasing beyond the Moore’s law prediction. It is quite complicated to implement arithmetical operations; here, a sophisticated algorithm is essential to successful implementation. Technological upgrades are leading to a new paradigm of applications, where the performance of a division circuit or block is a vital and critical feature of a successful system. The lexicon of algorithms used in the implementation of the division operation in electronics systems is discussed in detail in the present article, which indicates the mathematical formulation, criticality, conversion pattern, hardware requirements, and logic used for conversion. The current report describes the broad classification of dividers into basic classes named digit recurrence, high radix, functional iteration, estimation, a look-up table, and variable latency. It also illustrates that, in practical implementation, many algorithms have been developed that combine one or many classes and are implemented with different hardware architectures. The study indicated the possibility of improving the presently available algorithms or creating a new algorithm to enhance practical implementation.

This article presents a cryptographic key protection technique from physical security attacks through Si-backside of IC chip. Flip-chip packaging leads to a serious security hole that allows emerging backside physical security attacks. The proposed backside buried metal (BBM) structure forming a meander wire pattern on the Si-backside detects unexpected disconnection of the meander and warns the malicious attempts to expose a vulnerable Si substrate. Moreover, the BBM meander also shields key information of cryptographic circuit from both passive side-channel attacks and active laser fault injection as well. Unlike other conventional laminate-based protection, this backside monolithic approach does not require frontside wiring resources or additional packaging layers, resulting in only 0.0025% size-overhead. The BBM meander was formed on the backside of a 0.13- $\mu \text{m}$ CMOS cryptographic chip by wafer-level via-last BBM processing.

Monitoring system-on-chip performance under process, voltage, and temperature (PVT) variations is very challenging, especially when the parasitic effects dominate the whole chip performance in advanced process nodes. Most of the previous works presented the performance monitoring methodologies based on known/predicted candidates of critical paths under different operating conditions. However, those methodologies may fail when the critical path is misrecognized or mispredicted. This paper proposes a novel machine-learning based chip performance monitoring methodology to accurately match the chip performance without requiring the information of critical paths under various PVT conditions. The experimental results based on measured chip performance show that the proposed methodology can achieve 98.5% accuracy in the worst case under wide-range PVT variations.

Deep learning (DL) accelerators suffer from a new security problem, i.e., being vulnerable to physical access based attacks. An adversary can easily obtain the entire neural network (NN) model by physically snooping the memory bus that connects the accelerator chip with DRAM memory. Therefore, memory encryption becomes important for DL accelerators to improve their security. Nevertheless, we observe that traditional memory encryption techniques that have been efficiently used in CPU systems cause significant performance degradation when directly used in DL accelerators, due to the big bandwidth gap between the memory bus and the encryption engine. To address this problem, our paper proposes SEAL, a Secure and Efficient Accelerator scheme for deep Learning to enhance the performance of encrypted DL accelerators by improving the data access bandwidth. Specifically, SEAL leverages a criticality-aware smart encryption scheme that identifies partial data having no impact on the security of NN models and allows them to bypass the encryption engine, thus reducing the amount of data to be encrypted without affecting security. Extensive experimental results demonstrate that, compared with existing memory encryption techniques, SEAL achieves 1.34 – 1.4× overall performance improvement.

Trends in high pin density and an increasing number of routing layers complicate printed circuit board (PCB) routing, which is categorized as escape and area routing. Traditional escape routing research has focused on escape routing but has not considered the quality of area routing among chip components at the same time. In this work, we propose a complete PCB routing methodology, including simultaneous escape routing (SER), post-SER refinement, and gridless area routing. The SER completes the layer assignment of all nets and produces an escape order ensuring suitable escape and area routing on each layer. Length-matching constraints and differential pair routing are satisfied in each stage of the routing flow. The experiment results indicate that the proposed PCB routing method can complete routings for seven commercial PCB designs, whereas the commercial PCB tool cannot complete any of them.

Modern GPUs employ thousands of cores, yielding higher performance but also higher power consumption. To meet performance targets while staying within a reasonable power budget, designers have to make these execution cores increasingly more power efficient. One way to increase their power efficiency is to employ power-efficient adders. In this paper, we observe that consecutive arithmetic computations from the same code location are highly correlated and propose ST2 GPU, a GPU architecture that uses history-based speculative adders that produce guaranteed correct results while saving 70% of the nominal adder power. We estimate that ST2 GPU saves 21% of the GPU chip energy with practically no performance and area overheads.

Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing (CMP) process in VLSI manufacturing. This paper proposes a novel model-based dummy filling synthesis framework NeurFill, integrated with multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver. Inside this framework, a full-chip CMP simulator is first migrated to the neural network, achieving $8134 \times$ speedup on gradient calculation by backward propagation. Multi-modal starting points search is further applied in the framework to obtain satisfying filling quality optimums. The experimental results show that the proposed NeurFill outperforms existing rule- and model-based methods.

Chiplet based multi-die integration has been thought as a key enabler of the agile chip development flow. For 2.5D based multi-die system, Network on Interposer plays an essential role in the performance and the development cost of the chips. This work proposed a reusable NoI design for agile AI chip customization. The proposed NoI design can self-adapt to the inter-die communication patterns of various neural network applications, so the produced interposers can be reused across different AI chip specifications. Experimental results show the proposed NoI design brings 42.7%$\sim$79.5% of total data communication latency reduction in different scenarios, and it also decreased the area overhead by 26.4%.

The goal of this paper is to provide worst-case timing guarantees for real-time I/O requests, while fully utilizing the potential bandwidth for non real-time I/O requests in NAND flash storage systems. We identify a trade-off between flash chip sharing and I/O workload isolation in terms of timing guarantees and bandwidth. By taking such a trade-off into account, we propose a new real-time I/O scheduling framework that enables dynamic isolation between real-time I/O requests to meet all timing constraints and co-scheduling of real-time and non realtime I/O requests to provide high bandwidth utilization. Our in-depth evaluation results show that the proposed approach outperforms existing isolation approaches significantly in terms of both schedulability and bandwidth.

This study aims at comparing two subthreshold flip-flop architectures in frequency divider applications, implemented and fabricated in 130 nm CMOS process technology. They are the Power PC (Performance Computing) and Nand race-free flip-flops. Identification of a reliable and power efficient flip-flop, used in a frequency divider for ultra-low supply voltages, has been verified by measurements. The simulated results based on a netlist extracted from layout show that upsizing the Power PC flip-flop increases it's reliability while it may still provide lower power consumption than the Nand race-free flip-flop. Based on results verified by measurements for ten chip samples, both frequency dividers have demonstrated functionality down to a V dd of 135 mV. The Power PC flip-flop based frequency divider is 24% more energy efficient than the Nand race-free counterpart at an ultra-low supply voltage of 160 mV. The energy per operation for the Power PC- and Nand race-free- frequency dividers at the minimum energy point (MEP) of 250 mV, and maximum operating frequency, are 12.2 and 12.5 fJ, respectively.

In this work an analysis, design and layout of two start-up methods for high-voltage switched-capacitor converters is presented. During the converter start-up phase, the capacitors are charged from their initial voltage to their steady-state voltages. If a start-up approach is not considered, this creates undesired large currents in the power switches and chip I/Os, which can damage the chip. A 48 V −12 V switched-capacitor converter with an integrated power stage and external capacitors is designed and taped out in a 180 nm SOI CMOS process to demonstrate two different approaches of mitigating the start-up problem. The first approach solves the uneven capacitor charging during input ramp-up by creating a charging path from the input to the capacitors and carefully sizing the capacitors. The second approach charges the capacitors with a dedicated active pre-charging circuit and thereby ensures limited peak currents during start-up of the designed switched-capacitor converter. This first start-up method reduces the start-up peak current from 40 A to 6.5 A and the second method lowers the peak current to 3.5 A. The designed pre-charge circuit consumes 105µA quiescent current and has an area of 743µm x 911µm.

In this paper, a pseudo-noise (PN) code tracking method of optical-wireless code-shift-keying systems using two-layered PN codes is considered. A new tracking system that uses the two delay lock loops (DLL) is proposed. The two-layered PN codes used in this paper consist of spreading each chip of the selected modified pseudo-orthogonal M-sequence sets (MPOM) code, called outer PN code, with other MPOM code, called inner PN code. Therefore, the two DLLs of the proposed method are used in a suitable form for outer PN codes and inner codes of two-layered PN codes. In this paper, the symbol error rate taking into account jitter is evaluated.

The modified electroconvulsive therapy is an effective method for the treatment of severe depression and some other mental and nervous system disorders. In this paper, an electrical stimulation device for modified electroconvulsive therapy is designed. The device uses STM32F103ZET6 as the main control chip, and the constant current source circuit and H-bridge drive circuit are designed to output the stimulus pulse. The serial port screen is used as the human-computer interaction medium to set the stimulation parameters and control the output of the electrical stimulator. The operation is simple and the human-computer interaction is friendly. The experimental results show that the output pulse waveform of the electric stimulation device is good and the stimulation parameters reach the set target value.

As for the phenomenon of explosion failure of IGBT power module in the short-circuit current test, a new failure model of multi-chip module caused by the failure of reverse recovery anti-parallel diode chip is proposed. Based on the proposed model, various influence factors from the aspects of circuit layout and device mechanism are analyzed and discussed. By investigating the position and fault waveform of the internal chip and anti-parallel diode of IGBT power module, as well as the physical analysis after power module unraveling, we can conclude that the uneven current density of the anti-parallel diode chip that leads to the dynamic avalanche breakdown is the main reason of the explosion failure of the IGBT power module. Finally, suggestions for improving the firmness of the IGBT power module are given, which is of guiding significance to the design and manufacture of IGBT.

With the continuous development of deep sub-micron technology, the design scale of integrated circuits is getting larger and larger, and more and more interfaces between SOC and the outside, which poses more challenges to the physical design of integrated circuits. For large-scale SOC, it requires a lot of work to place and route the PADs by manual, what’s the worse, this work can always be with high error rate. In order to solve this problem, an original physical design method which uses scripts to place the PADs is created to realize the automatic arrangement of complex SOC PAD. This method is suitable for any SOC with separated IO and PAD. The form and parameters of the scripts can be adjusted according to the specific process, so as to realize the automatic PAD arrangement, shorten the physical design period, and speed up the time to get into the market. This method has been applied in many products of the company, such as PLC chips, ADC chips, MCU chips, RFID chips, etc.

Developed a positioning environment sensing multi-parameter tester that can be used by robots and miners. It uses a 16-bit ultra-low power microcontroller chip as the control core, combined with electrochemical carbon monoxide sensing elements, electrochemical oxygen sensing elements, and electrochemical hydrogen sulfide sensing elements, infrared methane sensing elements, and temperature sensor elements are designed to realize real-time monitoring and early warning of dangerous gas information in the surrounding environment of underground workers or robots. Combining device selection and circuit design to solve the cross-effect problem of catalytic methane element and hydrogen sulfide gas element in the current multi-parameter tester. And combining device selection and circuit design to solve the cross-effect problem of catalytic methane element and hydrogen sulfide gas element in the current multi-parameter tester. Besides, combined with wireless module, it can be connected to the monitoring system, and combined with DW1000 chip and UWB positioning technology to integrate the analyzer in the precise positioning system. Combined with the model design correction algorithm to improve the accuracy of distance measurement and positioning. Through the reserved serial port to realize the positioning and environmental information interaction between the robot transmission part and the measuring device.

Carrier frequency principles with synchronous de-modulation offer several advantages for use in capacitive sensors, in particular with respect to suppression of external disturbers, coexistence of sensors, and capability to determine frequency-dependent changes of the capacitance/impedance. A key component in such systems is the generation of the excitation signal(s) as well as the reference signals for demodulation.This work focuses on the early functional evaluation of direct digital synthesis for such signals using a virtual prototype in SystemC AMS (IEEE 1666.1), a high-level synthesis approach based on C (ISO 9899) as well as a classic hand-written VHDL code (IEEE 1076) for a rapid prototyping setup. The methods are compared with respect to efforts and results showing the advantages and disadvantages in a qualitative fashion. The lower efforts and lower risk of errors in the code provided by high level meta modeling allows to speed up the development cycle and required application dependent adaptations of signal generation in carrier frequency based capacitive sensor front-ends.

With the advent of the fourth industrial revolution i.e. Industry 4.0, plants and factories are becoming smarter and interconnected. The transitions demand vertical integration and seamless connectivity. For this purpose, there is a need for semantic communication between various devices including the heavily resource-constrained field devices. To address this, a real-time capable hardware-based implementation of a well-established semantic communication protocol, i.e. OPC Unified Architecture was designed and developed. This chip-based implementation is power-efficient and compact, making it suitable for the field level. The chip was analyzed and incorporated in a demonstrator as a proof of concept of its integration at field level in a plant module of the process industry. Various opportunities are also examined where the chip could be utilized to deliver benefits to existing and future technologies.

This work focuses on several synthetizations developed in both 32nm and 500nm technologies to evaluate the performance differences of MD5 Crypto-Processor. We decided to conduct a topographical synthesis instead of a nontopographical synthesis as it takes more parameters into account to create a more accurate design. We started by comparing some basic cells like inverters and register banks to understand the main differences between the two technologies. Several approaches were considered at this point to understand how different synthetization parameters affect the chip performance and characteristics. These different approaches were focused on time, power and area, and balanced configurations of synthesis flow. Finally, after comparing the performance given by the different approaches in basic digital structures, the balanced approach was implemented in 32nm and benchmarked with the 500nm implementation. Our conclusions were consistent among the various tests conducted and by downscaling we can expect a 10x increase in the clock frequency, a 100x decrease in power consumption, and around a 300x decrease in the area while using the 32nm technology. As a result, we developed a method to fairly compare complex systems to allow a designer to consider if the benefits justify the costs for a technology change.

Two-position measurement for fluorescence of a single cell captured in a microfluidic chip has been conducted manually. This paper describes the automation accomplished on moving the chip back and forth at two definite positions by a robotic arm controlled with a computer using Python codes. A single lung cancer cell was captured in the chip; measurements at two positions (cell and background) were automated to demonstrate the signal enhancement due to more accumulated reagents.

The promoted low power dissipation voltage-controlled oscillator (VCO) with low-pass filter of fifth order curer and low pass sigma-delta (ΣΔ) modulator are fabricated with tsmc 0.18 µm CMOS processing for phase-locked loop (PLL) controlled applications. The proposed dual-band current reusing VCO is used divided-by-2 to adopt low power dissipation, power saving and enhance performance. The proposed switching capacitors of dual-band ΣΔ modulator and filter optimized core chip area is report for PLL controlled applications.

This paper presents the design of 8-bit asynchronous based binary search analog to digital converter (ADC) using split design topology. In the proposed work, the 8 bits had been realized using two stages of 4 bits each with a subtractor in between. The use of such asynchronous design had resulted in reduction of switching network, reduced number of comparator and improvement in speed and chip area. The proposed 8-bit ADC is designed in 0.18 μm CMOS process and realizes conversion rate of approximately 230 MS/s while consuming 11.5 mW of power with 50% saving of chip area and 16% improvement of speed in comparison to other design. The proposed design achieves 6.22 pJ/conv-step of Walden FOM.

A systematic left to right process variation is observed across a 20 nm technology chip. Consequently, reference generators and amplifiers which are scattered around the chip undergo severe performance fluctuations. In this paper, we present a design methodology that is used to scale down the influence of systematic variation on circuit performance. The physical centre of the die is tapped and routed to the voltage generators as a feedback to minimize the left and right performance deviation. Optional connection cells are implemented in order to program and tap the feedback path whichever is closest to the physical centre accordingly.

With the rise of the use of CPU-based Systems on a Chip (SoCs) in critical applications, the need to comply with harsh environments such as radiations or environmental fluctuation of parameters where they will evolve is essential. Devices must be qualified using Accelerated Soft-Error Rate (ASER). They are irradiated with neutrons, heavy ions, protons, or alpha particles depending on the mission profile. In addition, high frequency and complex computing tasks make SoCs difficult to observe and origin of errors difficult to identify. Radiation-induced Single-Event Effects (SEEs) are then hard to interpret. In this paper we present the Fail-Reason Capture (FIRECAP) Intellectual Property (IP). This IP is embedded in a SoC and allows probing and recording processor resources. Recording is controlled by hardware watchpoints that are triggering actions when hit. In addition, illegal jump traps have been added in the memory, such as deadcode traps around program loops and Error Capturing Instructions (ECI) spread in unused memory. The FIRECAP IP is interfaced to a RISC-V based SoC. Probes are implemented on the PC, IR, SP and RA registers of the processor. Two SoCs are integrated in a 28-nm FDSOI test chip. The failure mode coverage and observation points have been evaluated through a fault injection campaign done in simulation, then experiments using Electromagnetic Fault Injection (EMFI) on the device are presented.

A new method of bonding the solid photoresist film is proposed for improving the thickness uniformity on the chip substrate. The water-soluble polymer supports the resist film and is dissolved before patterning. The chip area can be used up to the edge. The resist thickness demonstrated is 1.73 μm +/−1.2% in maximum deviation.

Multi-stack chips comprised of sapphire and Nd3+:YAG crystals with variable doping concentration were made by surface activated bonding technology. By use of sophisticated amplification setup for end-pumped solid-state laser, >2J operation with nanosecond pulses was obtained under room temperature.

A low thermal budget (≤ 250 °C) chip-to-chip and chip-to-wafer three-dimensional (3D) integration of application-specific smaller artificial intelligence (AI) chips (2.5 mm × 2.5 mm) with 6 level metal (M#) layers were carried out by using TSV (Through – Si - Via) - last method. Several back-end-of-line processes were carefully optimized, such as multi-die thinning, M1 revealing, protection of revealed M1 during TSV metallization, die-level Cu-chemical mechanical polishing for re-distribution layer formation, and μ-bumping were carefully optimized. The diode parameter evaluation for the chips before and after 3D-integration revealed the successful fabrication of AI module for specific applications.

Anodic bonding is in general a very attractive low temperature bonding method. Utilizing the progress in glass structuring and with adapted bonding conditions it can be used for CMOS-MEMS integrated wafers enabaling very complex, multifunctional chip solutions.