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in this paper, we demonstrate a high density heterogeneous large package using a RDL interposer with six interconnection layers. Four Si chiplets and two HBM modules are connected with fine pitch copper lines to deliver a complete system-in-package solution for high performance computation. The multilayer interconnections provide excellent design flexibility to optimize signal, power, and ground planes. The RDL interposer has generic structural advantages in interconnection integrity and bump joint reliability, which allows further scaling up of The package size for more complicated functional integration.

A 40 nm charge-trap embedded NVM technology is presented which is operational at the main power supply of 0.81 to 1.21 V. It is based on SONOS and requires only five extra masking steps beyond standard CMOS. A product-ready 8Mb macro is used to demonstrate technology capabilities. Key features are 25 ns read access time in the 0.99 to 1.21 V supply range and very low current consumption. The macro provides several power- saving modes, 100k write cycles and 10-year data retention for application in consumer and industrial SoCs.

The size of the plastic ball grid array (PBGA) package is getting smaller, and the problem of delamination in packaging has become more important. Therefore, in this study, the packaging process is improved through the finite element analysis (FEA) to analyze the delamination in the packaging components. First, the model of sealing and lamination is built through uniform design method (UDM) with Kriging model and response surface methodology (RSM). Then, the differences between these methods are investigated. The optimal parameters are obtained by UDM and RSM that the mold pressures are 31.7 and 42.57 MPa, temperature is 171.61 and 185 °C, and shoulder width is 358.33 and 800 μm, respectively. Due to process factors of sealing and lamination has an interaction with each other, the RSM in this case is more accurate. Therefore, the result obtained by RSM is more appropriate for the process.

In this paper, we focus on electronics industry by now, in the manufacturing process, the servo system of the position of the alignment platen to do a study on methods of improving the software, which aims for the measurement system in the circuit board lamination. Characteristic marker can do accurate alignment. In our method, as do the pre-photographic image pre-processing to detect and record the image in the location of the marker, then according to the measurement system captured images do wavelet transform and reduce the image size to improve performance, supplemented by 2: 1 candidate region search. That can do to enhance performance. By the actual experimental results can also be seen, this study found the correct way to position objects, and the time performance can finally improve.

Accelerated temperature lifetesting at T channel of 240, 255, and 270 °C was performed on 0.1-μm Pt-sunken InP HEMT low-noise amplifiers fabricated on 100 mm InP substrates. The reliability performance was evaluated based on ΔS21 channel of 125 °C. The high reliability demonstration of 0.1-μm Pt-sunken gate InP HEMT low-noise amplifiers on 100 mm InP substrates is essential for advanced military/space applications requiring high reliability performance.

Reliability performance of 0.1-µm Pt-sunken gate InP HEMT MMICs on 4-inch InP substrates was evaluated under elevated temperature lifetesting. The primary degradation mechanism was observed to be the progressive Schottky junction reaction with the Schottky barrier InAlAs and the InGaAs channel. Despite the progressive Schottky junction reaction with the InAlAs and InGaAs materials, the lifetest at T ambient of 280 °C projects the median-time-to-failure exceeding 1×106 hours at T channel of 125 °C. This result indicates that the promising initial reliability performance was achieved on Pt-sunken gate InP HEMT MMICs on 4-inch InP substrates.

For the first time, the sub-mW operation of InP HEMT X-band low-noise amplifiers on 4-inch InP wafer was demonstrated. With optimized non-alloyed ohmic contact, gate recess profile and epitaxial layer design, the InP HEMT achieves average peak transconductance of 1150 mS/mm at VDS=0.3 V. The mean current cut off frequency is above 150 GHz at VDS= 0.3 V and IDS= 150 mA/mm. The developed low power InP HEMTs enables the manufacturing of low-noise amplifiers for low power applications. The superior performance of X-band low-noise amplifiers was also demonstrated. Operating at a supply voltage of 0.25 V and drain current of 3.75 mA with DC power of 0.937 mW, the low noise amplifier exhibits noise figure of 1.6 dB and gain of 11 dB at frequencies from 6 to 12 GHz.

A wafer-level-packaging technology was used to integrate the 0.1 µm AlSb/InAs HEMT low-noise amplifiers with power amplifiers, switches and phase shifters to form a compact tri-stack transmit/receive module for light-weight and ultralow-power applications. The high manufacturability of AlSb/InAs HEMT receivers operating at 0.9 mW was demonstrated on a tri-stack wafer. This demonstration of manufacturable tri-stack transmit/receive modules is essential for phased-array applications requiring light weight and ultralow power.

An InGaAs/InAlAs/InP HEMT has been fabricated with 0.15µm EBL gate, double gate recess and improved Ohmic contact. While maintaining a peak transconductance (Gmp) in excess of 1000mS/mm, an onstate burnout voltage exceeding 8V and an operating drain voltage of 5V have been achieved. A loadpull measurement at 40GHz was conducted. An output power density of 471mW/mm, a power-added efficiency of 38% and a power gain of 8dB were demonstrated, making this technology attractive for power applications at millimeter wave frequencies.

The use of CFD for thermal analysis in the design of electronic devices has proven to be cost effective and time saving in the ever decreasing product development life cycle, However when the product involves components with several orders of magnitude in length scales, and comprises many fine features which may not be easily simplified because of their random nature, the ability to predict an accurate peak temperature may be called into question. In this paper, a multi-level approach, using compact modeling techniques at the larger scale level, is proposed to deal with the problem of handling fine features within a board or component level simulation, without the needs of a super computer. But increasing detail of the features is represented at the smaller scale levels while maintaining consistency in the boundary conditions between the larger and smaller scale models. This methodology not only identifies the hot spot locations and anticipates the heat distribution pattern, but can also predict peak temperatures within the fine features with more accuracy which are essential for failure analysis of critical features. Using a test vehicle which comprises numerous microvias subjected to different powering modes, it has been shown that the predicted peak temperatures in the critical features can rise by over 12degC as the level of the detail increases. This illustrates the importance of using the multi-level approach when dealing with thermal analysis involving several orders of magnitude in length scales.

A three-stage W-band InGaAs/InAlAs/InP HEMT Low-Noise Amplifier (LNA) has been fabricated with 0.1mum EBL gate and improved Ohmic contact. A noise figure of 2.5 dB with an associated gain of 19.4 dB is demonstrated at 94 GHz. To our knowledge, it is the best noise/gain performance in a W-band LNA ever reported. A noise figure of 2.7 dB and an associated gain of 14.6 dB is also demonstrated with a dc power of 3.6 mW, making it a viable alternative to the ABCS technology for low dc power LNA applications.

The degradation mechanisms of 0.1 mum AlSb/InAs HEMTs subjected to elevated-temperature lifetesting at three temperatures in N2 atmosphere were investigated. Device degradation exhibits the increase of non-pinch-off drain current (IDS), the decrease of transconductance (gm) and the gate current (IG) increase. The IG increase was found to correlate with material degradation on the gate-recess and Al0.7Ga0.3Sb-mesa-floor surfaces. Higher oxygen content was detected on these surfaces, indicating that they were modified by oxidation, which resulted in the IG increase. Despite the degradation observed in 0.1 mum AlSb/InAs HEMTs, the three-temperature lifetesting shows that the activation energy (Ea) is approximately 1.5 eV and demonstrates a median time to failure (MTF)of 2times106 hours at Tjunction of 85degC. This reliability result is essential for successful insertion of AlSb/InAs HEMTs into systems with ultralow-power requirements. Moreover, ohmic-metal lateral diffusion of Pd and Au elements was observed. To avoid potential ohmic-metal-lateral-diffusion induced device failure, lifetesting temperatures were kept below 190degC in this investigation.

Three-temperature lifetesting was performed to evaluate the reliability performance of 0.1 μm AlSb/InAs HEMT low noise amplifiers (LNAs) for ultralow-power applications. For the first time, the reliability performance of 0.1 μm AISb/lnAs HEMT LNAs was demonstrated. The results show a median time to failure of approximately 2x106 hours at Tjunction of 85°C with activation energy of 1.5 eV. High-reliability performance is essential for successful insertion of 0.1 μm AISb/lnAs HEMT LNAs for military and space applications with ultralow-power requirements.

A 0.1 mum n+-InAs-AlSb-InAs MMIC technology was developed for phased-array applications requiring ultralow power consumption. An n doped cap layer was utilized to provide lower access resistance and to reduce detrimental effects of cap layer etching during the process. As a result, the performance and manufacturability can be enhanced. In this work, we have demonstrated excellent DC and RF uniformity on both devices and low-noise amplifiers (LNA) using 0.1 mum n+-InAs-AlSb-InAs HEMTs on 3-inch GaAs substrates. In addition, the LNAs also demonstrate excellent RF performance while operating at ultralow power (~1 mW). This accomplishment is crucial for phased-array applications requiring ultralow power dissipation.

This paper describes a manufacturable and reliable 0.1 μm AlSb/InAs MMIC technology for ultra-low power applications. AlSb/InAs HEMTs have been demonstrated with only one-tenth power dissipation of conventional InAlAs/InGaAs/InP HEMTs. The uniform DC and RF performance of AlSb/InAs HEMTs have been demonstrated on 3-inch GaAs substrates. The further demonstration of reliable AlSb/InAs HEMT technology warrants the successful insertion of AlSb/InAs HEMT MMICs for military and space applications with ultra-low power requirements.

Uniform millimeter wave 0.1 mum InP HEMT MMICs (Ka-band, Q-band, W-band, and distributed amplifiers) on 100 mm InP substrates have been demonstrated. Moreover, high performance and high reliability have been achieved. The results indicate that the readiness of 100 mm InP HEMT technology for insertion to support military/space applications.

In this paper, the impact of ball bonding (BB) induced voltage transient on the reliability test including electro-migration (EM), time dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) and electro-static discharge (ESD) are investigated. During the electronic flame-off (EFO) of ball bonding process, a spark discharge current, which applies a high electric field between the wire and wand, is used to melt the wire to form a free air ball (FAB). In the mean time, however, the spark may generate ions in the air and some of them may charge to die for package. After free air ball was bonded to pad, a BB-induced voltage transient can be measured and may impose an electrical stress to devices, then to degrade the device lifetime if without suitable I/O protection circuits. The degradation mechanism can be considered as charge device model (CDM) electrostatic-discharge (ESD) event. To remove or reduce this package-induced damage, ionizers had been put closely to the bonding tool and showed very good package yield, compared to those without ionizer.

A 0.1 μm In02Al08Sb-InAs HEMT MMIC technology was developed for phased-array applications with ultralow-power and oxidation-free requirements. An In02Al08Sb layer was utilized to replace the upper AlSb layer in the conventional AlSb-InAs HEMT in order to mitigate the oxidation incurred by the AlSb layer. In this work, we have demonstrated excellent dc and rf performance on both devices and low-noise amplifiers (LNAs) using 0.1 μm In02Al08Sb-InAs HEMTs on 3-inch GaAs substrates. This accomplishment is crucial for phased-array applications with ultralow-power and oxidation-free requirements.

This paper reports the CSG/CDG capacitance behavior of 100 nm fully-depleted (FD) SOI CMOS devices with HfO2 high-k gate dielectric considering gate tunneling leakage current. According to the 2D simulation results, a unique two-step CSG/CDG versus VG curve exists for the device with the 1.5 nm HfO2 gate dielectric due to the vertical displacement effect. Gate tunneling leakage current has a more impact on CDG as compared to CSG

This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations

FUSI metal gate with strained engineering is extensively investigated and reported for the first time. Enveloped FUSI (fully silicided) phase transfer and volume change induced stress exhibits 10% NMOS ION enhancement. Further, the second CESL (contact etch stop layer) induced stress raised another 8% NMOS ION gain. Although the first CESL on poly-gate top removed by FUSI CMP leads to 10% PMOS ION degradation, it can be recovered or further improved by a dual CESL process

The carbon nanotubes (CNTs) were reinforced with poly(ethylene terephthalate) (PET) matrix resins to improve the electrical, thermal and mechanical properties of CNTs/PET composites in different contents of 0.25, 0.5, 0.75, 1.0, 1.25, 1.5 wt%. The powder material of PET and CNTs were first blended and then hot-pressed to form film specimen. The organizations and microstructures of the composites were studied with scanning electron microscope (SEM), the Atomic Force Microscope (AFM). The electrical resistivity of the composites was measured and was found to reduce rapidly when the contents of CNTs increase from 0 to 0.75%. The rate of reduction decreases as the contents of CNTs is greater than 0.75%. Temperature effect on the resistivity experiments indicates that the resistivity of the composites is not governed by CNTs, but the polymer materials between neighboring MWCNTs.

A porous k=2.5 low-k material (LK2.5) with its pore size distribution and mechanical properties comparable to the ones of k=3.0 low-k materials (LK3.0) was developed by a novel quasi-porogen approach for 65 nm BEOL Cu dual damascene (DD) interconnects. As compared to the Cu/LK3.0 DD, the Cu/LK2.5 DD, processed using similar etching and ashing processes and chemistries, showed a 14% line-to-line (L-L) capacitance reduction at S=0.1 /spl mu/m. Other physical, electrical and reliability results show that the Cu/LK2.5 DD is comparable to the Cu/LK3.0 DD with no degradations commonly associated with conventional porous LK2.5s formed using porogens, such as peeling or LK recess in CMP, k increase or trench bottom roughening in patterning, high L-L leakage, low L-L Vbd or low SM resistance. Further process extendibility studies revealed that k

Successful integration of high performance Cu dual damascene interconnects (DDIs) using a low-k etch stop (LES, oxygen-doped carbide, k/spl sim/3.0) and a porous low-k IMD (OSG, k/spl sim/2.5) has been demonstrated for the first time. The Cu DDIs with the LES not only revealed excellent resistance to stress induced voiding (SIV) but also exhibited 21% better interconnect RC delay, 100% higher via-EM endurance, 100 times lower line-line leakage at 125/spl deg/C, and 5% faster device operation speed as compared to the DDIs with a currently used etch stop (CES, oxygen-doped carbide, k/spl sim/4.5).

A novel PECVD porous low-k material with k=2.5, LK(k=2.5), has been successfully integrated with Cu for 90 nm generation BEOL interconnect technology on 300 mm wafers. Fundamental film studies showed that this low-k material is thermally stable up to 400/spl deg/C and can be strongly adhered to various dielectric films. Electrical measurement results from the Cu/LK(k=2.5) damascene interconnect showed tight and 100%-yielded distributions in 0.12/0.12 /spl mu/m interline leakage, one million 0.13 /spl mu/m viachain via Rc and 0.12 /spl mu/m Cu line Rs. To maximize the Cu/LK(k=2.5) interconnect capacitance performance, no middle etch stop layer and no top CMP cap were used in the dielectric film stacking. The final k value of the LK(k=2.5) after integration was retained at 2.5 using an optimized PR ashing chemistry by comparing the Cu/LK(2.5) 0.12/0.12 /spl mu/m interline capacitance to a Cu/LK(3.0) one. The intrinsic BEOL time dependent dielectric breakdown (TDDB) lifetime, T/sub 63,/ of the Cu/LK(k=2.5) is predicted to be 4.56/spl times/10/sup 8/ yrs at 0.3 MV/cm and 125/spl deg/C. Further reliability evaluations of the Cu/LK(k=2.5) in electromigration (EM) and stress migration (SM) showed that its predicted T/sub 0.1/ EM lifetimes for 0.12 /spl mu/m Cu line or 0.13 /spl mu/m via at 1 MA/cm2 and 110/spl deg/C are 152k hrs or 144k hrs, and its SM failure rate (>10% shift in Rc) is zero after 500hr annealing at 175/spl deg/C. Finally, the packaging feasibility of this Cu/LK(k=2.5) damascene interconnect was also demonstrated using current wire bonding technologies.

Two different TDDB behaviors have been for the first time observed in our work with different dual gate oxide thicknesses. (1st) The different transient scheme during TDDB stress for thin and thick oxide thickness, and (2nd) The different neutral trap generation rate during oxide degradation procedure for n and p type capacitors and different neutral trap distribution post oxide stress for thin and thick oxides. A variety of physical and electrical methodologies are presented in this paper to investigate the role of boron on 0.17 /spl mu/m dual gate and dual oxide technologies.

An all-fiber WDM channel monitor based on narrowband AOTF and on-fiber detector is demonstrated. By employing FSK modulation scheme, intrinsic wavelength accuracy of 0.02 nm is obtained for single channel detection and 0.05 nm for multiple channel detection.

A pressure-induced microbending long-period grating is used to determine the birefringence axes of a PM fiber. From the change of polarization-sensitive transmission spectrum versus rotational angle of the fiber, the birefringence axes can be accurately identified.

Heart rate variability is due to the interaction of sympathetic and parasympathetic nervous system. The spectral analysis of HRV provides a noninvasive probe to assess the function of the autonomic nervous system. The recording of physiological signals on free-moving subjects provides a useful tool to evaluate the autonomic states in the daily activities, but the information of activities is lack in the conventional ECG Holter, so it is difficult to estimate HRV in different activities. In this paper, we developed a microcontroller-based system for ECG and physical-activity recording system. The acceleration signals located at chest and thigh is used to classify the basic activities, including lying (supine, left lateral, right lateral, and prone), sitting, standing, and dynamic activity. Time-frequency analysis is used to compute the time-varying spectra of heart rate variability. In the 24-hour recording, the high-frequency fluctuations are the largest and the second in the sitting, which means major dominance of parasympathetic tone. As the posture is changing form sitting to standing and dynamic activity, the low-frequency power to high-frequency power ratio increases which demonstrates the increase of sympathetic tone and decrease of parasympathetic tone.

In anti-Gray codes, binary indexes are assigned to code vectors in a way that maximizes the average quantization distortion introduced in the reproduced source vectors when a transmitted index is corrupted by channel noise. In this paper, anti-Gray coding is used for VQ encoded images. Since the average distortion at the receiver is maximized by the anti-Gray coding technique, errors can be easily detected. To detect channel errors, we first classify an image into uniform and edge regions. Then we propose a mask to detect channel errors based on the image classification (uniform and edge regions) and anti-Gray code characteristics. We also mathematically derive criteria for error detection based on image classification. Once error indexes are detected, the recovered indexes can be easily chosen from a candidate set by minimizing the gray-level transition across the block boundaries in a VQ encoded image. Simulation results show that the proposed technique provides the detection results with less than 0.1% probability of error and more than 86.3% probability of detection at random bit error rate 0.1%. For those undetected errors, they appear invisible. In addition, the proposed approach provides a better PSNR performance than other similar techniques and pseudo-Gray codes for images under noisy channels.

We present an optically pumped long wavelength vertical cavity surface emitting laser using an InGaAs/InGaAsP strain-compensated multiple quantum well gain medium fabricated an a GaAs substrate. The device relies on an 800 /spl Aring/-thick intermediate spin-on glass layer to join the high-gain InP-based gain medium with highly reflective GaAs-based AlAs/GaAs Bragg reflectors. At room temperature, the device operates at 1.44 /spl mu/m and has a low threshold pump power of 4.2 KW/cm/sup 2/.

Multiple quantum well (MQW) lasers have exhibited improved performance over conventional double heterostructure (DH) lasers for low threshold, high frequency, and high power applications. Ideally, the modulation bandwidth should increase with the number of wells due to the enhancement of differential gain. However, in reality, the maximum number of wells that can work effectively is governed by carrier transport. Because of the lower mobility of holes, those wells far away from the hole injection side (p-electrode) receive less carriers and have a smaller gain; and those wells close to the p-electrode receive more carriers and have a higher gain. The excess carriers in the wells near the p-electrode tend to reduce the differential gain, thus degrade the high frequency characteristics. A carrier diffusion model is used to theoretically analyze the effect of nonuniform pumping in a 1.55 /spl mu/m InGaAs/InGaAsP MQW (20 wells) laser. A substantial nonuniformity in gain distribution among the wells limits the ultimate modulation bandwidth. Possible schemes of overcoming the transport-limited nonuniform pumping such as using p-doping are discussed.

A high-performance BiCMOS data separator IC has been created with a 1.5 GHz NPN FT, 2 mu m EXAR modular CMOS process. Equivalent performance to bipolar implementations have been achieved at one half of the die size and nearly one quarter of the power. A versatile N2000 EXAR process and cell library was used for this design. The process features a well-characterized cell library containing nearly all required cells. Minimal cell design or adaption was necessary. The addition of two mask layers for buried layer and p base allows the inclusion of both an npn transistor and a lateral pnp device. There are 16 mask steps used. The process has two levels of metal and dual poly for interconnection. >

For high-capacity wavelength division multiplexing (WDM) optical communication systems, distributed feedback (DFB) laser arrays having a nanometer wavelength spacing are highly desirable. Most of the WDM laser arrays fabricated today used E-beam lithography to achieve accurate control of the channel spacing. However, E-beam lithography is not suitable for high volume production because of its low throughput and high cost. Recently, we developed a new fabricating process, cascaded self-induced holography, to form submicron gratings. This process is simple, reliable, and insensitive to vibrations and environmental changes. In this paper, we use cascaded self-induced holography to demonstrate multiple grating pitches having a period difference of a few angstroms between adjacent devices. This technique is particularly attractive for WDM laser arrays.

The partially depleted SOI MOSFET (PD-SOI) has been found to be an attractive device due to advantages such as full dielectric isolation and reduced junction capacitance compared to the bulk Si device (Assaderaghi et al, 1997; Maeda et al, 2000). However, the floating body effect occurs on PD-SOI devices, resulting in threshold voltage reduction and noise overshoot (Tseng et al, 1997). Body contact structures have been proposed to improve the floating body effect (Huang et al, 1998). This paper describes high performance 0.1 /spl mu/m generation SOI MOSFET technology with body contact structure (BC-SOI) which was used to investigate the device characteristics as well as thermal effects in comparison with the floating body SOI MOSFET (FB-SOI), which is without body contact. The dynamic-threshold voltage SOI MOSFET (DTMOS) was also investigated.