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For the first time, a sub-100 nm gate length CMOS transistor is demonstrated with the source/drain extension implemented by laser thermal process (LTP). Ultra-shallow (

This paper reports on characterization and numerical modelling of dual-collector magnetotransistors with suppressed sidewall injection (SSIMT) fabricated in silicon on insulator (SOI) technology. This process allows to eliminate, by design, the undesirable high substrate current usually present in conventional bipolar or CMOS fabricated SSIMT's. Two-dimensional simulations reveal that the device operates like a PIN diode rather than as a true transistor, as expected. The presence of an electron-hole plasma in the active device region inhibits a proper transistor behavior. The magnetic performance of the SSIMT is improved by reducing the minority carrier lifetime and by redefining the doping profiles of the process. >

We studied the operation of multi-collector bipolar transistors with directional magnetic field sensitivity. The complex three-dimensional (3D) device consists of four crosswise-arranged lateral transistors with one common central emitter. To analyze the electrical characteristics and sensor performance, we modeled the complete device structure using technological and physical parameters, extracted from experimental measurements on real devices. Because of the complex geometry, a full 3D numerical analysis of carrier flow and electrostatic potential is required in order to study the effects of an arbitrarily oriented magnetic field. Full 3D analysis is essential also in devices whose contact areas differ widely. In this case, a simplified analysis confined on the 2D central mirror plane is inadequate even for the mere electric device behavior at zero magnetic field. This reflects the problem of current calibration inherent in 2D approximations of devices with truly 3D structures. To overcome this discrepancy, we implemented, for the first time, the 3D galvanomagnetic transport vector equations in a state-of-the-art general purpose device simulator. >

The semiconductor industry is not motivated to make practical use of cryogenic operation as long as IC performance could be improved at room temperature. However, as CMOS approaches the scaling limits, cooled chip operation becomes an attractive alternative. This paper explores the feasibility of IC temperature "scaling" and its implications to device performance and reliability for sub-50 nm CMOS generations.

3D simulations have been performed to study the impact of self-heating in SOI on circuits. Using multiple finger structures we have established bounds on the magnitude of the heat increase and its behavior with device scaling. This allows circuit designers to quickly evaluate temperature variations in real circuits under various operating conditions. for various device sizes and subject to different current density thanks to simple scaling of the presented results. The approach gives a simple and efficient way to take into account self heating in circuit optimization. In addition. contrary to previous studies, we have found that the heat predominantly flows through the buried oxide.

This paper explores the ultimate scaling limit of gate oxide due to MOSFET gate leakage and device performance. The limit on Tox reduction with respect to gate leakage tolerance is considered by the concept of "dynamic" gate leakage in nano-scale MOSFET's. Tox scaling is also limited by transistor performance degradation due to the loss of inversion layer charge through gate leakage and the degradation of carrier mobility in the channel from increased scattering. All the three effects are investigated experimentally on CMOS devices with gate length down to 50 nm and gate Tox down to 12 A. The minimum Tox is proposed and the implications on voltage scaling, high-k gate dielectrics and low-temperature CMOS are discussed.