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In-memory computing based on memristive logic is considered as a prospective non von Neumann computing paradigm. In this letter, we systematically analyze the four-variable logic method and map it into the operation of two anti-serial complementary memristors in the crossbar array architecture. Arbitrary Boolean logic can be implemented within three cycles with the experimental evidence of reconfigurable NAND, NOR, and XOR logic using Pt/HfO2/TiN devices. Taking advantage of the functional flexibility, a parallel 1-bit full adder that can be realized in 8 cycles within a $\textsf {4}\times \textsf {3}$ array has been designed and verified in simulation. [ABSTRACT FROM AUTHOR]

In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 107 cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture. [ABSTRACT FROM AUTHOR]

Machine learning (ML) models and algorithms can enable a personalized learning experience for students in an inexpensive and scalable manner. At the heart of ML-driven personalized learning is the automated analysis of student responses to assessment items. Existing statistical models for this task enable the estimation of student knowledge and question difficulty solely from graded response data with only minimal effort from instructors. However, most existing student–response models are generalized linear models, meaning that they characterize the probability that a student answers a question correctly through a linear combination of their knowledge and the question's difficulty with respect to each concept that is being assessed. Such models cannot characterize complicated, nonlinear student–response associations and, hence, lack human interpretability in practice. In this paper, we propose a nonlinear student–response model called Boolean logic analysis (BLAh) that models a student's binary-valued graded response to a question as the output of a Boolean logic function. We develop a Markov chain Monte Carlo inference algorithm that learns the Boolean logic functions for each question solely from graded response data. A refined BLAh model improves the identifiability, tractability, and interpretability by considering a restricted set of ordered Boolean logic functions. Experimental results on a variety of real-world educational datasets demonstrate that BLAh not only achieves best-in-class prediction performance on unobserved student responses on some datasets but also provides easily interpretable parameters when questions are tagged with metadata by domain experts, which can provide useful feedback to instructors and content designers to improve the quality of assessment items. [ABSTRACT FROM PUBLISHER]

Today’s computer architectures suffer from many challenges, such as the near end of CMOS downscaling, the memory/communication bottleneck, the power wall, and the programming complexity. As a consequence, these architectures become inefficient in solving big data problems or general data intensive applications. Computation-in-memory (CIM) is a novel architecture that tries to solve/alleviate the impact of these challenges using the same device (i.e., the memristor) to implement the processor and memory in the same physical crossbar. In order to analyze its feasibility in depth, this paper proposes two memristor implementations of a data intensive arithmetic application (i.e., parallel addition). To the best of our knowledge, this is the first paper that considers the cost of the entire architecture including both crossbar and its CMOS controller. The results show that CIM architecture in general and the CIM parallel adder in particular have a high scalability. CIM parallel adder achieves at least two orders of magnitude improvement in energy and area in comparison with a multicore-based parallel adder. Moreover, due to a wide variety of memristor design methods (such as Boolean logic), tradeoffs can be made between the area, delay, and energy consumption. [ABSTRACT FROM PUBLISHER]

Moore's law relies on device size reduction for progress, but an energy tax due to Boolean logic properties could block this progress. There are alternatives. [ABSTRACT FROM AUTHOR]

As CMOS technology begins to face significant scaling challenges, considerable research efforts are being directed to investigate alternative device technologies that can serve as a replacement for CMOS. Spintronic devices, which utilize the spin of electrons as the state variable for computation, have recently emerged as one of the leading candidates for post-CMOS technology. Recent experiments have shown that a nano-magnet can be switched by a spin-polarized current and this has led to a number of novel device proposals over the past few years. In this paper, we provide a review of different mechanisms that manipulate the state of a nano-magnet using current-induced spin-transfer torque and demonstrate how such mechanisms have been engineered to develop device structures for energy-efficient on-chip memory and logic. [ABSTRACT FROM PUBLISHER]

Recently, a systematic procedure was proposed to derive a minimum input quantum circuit for any given classical logic with the generalized quantum Toffoli gate, which is universal in Boolean logic. Since quantum Boolean circuits are reversible, we can apply this property to build quantum iterative logic array (QILA). QILA can be easily tested in constant time (C-testable) if stuck-at fault model is assumed. In this paper, we use Hadamard and general controlled-controlled not gates to make QILA 1-testable. That is, for any quantum Boolean circuit, the number of test patterns is independent of both the size of the array and the length of the inputs. [ABSTRACT FROM PUBLISHER]

As manufacturing technology reaches nanoscale, architectural designs need to accommodate the uncertainty inherent at such scales. These uncertainties are germane in the minuscule dimension of the devices, quantum physical effects, reduced noise margins, system energy levels reaching computing thermal limits, manufacturing defects, aging, and many other factors. Defect-tolerant architectures and their reliability measures will gain importance for logic and micro-architecture designs based on nanoscale substrates. Recently, the Markov random field has been proposed as a model of computation for nanoscale logic gates. This opens up new possibilities in designing logic and architecture where the conventional Boolean logic is replaced by a notion of an energy distribution function based on Gibbs distribution. In this computational scheme, probabilities of energy levels at various gate inputs and interconnects are considered, and belief propagation is used to propagate these probability distributions from the primary inputs to the primary outputs of a Boolean network. In this paper, we take this approach further by automating this computational scheme and belief propagation algorithm. We have developed MATLAB-based libraries for fundamental logic gates that can compute probability distributions and entropies at the outputs for specified discrete input distributions and in the presence of noise at the inputs and interconnects. Our tool automates the evaluation of reliability measures of combinational logic blocks. The effectiveness of this automation is illustrated in this paper by automatically deriving various reliability results for defect-tolerant architectures, such as triple modular redundancy (TMR), cascaded TMR, and multistage iterations of these. Also, signal noise is modeled as uniform and Gaussian distributions at the inputs and interconnects, so as to evaluate reliability-redundancy tradeoffs of these architectural configurations taking into account such noise models. [ABSTRACT FROM PUBLISHER]

We propose a two-input configuration of a magnetic tunnel junction (MTJ) for use as a programmable logic element. The MTJ intrinsically performs four logic functions—NAND, NOR, IMP, and NIMP—based on two physically independent inputs whose values are determined by magnetic field and the voltage bias. By applying the surface magnetoelectric effect, four distinct input states are determined to perform these logic operations through switching of the MTJ. With predetermined logic inputs, a single MTJ can serve as a programmable logic gate that represents all fundamental logic functions. [ABSTRACT FROM AUTHOR]

In this letter, the performance evaluation of rate-adaptive transmission schemes for indoor unguided optical links has been analyzed in the context of runlength-limited (RLL) sequences. Here, the superiority of on-off keying (OOK) formats with runlength constraints based on silence periods has been corroborated in terms of code efficiency and peak-to-average optical power ratio (PAOPR) compared to a hybrid HHH (1,13) code, variable-rate signalling technique obtained by modifying the RLL (1,13) code specified in the very fast infrared (VFIr) standard by the infrared data association (IrDA). Additionally, the use of very simple decoding schemes based on Boolean logic has been proposed. [ABSTRACT FROM PUBLISHER]

The novel design of an all-optical XOR gate by using cross-gain modulation of semiconductor optical amplifiers has been suggested and demonstrated successfully at 10 Gb/s. Boolean AB~ and A~B of the two input signals A and B have been obtained and combined to achieve the all-optical XOR gate. No additional input beam such as a clock signal or continuous wave light is used in this new design, which is required in other all-optical XOR gates. [ABSTRACT FROM PUBLISHER]

The Boolean logic is a tool to model the algebra of truth values. It is an essential subject in Computer Programming and Digital Electronics. While teaching the Boolean logic, teacher usually gives examples to elaborate the Boolean logic formulation. However, the physical meaning of the Boolean logic is difficult for students to imagine without the realization to real-world case. The classical Pac-Man game which has clear Boolean logic game rules and simple game scenario is chosen as the teaching aid. Accordingly, two learning activities, the Boolean logic realization activity and game scenario formulation activity, are proposed. Our idea is that through game rule tuning in the learning activities, the students can comprehend how the changing of game rule (Boolean logic) affects the game scenario. To manipulate the game scenario for teaching specific learning objectives of Boolean logic, the Game Rule of the original Pac-Man game is defined and seven versions of modified game scenarios provided as illustrations are appropriately organized for students to practice one Boolean logic concept each time. The experimental results showed the proposed activity can have higher learning achievements compared to the traditional lecturing. [ABSTRACT FROM PUBLISHER]