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This paper introduces a novel control strategy for multifunctional grid-tied inverters in industrial/commercial power systems, aiming to address the compensation of instantaneous power oscillations. The proposed strategy is derived from the Conservative Power Theory, which offers the ability to extract and analyze oscillating power terms directly in the abc frame. To demonstrate the efficacy of the proposed strategy, simulation results are presented, considering a scenario with a three-phase multi-functional grid-tied inverter with an LCL filter operating in a laboratory scale prototype. The power system includes various types of loads, such as linear, non-linear, unbalanced loads and a three-phase induction motor with capacitive compensation. Simulation results show the effectiveness of the proposed strategy in coping with the active power dispatch provided by the inverter, concomitantly ensuring that the induction motor operates with constant torque, as well as that the industrial/commercial electric system operates with improved power quality. Furthermore, the proposed strategy is also validated by means of experimental results obtained from a 3.6 kVA inverter prototype. The experimental findings affirm that the compensation of the targeted oscillating power terms is successfully achieved. Such a validation underscores the practical viability of applying the proposed strategy to real-world scenarios.

This work proposes a novel secondary control system based on the Consensus algorithm to balance the RMS current between the distributed generation (DG) phases in an isolated four-wire Microgrid (MG) containing unbalanced and non-linear loads. The control strategy proposes using a droop control per phase to regulate the voltage magnitude, whereas the harmonic current sharing is performed using the virtual impedance concept. Additionally, the proposed control scheme guarantees voltage regulation, causing the MG to operate at its nominal voltage value. In addition to sharing the RMS value of the current, the consensus algorithm also provides the equal sharing of the RMS value of the harmonic current between each phase of the DGs that comprise the MG and also ensures that the harmonic distortion of the voltage in the PCC of each DG remains within limits defined by the standards and recommendations. Simulation results demonstrate the functioning and effectiveness of the proposed control strategy.

This paper explores the application of multifunctional inverters connected to the electrical network, to propose an adaptable system to individually control reactive power, load imbalance, and harmonic currents. Based on Conservative Power Theory (CPT), the dynamic compensation of Power Quality (PQ) indices is carried out under different conditions of demand and energy generation. First, a set of global factors for reactive power, imbalances, and current harmonics is introduced, which are effective even for bidirectional power flows in systems with harmonic voltage distortion and/or voltage unbalance. This set of factors gives rise to a multiobjective decision-making algorithm to estimate coefficients of proportionality, which instantly considers the reference signals linked to the disturbances, enabling to individually keep track of the target values of each of the PQ indices, as customarily established through standards or electricity utility criteria. As a result, this proposed approach allows a multiobjective operation of the inverter connected to the network, thereby allowing maximum use of energy generated, as well as limiting energy losses of distribution networks, and enhancement of the PQ of a prosumer. Finally, to illustrate the effectiveness of the proposed approach, different case studies were simulated with this set of case studies, including one representative real case containing a PV system connected to the network and a non-linear unbalanced load with variable demand.

Active and reactive power regulation, unbalanced current compensation, and harmonic current mitigation are the most significant functionalities typically embedded to a three-phase multifunctional grid-connected inverter. However, a vital control feature minimally addressed in the literature is the capability to adjust the grid power factor to the minimum value required by standards or grid codes. Hence, this paper presents an adaptive compensation approach to perform dynamic power factor regulation under varying power demand and unpredictable energy generation, also withstanding non-ideal voltage conditions. To demonstrate such an approach, a global power factor definition is first introduced, being validated upon bidirectional power flow conditions and under unbalanced and distorted voltages. Secondly, a simple algorithm is devised to attain scaling coefficients used on compensation purposes, allowing to instantaneously weigh up reference control signals to track a desired grid-side power factor value. As a result, the strategy can be used to retrofit the controllers of grid-connected inverters with little effort, limiting distribution losses and improving power quality. Simulations and analyses of a representative real study case are conducted to illustrate how the proposed approach copes with unpredictable distributed energy resources and variable load demands. Moreover, experimental results considering a grid-connected inverter prototype are shown to validate the feasibility of the control approach to real-life implementations.

An improved distributed control strategy for imbalance and harmonic sharing in 4-leg droop controlled power converters for 3-phase 4-wire isolated Microgrids is presented in this letter. The proposed control scheme improves a previous one proposed by some of the authors of this letter in the sense that both negative and zero current sequence components are independently controlled. A numerical comparison between the previous method [1] and the presented in this letter shows that, for the studied case, the negative sequence powers shared among the 4-leg converters using the method [1] are: 1638 VA, 2309 VA, 1760 VA, 2610 VA and 1344 VA (these powers are unequally shared). In contrast, with the improved method, all of these powers are equally shared at 1945VA, showing the effectiveness of the proposal. Similar behaviour was verified for zero-sequence powers, which, for the method [1], varied from 1588 VA to 2547 VA, while the proposed approach produced equal sharing of zero-sequence powers (2072 VA) among all the converters. [ABSTRACT FROM AUTHOR]

This article investigates the device variability induced by the total ionizing dose (TID) effects in a commercial 16-nm bulk nFinFETs, using specially designed test structures and measurement procedures aimed at maximizing the matching between devices. DC static characteristic measurements show that below 100 Mrad(SiO2) the device variability is slightly affected by the total accumulated dose. However, when the total dose reaches 100 Mrad(SiO2), the device variability increases significantly showing a correlation with pre-irradiation electrical responses of the devices. Transistors characterized by higher drain current exhibit the worst TID degradation. This phenomenon is likely due to the impact of random dopant fluctuations on the TID effects and/or to variations in the hydrogen concentration responsible for the TID-induced interface traps. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions. [ABSTRACT FROM AUTHOR]

This article investigates the fin- and finger-number dependence of the total ionizing dose (TID) degradation in 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs designed with different numbers of fins and fingers are irradiated up to 500 Mrad(SiO2) and then annealed for 24 h at 100 °C. The TID responses of nFinFETs are insensitive to the fin number, as dominated by border and interface trap generation in shallow trench isolation (STI) and/or gate oxide. However, pFinFETs show a visible fin-number dependence with worst tolerance of transistors with the smallest number of fins. The fin number dependence may be related to a larger charge trapping in STI located at the opposite lateral sides of the first and last fins. In addition, both n- and p-FinFETs exhibit an almost TID insensitivity to the finger number. During the design of integrated circuits, the TID tolerance of electronic systems can be enhanced by preferably using transistors with a higher number of fins than fingers. [ABSTRACT FROM AUTHOR]

Discussions on the different methods for sharing responsibilities regarding harmonic distortions in power grids have received wide attention in the area of power quality. This paper proposes a methodology based on Conservative Power Theory (CPT) for responsibility assignment due to the harmonic voltage distortions present at the point of common coupling. First, a theoretical basis for analyzing the orthogonal current decomposition of CPT under non-sinusoidal conditions is presented. Next, using the frequency domain, a methodology is introduced to separate the contributions of the harmonic voltage distortions in the CPT's orthogonal currents. To illustrate the application of the proposed methodology, it is simulated a real large-scale electrical system composed of an energy utility and three industrial plants connected to the same common coupling point. Finally, the results obtained are compared to other method showing the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

This article investigates the total ionizing dose (TID) degradation mechanisms of 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs with several channel lengths are irradiated up to 1 Grad(SiO2) and then annealed for 24 h at 100 °C. Irradiated devices show significant degradation in transconductance and OFF-state leakage currents with slight subthreshold stretch-out and negligible threshold voltage shifts. At doses up to 10 Mrad(SiO2), the TID response is dominated by positive trapped charges in the shallow trench isolation (STI). At ultrahigh doses approaching 1 Grad(SiO2), dc static measurements suggest generation of trapped charge at the STI/Si interface and/or at the corner between the STI and the gate dielectric. The TID sensitivity depends on the bias condition and channel length. Halo implantations fortuitously increase the radiation tolerance of short-channel FinFETs due to the increased channel doping caused by the overlap of the source and the drain halos. The worst degradation is found when a high electric field is applied to the gate during irradiation. [ABSTRACT FROM AUTHOR]

Gate-all-around (GAA) silicon nanowire (NW) CMOS transistors demonstrate outstanding total-ionizing-dose (TID) tolerance due to the ultrascaled gate dielectric thickness, enhanced electrostatic gate control, and suppression of parasitic leakage current paths. nFETs and pFETs show similar TID responses, making the GAA NW technology an excellent candidate for CMOS IC applications in high-radiation environments. The slight degradation of the threshold voltage suggests limited charge buildup in the gate dielectrics. However, low-frequency noise and random telegraph noise measurements show the importance of change in trap configurations in both the near-interfacial SiO2 and HfO2 dielectric layers to the radiation response and reliability of GAA NW devices. These traps are most likely due to oxygen vacancies and/or hydrogen complexes. [ABSTRACT FROM AUTHOR]

The increasing penetration of renewable energy sources is pushing low-voltage electrical grids to become predominantly power electronic-based. Consequently, the design and operation of the related grid-connected converters must be achieved under proper manner, in order to maintain stability and support reliable operation of the entire power system. Thus, this work presents the modeling and control of a single-phase grid-connected multifunctional converter, which operates as a current-controlled voltage source inverter using an LCL-type output filter. An active damping approach is employed for attenuation of oscillations occurring from interactions between the grid and the inductances and capacitance of the LCL filter. Additionally, the voltage and current control loops of the inverter are addressed in this paper, along with the design of their respective controllers, considering that the grid impedance is unknown. Experimental results demonstrate stable operation of the inverter and show its satisfactory behavior under steady state conditions, proving its capability to offer ancillary services such as active filtering. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) mechanisms are investigated in 28-nm MOSFETs via dc static and low-frequency noise measurements. nMOSFETs and pMOSFETs are irradiated up to 1 Grad(SiO2) and annealed at high temperatures. TID sensitivity depends on the channel length, the channel width, and the bias condition. Halo implantations improve the radiation tolerance of shorter-channel transistors. Worst case bias for TID-induced degradation is found with high electric field applied to the gate during irradiation, due to increased charge trapping in the upper corner of the shallow trench isolation (STI) and in the gate oxide. DC and low-frequency noise measurements show that, at doses up to ~100 Mrad(SiO2), radiation-induced degradation is primarily due to the positive charge buildup in the STI oxides. At ultrahigh doses approaching 1 Grad(SiO2), TID degradation is influenced by charge buildup in the gate oxide and traps at or near the gate/dielectric interface and/or along the STI sidewalls. Worst case degradation is found in narrower and longer-channel devices, due to the enhanced charge buildup in the STI oxide and along its interfaces. [ABSTRACT FROM AUTHOR]

The total-ionizing-dose (TID) response of indium gallium arsenide (InGaAs) MOSFETs with Al2O3 gate dielectrics and several channel lengths is evaluated under different biases. DC static characteristics show large negative threshold voltage Vth shifts and subthreshold stretchout (SS), indicating net positive charge trapping in the gate oxide and generation of the interface and border traps. Hysteresis and Id – Vgs measurements from cryogenic to high temperatures show the important role of defects in the Al2O3 gate dielectric to the TID response. Radiation-induced-hole trapping is attributed to oxygen vacancies in the Al2O3. The relatively large hysteresis in these devices is attributed primarily to dangling Al bonds in the near-interfacial Al2O3. Analysis of the temperature dependence of Vth and SS suggests that the rate at which electrons leave the Al2O3 during a positive-to-negative gate-bias sweep is higher than the rate at which they enter during a negative-to-positive gate-bias sweep. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose mechanisms are investigated in 16-nm InGaAs FinFETs with an HfO2/Al2O3 gate-stack. Transistors are irradiated up to 500 krad(SiO2) and annealed at high temperatures. Irradiated devices show negative threshold-voltage Vth shifts, subthreshold stretch-out, and leakage current increases. These result from positive charge trapping in the gate oxide and shallow trench insulators, and increases in the interface and border-trap charge densities. Low-frequency noise measurements at different temperatures indicate a significant increase of noise magnitude in irradiated devices at an activation energy of ~0.4 eV. Density functional theory (DFT) calculations strongly suggest that transistor Vth shifts are due primarily to hole trapping at oxygen vacancies in HfO2, and the increased noise is due primarily to O vacancies in Al2O3. Additional contributions to the noise from defects in the GaAs buffer layer are also likely, primarily at low temperatures. [ABSTRACT FROM AUTHOR]

We evaluate the total-ionizing-dose (TID) responses of InGaAs nMOS fin field-effect transistors (FinFETs) with a modified gate-stack irradiated with 10-keV X-rays under different gate biases. This modified InGaAs nMOS FinFET process shows decreased subthreshold leakage current and increased hysteresis in as-processed devices, and reduced hole trapping in irradiated devices, than first-generation development-stage devices. The reduction in subthreshold leakage current is attributed to changing the buffer layer from GaAs to In0.3Ga0.7As, thereby enhancing the material quality. Both the increased hysteresis in as-processed devices and reduced hole trapping in irradiated devices are attributed primarily to thinning the Al2O3 layer that separates the HfO2 from the InGaAs layers. This facilitates charge exchange with defects at the HfO2/Al2O3 interface and reduces the percentage of radiation-induced holes that are generated in Al2O3 and trapped in HfO2. The removal of a tungsten layer above the TiN gate reduces the interface dose enhancement. [ABSTRACT FROM AUTHOR]

In this paper, a commercial 65-nm CMOS technology is irradiated at ultrahigh ionizing doses and then annealed at high temperature under different bias conditions. The experimental results demonstrate the high sensitivity of pMOSFETs to radiation-induced short-channel effects, related to the buildup of defects in spacer dielectrics. We find that the charge buildup in the spacers is insensitive to the applied source-to-drain electric field, but the generation and/or annealing of interface traps strongly depends on applied drain bias and channel length. The static dc and charge-pumping measurements indicate a high density of interface traps in the lateral source/drain extension regions. The worst case bias condition corresponds to the application of a large drain–source voltage, due to the lateral electric field driving hydrogen from the spacers toward the source extension and the channel. The consequent differences in growth and annealing rates of interface traps lead to a large asymmetric degradation of the short-channel transistors. The technology computer-aided design simulations are used to qualitatively confirm the proposed degradation model. [ABSTRACT FROM AUTHOR]

We evaluate the total ionizing dose (TID) responses of InGaAs nMOS FinFETs with different gate lengths irradiated with 10-keV X-rays under different gate biases. The largest degradation after irradiation occurs at $V_{\mathrm {G}} = -1$ V. Radiation-induced trapped positive charge dominates the TID response of InGaAs FinFET transistors, consistent with previous results for InGaAs multifin capacitors. Shorter gate-length devices show larger radiation-induced charge trapping than longer gate-length devices, most likely due to the electrostatic effects of trapped charge in the surrounding SiO2 isolation and SiO2/Si3N4 spacer oxides. The 1/ $f$ noise measurements indicate a high trap density and a nonuniform defect-energy distribution, consistent with a strong variation of effective border-trap density with surface potential. [ABSTRACT FROM AUTHOR]

In this paper, the total ionizing dose (TID) response of a commercial 28-nm high-k CMOS technology at ultrahigh doses is measured and discussed. The degradation of pMOSFETs depends not only on the channel width but also on the channel length. Short-channel pMOSFETs exhibit a higher TID tolerance compared to long ones. We attributed this effect to the presence of the halo implantations. For short-channel lengths, the drain halo can overlap the source one, increasing the average bulk doping along the channel. The higher bulk doping attenuates the radiation-induced degradation, improving the TID tolerance of short-channel transistors. The results are finally compared and discussed through technology computer-aided design simulations. [ABSTRACT FROM AUTHOR]

The radiation response of complementary metal–oxide–semiconductor (CMOS) gate oxides is typically insensitive to true dose-rate effects, but damage in deep-sub-micrometer technologies is dominated by ionization mechanisms in thick isolation oxides surrounding the transistors. Recent results in 65-nm FETs demonstrated that performance degradation in ultrahigh total ionizing dose (TID) experiments is due to defects in the isolation shallow trench isolation oxide or in the materials composing the lightly doped drain spacers. These insulators are thick, deposited, and crossed by a low electric field, characteristics similar to those typical of passivation oxides in linear bipolar technologies for which an enhanced low-dose-rate sensitivity (ELDRS) has been observed and systematically studied. We report in this paper the clear evidence of a dose-rate sensitivity of the TID-induced damage in both 130- and 65-nm CMOS technologies exposed to different radiation sources (X-rays and $\gamma $ -rays from a 60Co source). This sensitivity is attributed to mechanisms similar to those explaining ELDRS in bipolar devices and represents a significant challenge to the definition of a qualification procedure for circuits to be used in extreme radiation environments. [ABSTRACT FROM AUTHOR]