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The role of charged, solid particulate matter (i.e., "dust"’ in plasmas has been considered for several decades. However, beginning with observations of structures in the dust tails of comets and the Voyager observations of radial structures ("spokes"’ in Saturn’s rings, the role of charged dust in the solar system led to the emergence of the field of "dusty" (alternatively, "complex"’ plasmas. Since the early 1990’s there has been a complementary effort in the area of laboratory dusty plasmas that has, over almost four decades, led to the observation of numerous types of plasma and dusty plasma behavior – ranging from appearance of strongly-coupled, self-organized dusty plasma crystals to new types of collective, dust-driven modes, such as the dust acoustic and dust density waves.

We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with IDSAT=1.4 mA/mum and 1.1 mA/mum respectively (IOFF=100nA/mum, VCC =1.1V and LG=40nm) with excellent short channel effects (SCE)-DIBL and subthreshold swing, DeltaS. The contributions of strain, the lang100rang vs. lang110rang substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade ION-IOFF and DeltaS

Several key emerging nanoelectronic devices, such as Si nanowire field-effect transistors (FETs), carbon nanotube FETs, and III-V compound semiconductor quantum-well FETs, are assessed for their potential in future high-performance, low-power computation applications. Furthermore, these devices are benchmarked against state-of-the-art Si CMOS technologies. The two fundamental transistor benchmarking metrics utilized in this study are: (i) CVII versus L/sub G/; and ii) CVII versus I/sub ON//I/sub OFF/. While intrinsic device speed is emphasized in the first metric, the tradeoff between device speed and off-state leakage is assessed in the latter. For high-performance and low-power logic applications, low CVII and high I/sub ON//I/sub OFF/ values are both required. Based on the results obtained, the opportunities and challenges for these emerging novel devices in future logic applications are highlighted and discussed.

Sustaining Moore's Law requires continual transistor miniaturization. Through silicon innovations and breakthroughs, CMOS transistor scaling and Moore's Law will continue at least through early next decade. By combining silicon innovations with other nanotechnologies on the same Si platform, it is expected that Moore's Law will extend well into the next decade. This paper describes the most recent advances made in silicon CMOS transistor technology and discusses the challenges and opportunities presented by the recent emerging nanoelectronic devices such as carbon nanotubefield-effect transistors (FET), Si-nanowire FETs and III-V FETs for high-performance, low-power logic applications.

Clock distribution on the microprocessor codenamed Montecito features four distinct segments and topologies each tuned to a specific purpose. A region based active de-skew (RAD) system reduces the process, voltage, and temperature sources of skew across the 21.5 /spl times/ 27.7mm/sup 2/ die during normal operation. Clock vernier devices (CVDs) inserted at each local clock buffer allows 70ps of adjustment via scan. The system supports a constantly varying frequency and consumes less than 25W on its 30mm route from PLL to latch.

Sustaining Moore's Law of scaling Si CMOS transistors requires not only shrinking the transistor dimensions, but also the introduction of new materials and structures. In the future, advanced high performance CMOS transistors are likely to incorporate highly strained Si and SiGe channels for enhanced carrier transport and high-k/metal-gate stacks for low gate leakage. This work describes the recent advances made in integrating strained Si and SiGe channel transistors with high-k/metal-gate stacks for future high performance, low power logic applications.

In this paper, the performance and energy delay trends for research devices down to 10 nm and also discusses the 10 nm barrier and potential ways to break it were explored.

The effects of the dicing and packaging of oxynitride-passivated CMOS devices are reported. It is shown that the dicing leads to extremely large threshold voltage shifts for both n- and p-MOS devices. The damage can mostly be annealed away at high temperatures, although the time and temperature are critical. Interface states and oxide charges are shown to be created and to follow different annealing kinetics. It is found that, even after full annealing, there is an increased hot-carrier susceptibility. No such effect is found for oxide and nitride passivations. Furthermore, the threshold voltage shift of a device is found to depend on its proximity to the point of dicing, indicating that mechanical stress is at the origin of this effect. >

The goal of the robotic soccer competition is to develop completely autonomous robotic agents that can cooperate to perform the desired tasks in an extremely dynamic environment. The approach is to train the robots, using various combinations of learning algorithms, i.e., the robots are to initially have no understanding of their environment. The robots are rewarded for positive contributions to the team, and in turn learn better performance through multiple sessions. The majority of learning will take place in simulation and then transferred to real physical mobile robots. The concept of tropism-based control architecture is introduced that not only allows for the evolution of cooperative strategies, but also obtains the acquired knowledge in a format that is easily comprehensible by humans. The results of many generations of simulated evolution are presented, accompanied by the game results and fitness characteristics.