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In the paper, pulse amplitude modulation (PAM) visible light communications link (VLC) which applies turbo equalizer to overcome is demonstrated. Significant performance gain compared to decision feedback equalizer is reported.

Basically, there are two main methods for estimation of tropospheric delays based on GNSS data. First, the relative technique, relying on creating double-differences (DD) of the observations and processing baselines connecting GNSS stations. The second method from undifferenced measurements is the Precise Point Positioning (PPP). These techniques differ in terms of processing complexity, handling of error sources and required geodetic products.In this research, GNSS-derived tropospheric parameters were computed for selected EUREF stations located in Poland and Europe using both approaches. For DD approach the Bernese v.5.2 software was applied, while the PPP solution was executed with the G-Nut/Tefnut software and with the Bernese v.5.2 software as well. The IGS final products were used. The resulting time series were compared in terms of quality and accuracy. In addition, both solutions were compared to the final EUREF solution. It was concluded that both approaches allow generation high-quality tropospheric delay estimates.

This paper demonstrates silicon-integrated, thinfilm, high-density tantalum capacitors for integrated power modules. The capacitors in form-factors of less than 75µm showed stable capacitance densities of more than 0.3 µF/mm2 with leakage of less than 0.1 µA/µF at 3 V. To the best of authors' knowledge, this is the highest capacitance density reported till date at the mentioned form-factors. Furthermore, these capacitors are integrated directly above the active silicon, enabling shorter interconnection path with lower system parasitics, leading to higher switching frequencies and lower losses. These ultra-miniaturized, substrate-compatible tantalum capacitors, thus, address the strategic need for highly-efficient, ultra-miniaturized power modules.

In this paper we present the comparison of signal acquired from samples containing particles of two different diameters. This work is continuation of our previous 1D imaging experiments conducted using the MPI scanner setup for small animals or samples developed by our group. Analyzes of those measurements should allow us to calculate the system function of the scanner as well as to evaluate the usability of the scanner as the magnetic particles spectrometer.

To enable the miniaturization, electrical performance and heterogeneous functionality needs for emerging Analog applications, a stacked Wafer-level Chip Scale Package (WCSP) package platform has been developed using Through-Silicon Via (TSV) technology. This allows stacking of ICs, MEMS, passives and other components in the vertical direction onto active or passive TSV wafers, to create innovative System-in-Package (SiP) product solutions. Since Analog devices are small in size and cost is a key care about, a careful selection of the integration flow is required to achieve a low cost packaging solution. In this work, an integration flow for the stacked WCSP package is presented, along with development details for the Chip-on-Wafer (CoW) bonding and wafer overmolding unit processes. The test vehicle was 3mm × 3mm in size and used 25u diameter Cu TSVs in a 200mm diameter wafer. Interconnect reliability evaluations were done with different micro-bump Under Bump Metallurgy (UBM) and TSV tip surface finish metallization combinations. Wafer ovemolding development included warpage, saw and adhesion evaluations with multiple mold materials. A back-end assembly flow was established with a mass reflow bonding process and an overmold material with low CTE and intermediate T g and modulus. Samples were prepared with mold-on-die and exposed die package structures. Excellent time-zero yields were obtained, with an average TSV micro-bump interconnect resistance of 25 mohms. Results and failures modes from preliminary reliability testing are included.

A single spatial phase filter that discriminates multiple channels at the output of mode division multiplexing system is shown. Excellently low crosstalk performance is reported for 4 × 4 and 8 × 8 systems.

We propose spatial light modulation with binary phase filters to increase the transmission bandwidth of multimode fibers. In the experiment more than 300 % of bandwidth enhancement is obtained.

The paper investigates the influence of the amplitude spatial filtering of the launched light beam on the base-band width of MM fiber frequency response. The filter is located on the confocal plane of an 4f imager. It is shown both theoretically and experimentally that a substantial increase of 3 dB base-band frequency is possible with only moderate filtration losses.

The need of a major urban utility to improve network reliability and feeder processing has generated the development of a series of switchgear devices. Size is an important issue since some applications are in existing 32-inch manhole structures and in vaults where space is limited. In addition environmental concerns were addressed with designs consisting of vacuum bottle switching with solid EPDM rubber insulation, eliminating the concern of leakage of greenhouse gases or liquid contaminants. This new switchgear reduces the time of feeder processing to restore repaired or changed networks to normal conditions, in some cases from days to hours. Three devices evolved to meet different requirements. The requirements included different combinations of loadbreak and/or loadmake with or without 40kA fault close capability and with or without SCADA control. This paper describes the function and application of these devices.

Frequency response of Multimode (MM) fibers beyond the baseband is studied both theoretically and experimentally. It is shown that in the absence of mode group mixing there are relative flat passbands suitable for transmission in such fibers if the number of mode groups propagating is not too large. Such conditions are usually met for typical contemporary graded index (GI) silica fibers. It is also proved that the passbands width is related to the baseband width. Moreover, the 1300 nm window is the most suitable for transmission due to small chromatic dispersion and reduced number of mode groups propagating.

Frequency response of Multimode (MM) fibers beyond the baseband is studied both theoretically and experimentally. It is shown that in the absence of mode group mixing there are relative flat passbands suitable for transmission in such fibers if the number of mode groups propagating is not too large. Such conditions are usually met for typical contemporary graded index (GI) silica fibers. It is also proved that the passbands width is related to the baseband width. Moreover, the 1300 nm window is the most suitable for transmission due to small chromatic dispersion and reduced number of mode groups propagating.

In this paper, operation of a cost-effective, two channel mode group diversity multiplexing system is demonstrated. The system works without use of single mode fiber components and with both step and graded index multimode fibers.

In this paper, operation of a cost-effective mode group diversity multiplexing system allowing 3 channel operation is demonstrated. Two different multiplexing/demultiplexing techniques are presented.

Employment of MM PON appears to be natural for short-range application such as intra-office or home networks. We have presented the results of the measurements of MM fiber PONs frequency responses in various configurations.

This paper describes the design and application of a three-phase device used to isolate a faulted spur from the main feeder. This allows restoration of service to the feeder. Visibly open contacts and provisions for grounding the faulted spur provides the operating conditions for repairing the fault. When the fault is repaired the device can be triggered to close spring-loaded contacts and reconnect the spur to the feeder without interruption of the feeder. The device is designed to operate on a 27 kV, 600 A system with a fault-close rating of 40 kA for 10 cycles

Wafer level packages (WLPs) have demonstrated a very clear size and cost advantage vs. traditional wirebond technologies, especially for small components that have a high number of dice and I/O per wafer. The Kulicke & Soffa Flip Chip Division (FCD) introduced it's first WLP in 1998. This initial WLP utilized a bump on nitride structure (BON) which had good reliability but also high input capacitance. A new WLP has been developed by FCD. This new WLP has a solder bump on polymer (BOP) dielectric structure. A major driver for pursuing a BOP structure was to achieve minimal input capacitance for high speed applications. During development, a new polymer dielectric material was carefully selected based on reliability tests and manufacturability. Thermal Cycling (TC) test showed 30% better TC performance vs. the BON structure. The new WLP also passed 168 hours of autoclave and JEDEC Level 1 Preconditioning testing. In this paper, the advantages of this new WLP will be discussed in detail. In addition, reliability test results will be presented.

The reliability of a ternary Sn/Ag/Cu alloy for flip chip solder joints will be reported in this paper. Dominant failure mechanisms for given thermal stress regimes are well defined for 63Sn/Pb eutectic solder. Characterizing Sn/Ag/Cu solder reliability in comparison to 63Sn/Pb solder provides a true baseline for these thermal stress regimes and still allows for a broad search of mechanisms due to the change in alloy properties inherent in this new metallurgic system. Reliability characterization must examine both solder bump and under bump metallization (UBM) robustness, because the interaction between the two contributes to the overall efficacy of the structure. Reported in this work are thermal cycle, high temperature storage, and die shear test results demonstrating the solder bump reliability. Electromigration, multiple reflow, and bare die high temperature test results verifying the UBM robustness are also presented. In addition, the assembly-related details are reported in an effort to provide a foundation for improved yield.

Wafer-applied underfill systems for flip-chip bonding have been developed to overcome throughput limitations imposed by capillary underfill systems. The wafer-applied underfill system consists of a highly filled film laminated to a bumped IC wafer and a liquid flux adhesive dispensed on the board. The wafer is diced after film lamination and the individual chips carry the underfill through the assembly process. The flux adhesive is dispensed at the bond site just prior to chip placement. These underfill materials undergo most or all of the required cure through a single reflow oven pass. A critical concern for a successful wafer-applied underfill bond is the prevention of discontinuities or voids in the underfill layer. Voids in the underfill can weaken the solder reinforcement otherwise provided by the underfill or permit the formation of between-bump shorts caused by solder extruding into the void. The wafer-applied underfill film laminating process presents one possible source for discontinuities. Since the film is laminated to a bumped wafer, the complete encasement around each solder bump by the wafer-applied underfill film is a necessity. A lamination process used to transfer the wafer-applied underfill film to the bumped wafer without such discontinuities will be described. This lamination process has been shown to provide uniform lamination over a full wafer with complete encasement of the solder bumps. Wafer-applied underfill and flux material characteristics and reliability results also will be reported.

Direct bump-on-copper technology provides a direct cost saving, equivalent bumping qualities, and better performance and reliability for products. The bump-on-copper FOC (flex-on-cap) technology is modified and derived from the existing high volume, reliable, proven bump-on-aluminum FOC process. A copper compatible adhesion layer, namely, titanium, combined with a NiV barrier layer and a Cu wetting layer for solder are used to construct the tri-metal stack that defines a reliable under bump metallurgy (UBM) for flip chip solder bumps. A proprietary solder deposition technique using solder paste is then applied to form the solder interconnects. Bump quality tests such as bump height and bump shear strength demonstrates an equivalent structure to the existing Al/NiV/Cu based flip chip bump. Wafers constructed as described are tested at both wafer level and in an assembled level. All perform well in the preliminary reliability evaluation including temperature cycle (TC), thermal shock (TS), autoclave test (PCT), high temperature storage (HTS), high temperature operational life (HTOL), and high accelerated stress test (HAST).

Flip chip wafer bumping using solder paste technology is currently in high volume production for minimum bump pitches in the range of 150 microns peripheral and 225 microns area array. This paper also covers the recent advances made in the bumping of wafers with 120 to 150 micron peripheral pitches as well as 200 micron pitch area array pitches. Information on flip chip bump cross sections, height uniformity and shear strength are also shown. Design rules for utilizing these fine pitch bump structures are shown, including both the bump design rules as well as the IC design rules. A principle advantages of the solder paste bumping technology is the ability to accurately control the solder alloy composition. This capability has been utilized to create a unique lead free solder alloy that is a quaternary alloy. This lead free alloy, which is currently in bump process development, has demonstrated a reliability increase of 50% over that of 63 Sn/Pb solder for flip chip applications. Lead free solders provide a potentially feasible path to meet ultra low alpha requirements as well as meeting the coming environmental restrictions on the use of lead. This Pb free alloy has a melting range of 190 to 200/spl deg/C. Flip chips bumped with this alloy were successfully assembled to laminate substrates with a peak reflow temperature of 230/spl deg/C.