Search

Your search keyword '"Nicolas Planes"' showing total 6 results
Start Over "Nicolas Planes" Topic optoelectronics Publisher hal ccsd
6 results on '"Nicolas Planes"'

1. Study of Hot-Carrier-Induced Traps in Nanoscale UTBB FD-SOI MOSFETs by Low-Frequency Noise Measurements

Author

Gerard Ghibaudo, X. Mescot, Nicolas Planes, T.A. Karatsori, Charalabos A. Dimitriadis, Sebastien Haendler, Christoforos G. Theodorou, Aristotle University of Thessaloniki, Department of Physics, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), ARISTEIA II, European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA)

Subjects
Materials science, Infrasound, Silicon on insulator, 02 engineering and technology, 01 natural sciences, 0103 physical sciences, MOSFET, Electrical and Electronic Engineering, Lorentzian noise, hot carriers (HCs), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, Noise measurement, business.industry, Subthreshold conduction, Flicker noise, Electrical engineering, Time constant, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, Amplitude, random telegraph noise (RTN), Optoelectronics, 0210 nano-technology, business, Noise (radio), fully depleted silicon-on-insulator (FD-SOI) MOSFETs
Abstract

International audience; The hot carrier (HC)-induced traps in nanoscale fully depleted ultrathin body and buried oxide nMOSFETs are investigated by low-frequency noise (LFN) measurements in the frequency and time domains. The measured noise spectra are composed of 1/f and Lorentzian-type components. The Lorentzian noise is due to either generation-recombination noise or random telegraph noise (RTN). Based on the LFN results, the effect of the HC stress on fully depleted silicon-on-insulator MOSFETs is investigated after short- and long-time stress. The capture and emission time constants responsible for the RTN noise were calculated as the average duration time of the high/low drain current state, respectively. Analysis of RTN traps detected in fresh and HC-stressed devices indicates that the RTN amplitude is uncorrelated to the trap time constants, i.e., the impact of the trap depth from the interface is masked by that of the trap location over the channel. The overall results lead to an analytical expression for the RTN amplitude, enabling to predict the RTN changes from the subthreshold to the above-threshold region.

Published
2016
Full Text
View/download PDF

2. Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Author

Nicolas Planes, Christoforos G. Theodorou, T.A. Karatsori, Charalabos A. Dimitriadis, A. Tsormpatzoglou, Sebastien Haendler, Gerard Ghibaudo, E. G. Ioannidis, Aristotle University of Thessaloniki, Department of Physics, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), ARISTEIA II project, and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA)

Subjects
Materials science, fully depleted silicon-on-insulator (FD-SOI) ultrathin-body and box (UTBB) MOSFETs, Channel length modulation, business.industry, Semiconductor device modeling, Silicon on insulator, Saturation velocity, Electronic, Optical and Magnetic Materials, Threshold voltage, Velocity overshoot, Logic gate, compact model, MOSFET, Electronic engineering, Optoelectronics, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Back-gate control
Abstract

International audience; An analytical drain-current compact model for lightly doped short-channel ultrathin-body and box fully depleted silicon-on-insulator MOSFETs with back-gate control is presented. The model includes the effects of drain-induced barrier lowering, channel-length modulation, saturation velocity, mobility degradation, quantum confinement, velocity overshoot, and self-heating. The proposed model has been validated by comparing with the experimental transfer and output characteristics of devices with the channel lengths of 30 and 240 nm and with back bias varying from -3 to +3 V. The good accuracy of the model makes it suitable for implementation in circuit simulation tools.

Published
2015
Full Text
View/download PDF

3. Hot carrier degradation mechanisms of short-channel FDSOI n-MOSFETs

Author

T.A. Karatsori, Sebastien Haendler, Christoforos G. Theodorou, C.A. Dimitriadis, Gerard Ghibaudo, Nicolas Planes, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Aristotle University of Thessaloniki, Department of Physics, STMicroelectronics [Crolles] (ST-CROLLES), and ARISTEIA II(Project 4154 of the GreekGeneral Secretariat for Research and Technology, co-funded by theEuropean Social Fund and national funds)

Subjects
Materials science, business.industry, 020208 electrical & electronic engineering, Gate dielectric, Electrical engineering, 020206 networking & telecommunications, 02 engineering and technology, Dielectric, [SPI.TRON]Engineering Sciences [physics]/Electronics, Stress (mechanics), Logic gate, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Degradation (geology), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, AND gate, Communication channel, Voltage
Abstract

session poster; International audience; The HC degradation of nanoscale FD-SOI n-MOSFETs has been investigated under the worst bias stress conditions (Vds,stress = Vgs,stress). At high stress voltages the hot carriers injected into the gate dielectric are the main degradation mechanism, superseding the interface degradation. The proposed degradation mechanisms are supported with the interface and gate dielectric trap properties extracted from LFN measurements.

Published
2015
Full Text
View/download PDF

4. Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

Author

Nicolas Planes, J. Pradelle, Pierre Perreau, P. Brun, Olivier Weber, Konstantin Bourdelle, Thierry Poiroux, Bich-Yen Nguyen, J. Ducote, Claire Fenouillet-Beranger, Remi Beneyton, R. Bianchini, B. Orlando, Francois Andrieu, A. Margain, L. Tosti, F. Abbate, C. Borowiak, C. Richard, D. Pellissier-Tanon, O. Faynot, C. Richier, T. Benoist, Magali Gregoire, Pascal Gouraud, Frederic Boeuf, Thomas Skotnicki, J. Bustos, Sebastien Haendler, E. Gourvest, Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Recherches sur les lois Fondamentales de l'Univers (IRFU), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Paris-Saclay, Unité Commune d'Expérimentation Animale, Institut National de la Recherche Agronomique (INRA), Silicon-on-Insulator Technologies (SOITEC), Parc Technologique des Fontaines, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA)

Subjects
Power management, Engineering, Materials science, Silicon on insulator, 02 engineering and technology, 01 natural sciences, law.invention, law, 0103 physical sciences, Materials Chemistry, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Metal gate, ComputingMilieux_MISCELLANEOUS, Ground plane, High-κ dielectric, 010302 applied physics, business.industry, Transistor, Electrical engineering, Biasing, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Threshold voltage, Modulation, Logic gate, Optoelectronics, 0210 nano-technology, business
Abstract

In this paper, we study how to boost the performance of FDSOI (Fully-Depleted Silicon On Insulator) devices with High-K and Single Metal gate by using the combination of Ultra-Thin Buried Oxide (UTBOX), Ground Plane (GP) and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of threshold voltage VT modulation and power management study on the 45 nm 0.374 μm2 bitcells and on the ESD functionality as compared to bulk technology.

Published
2013
Full Text
View/download PDF

5. Front-back gate coupling effect on 1/f noise in ultra-thin Si film FDSOI MOSFETs

Author

Francois Andrieu, Gerard Ghibaudo, Nicolas Planes, Olivier Faynot, Christoforos G. Theodorou, J. Jomaah, Charalabos A. Dimitriadis, Sebastien Haendler, E. G. Ioannidis, Franck Arnaud, Thierry Poiroux, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Aristotle University of Thessaloniki, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), HERACLEITUS IIco-financed by the European Union (European Social Fund – ESF) and Greeknational funds through the Operational Program ‘‘Education andLifelong Learning’’ of the National Strategic Reference Framework(NSRF), European Project: CT208,Catrene, and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Materials science, business.industry, Semiconductor device modeling, Silicon on insulator, Charge density, Biasing, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Noise (electronics), [SPI.TRON]Engineering Sciences [physics]/Electronics, CMOS, 0103 physical sciences, MOSFET, Optoelectronics, Flicker noise, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract

International audience; Low-frequency (LF) noise was studied on 28 nm CMOS technology FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). The noise level was observed to be strongly dependent on the combination of the front and back gate biasing voltages. This was explained by the coupling effect of both Si/High-K dielectric and Si/SiO 2 interface noise sources (channel/front oxide and channel/buried oxide), in combination with the variation of the Remote Coulomb scattering coefficient α. From comparison of the experimental and simulation results, it is illustrated that the main reason of this dependence is the distance between the charge distribution centroid and the interfaces, which is also controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient α. A new LF noise model approach is suggested to include the impact of all these parameters, and also allows us to extract the oxide trap density values for both interfaces.

Published
2012
Full Text
View/download PDF

6. Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

Author

Charalabos A. Dimitriadis, Christoforos G. Theodorou, Sebastien Haendler, Nicolas Planes, Gerard Ghibaudo, E. G. Ioannidis, Franck Arnaud, J. Jomaah, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Aristotle University of Thessaloniki, HERACLEITUS IIco-financed by the European Union (European Social Fund – ESF) and Greeknational funds through the Operational Program ‘‘Education andLifelong Learning’’ of the National Strategic Reference Framework(NSRF), European Project: CT208,Catrene, and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Materials science, business.industry, Infrasound, Oxide, Electrical engineering, Charge density, Silicon on insulator, Biasing, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Noise (electronics), [SPI.TRON]Engineering Sciences [physics]/Electronics, chemistry.chemical_compound, chemistry, Gate oxide, 0103 physical sciences, MOSFET, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract

International audience; Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

Published
2012
Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results