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Nano-electro-mechanical (NEMS) systems are compacted to be of dimension less than a micron by MEMS. Extremely high fundamental frequencies can be reached in this size regime while at the same time maintaining extremely elevated mechanical sensitivity (minute strength constant). This powerful mixture of attribute directly translate in to elevated strength sensitivities, ultra-low power operability's, and the capability to cause functional nonlinearities by very diffident controlling powers. Current paper addressed NEMS in this overview and will detail numerous of their stimulating original application. At the threshold for this new domain, however, there is a steep entry fee: modern innovation is key to realizing NEMS ' full potential. Some of the foundations of MEMS ' methods would obviously not usefully fit into the NEMS system. The main problem is the dimensions of the systems relative to the circuits in which they will be embedded, its excessive volume-to-surface ratio and its alternative “characteristic operating range.” These create some of the main challenges currently facing the development of NEMS. The majority of well-known of these is the requirement for: Very sensitive, elevated values of bandwidth dislocation transducer; unprecedented controls of quality of surface and adsorbents; new mode of capable Nano-scale actuations; and new surface as well as bulk Nano-machining approaches that are precise, robust and routinely reproducible.

The “Quantum Dot Cellular Automata” or QCA is mainly used to design and simulate ‘3D’ structures for area-occupation, latency and total power reduction of any electronic circuit. At present, this “Nano-technology world” requires less-complex, small-size, high-frequency, fault-tolerant, low-power devices to increase the component-density in a single die. QCA designs are the well-known and optimum alternative of CMOS designs due to its above mentioned advantages. Further, reversible gates can also be formed based on QCA design. Reversible logic not only reduce the complexity of the design but also it can increase the information storage possibility by saving the power and energy. It is capable of reducing the leakage power (‘KTln2’ amount of dissipated energy for every bit can be ignored due to this logic). Cost of any device depends on the delay, power and occupied-area of the device which can be decreased by reversible multilayer (‘3D’) QCA structures. So, this proposed technique has an ability to provide the design for a cost-effective electronic device with good scalability and fault-tolerance. In the present work, we have simulated of an “Arithmetic and Logic Unit” in “QCA Designer” and “Xilinx” software. The first software is used due to the above advantages and here we apply reversible logic (reversible TSG gate with reversible AND-OR gate). This ALU is capable of performing one arithmetic (addition of two inputs) and three logical operations (AND, OR and XOR operations of two inputs) at a time. The TSG gate is used here as a full-adder with two input XOR operation and The reversible AND-OR gate is utilized for getting the AND result and OR result of two inputs. This design is also required a “4:1 MUX” which helps to select the operations properly. Schematic designs of proposed design with calculated values of delay and total power (for different room-temperature) are achieved in our work by using ‘Xilinx’ simulator. The used Verilog coding of our formed-design is also implemented in a “FPGA Board” (“Spartan 3E”) for hardware verification. Our presented circuitry can also continue its functionalities at high-temperature.

Now adays Very Large-Scale Integration (VLSI) circuits have good or great demand. Because CMOS circuit design having less power consumption. Transistors on the chip is doubled every two years, according to Moore’s law. So, it means transistor size is decreasing. This leads to increase the chip density and decrease the device size. The write and read depending on the bitline and bitline bar discharging and charging. When design the memory in below 16 nm uses Fin Field effect Transistor (FinFET) technology instead of CMOS (Complementary metal oxide semiconductor field effect transistor). Because to avoid short channel effect. Comparing leakage power, dynamic power and static power at 90 nm technology and write delay, read delay at both 90 nm and 45 nm technology in nine transistors (9 t), eight transistor (8 t) and six transistor (6 t) sram cell.

The manuscript presents the smart view of hybrid PV-wind power generation system by implementing the fuzzy logic at required stages for exploiting the maximum efficiency of the renewable system. The extracted power is processed through quadratic boost converters(QBC) and multi-level inverters for efficient maintenance of power quality and stability in the grid. The converters in the topology are provided with the fuzzy logic controllers to enhance the power extraction from the energy conversion system and performance of the overall system. The idea of this circuit topology is configured from various analysis of conventional systems by eliminating the unbalanced issues such as unbalanced voltages, power events, stability and quality issues. The proposed circuits are simulated on the Matlab software by providing the real time data such as power events in the grid. The results are contrasted with conventional topologies and discussed in the upcoming sections of the manuscript with the detailed simulation.

Harnessing energy from the environment promotes the rapid development of micro-power generators and relevant power management modules of alternating current (AC) line-filtering to obtain a stabilized direct current (DC) output for storage and use. Micro-supercapacitors (MSCs) with miniaturized volume and high-frequency response are regarded as a critical component in filtering circuits for microscale power conversion. Here, we reported the fabrication of the wafer-sized planar MSCs (M-MSCs) based on 2D Ti3C2Tx MXene using a photolithography technique. The M-MSCs exhibited an areal capacitance of 153 μF cm−2 and a frequency characteristic (f0) of 5.6 kHz in aqueous electrolyte. Moreover, by employing suitable ionic liquid as electrolyte, the voltage window was expanded to 2 V and the f0 could be pushed to 6.6 kHz relying on the electrical double-layer mechanism and lower adsorption energy while maintaining quasi-rectangular cyclic voltammogram curves at 5000 V s−1. Furthermore, the integrated MSCs pack was constructed and exhibited excellent rectifying ability by filtering various high-frequency 5000 Hz AC signals with different waveforms into stable DC outputs. Such ultrahigh-rate and high-voltage M-MSCs module for kHz AC line-filtering would be potentially integrated with customizable electronics to realize on-chip rectifiers in high-density integrated circuit.

Hardware electronic synapse and neuro-inspired computing system based on phase change random access memory (PCRAM) have attracted an extensive investigation. However, due to the intrinsic asymmetric reversible phase transition, the defective weight update of PCRAM synapses in aspects of tuning range, linearity and continuity has long required a system-level complexity of circuits and algorithms. The cell-level improvements to a great extent may slim the system thus achieving efficient computing. We report in this work the great enhancement of Ge2Sb2Te5 (GST) based PCRAM synapses by combining materials engineering and pulse programming. It is found that carbon doping in GST retards the rate of phase changing thus increasing the controllability of the conductance, while non-linear programmable pulse excitations can eventually lead to a reliable synaptic potentiation and depression. A set of improved programmable pulse schemes for spike-timing dependent plasticity was then demonstrated, suggesting its potential superiority in flexible programming and reliable data collection. Our methods and results are of great significance for implementing PCRAM electronic synapses and high-performance neuro-inspired computing.

In this paper, a new adiabatic logic family named as adiabatic differential cascode voltage-switch logic (A-DCVSL) for low power applications is presented. The family operates on a two-phase split level sinusoidal power clock instead of four-phase trapezoidal power clock. The proposed A-DCVSL circuits reduce the power dissipation by charge recovery and minimizing the peak current flow. The behavior of the inverter is analysed and the power dissipation of A-DCVSL circuit is mathematically modeled. The performance of A-DCVSL inverters is compared with other existing differential adiabatic logic families. A full subtractor is also designed to exhibit the benefits at the application level. The results confirm that the proposed A-DCVSL circuit outperforms in terms of power dissipation and can be adapted to the design of lower power applications. The simulations were performed on Tanner EDA tool using 32 nm PTM technology parameters.

In the present era of data-driven architectures like 5G, Internet of things (IoT), Artificial Intelligence (AI), etc, the requirement of fast-switchable memory storage is more than ever. Oxide resistive switches are considered to be a primary choice in the non-volatile memory design. In this work, we have engineered the conventional metal-insulator-metal (MIM) structure of an oxide memristor (Ag/ZnO/ITO) by inducing an additional oxide layer La0.7Sr0.3MnO3 (LSMO) at the interface between the active layer (ZnO) and Ag electrode. The presence of LSMO acts as a reservoir for the oxygen vacancies, easing the conducting filament formation process in ZnO, thereby enabling drastic improvement of the switching performance and offering reliable endurance over multiple switching cycles. First-principles-based calculations suggested the role of Oxygen vacancies in controlling the electronic state of ZnO and formation of vacancies in the resistive switching process, which is in agreement with the experimental observation. The current results pave ways for improving the switching performance of resistive memory circuits through simple structural engineering incorporation, which lies at the heart of oxide electronics.

In this paper, a physical Sr 0.97 Ba 0.03 TiO 3 - x (SBT) memristor with the voltage threshold characteristic was prepared. For characterizing the electrical characteristics of SBT memristor accurately, an adaptive voltage threshold memristor model was proposed. The synaptic plasticity of SBT memristor with different pulse stimulation was analyzed. Moreover, a Pavlov associative memory circuit was designed in the LTSPICE environment, which is composed of neuron circuit and memristive synaptic circuit. The neuron circuit can generate spike signals when the input signals exceed the threshold, and the synaptic weight can be tunable continuously by spike signals. Different from other memristive synaptic circuits, the proposed memristive synaptic circuit is based on physical SBT memristor, and the change of synaptic weight can be truly reflected in the circuit. In Pavlov’s dog experiment, when the presynaptic neuron receives the conditioned stimulus (CS) before the unconditioned stimulus (US), the synaptic weight of SBT memristor is increasing and the associative memory is building. When the presynaptic neuron receives the CS alone, or presynaptic neuron receives the CS after the US, the synaptic weight of SBT memristor is decreasing and the associative memory is losing. This phenomenon is highly similar to the building and losing processes of biological associative memory. These experimental results verify the feasibility and applicability of SBT memristor as electronic synapse in neuromorphic applications, and pave the way towards further development of artificial neural networks.

The single-gate (SG) and dual-gate (DG) organic thin-film transistors (OTFTs) performances have been analyzed by using high dielectric constant material. The dielectric and gate electrode material variation does the comparative study on SG (bottom-gate bottom-contact configuration) and DG-based OTFTs. Variation in thickness of the dielectric layer (step size 2) and channel length (step size 10) results in a deviation in the performance parameters like threshold voltage, mobility, ION/IOFF current ratio, subthreshold swing, trans-conductance, etc. Such variations in the performance of OTFT have been observed by using 2D numerical devices ATLAS simulator. Subsequently, it is analyzed that reduction in channel length from 50 µm to 10 µm leads to an increase in the drain current from −9.88 × 10−10 A to −5.8 × 10−9 A (in case of DG-OTFT) and from −9.84 × 10−11 A to −5.3 × 10−9 A (in case of SG-OTFT). Similarly, the reduction in dielectric layer thickness from 10 nm to 2 nm leads to an increase in the drive current/the current ratio from 3.9 × 1012 to 1.3 × 1013 (in case of SG-OTFT) and from 1.8 × 105 to 1.5 × 106 (in case of DG-OTFT). So achieving a better result, we switch to DG- OTFT compared to SG-OTFT, which would be helpful in various future applications like chemical sensors, circuits, RFIDs, etc.

This study describes a new method to compensate bias heating effects for microbolometer readout circuits using a finely adjustable CMOS resistance as a reference. The proposed self calibrated cooler-less structure dynamically modifies CMOS resistance during integration time. This compensation structure also includes a feedback loop, which forces the oscillators to work in the linear region. The proposed self calibration circuit is designed and simulated using a 65-nm process node, and achieves 40 mK NETD (Noise Equivalent Temperature Difference) value for one percent resistance non-uniformity of pixel resistance values across one row. The layout area of this circuit occupies approximately one third of the layout area used by classical readout circuits. The circuit dissipates one third of power compared with classical microbolometer readout approaches.

Memristors have drawn a significant widespread attention from the research community since past decade due to their high-speed operational potential in analog applications. However, it has been difficult to achieve the memristor behavior directly from solid state solution and state of the art. This work presents a novel emulator design to mimic the memristor behavior. A generic and simple emulator circuit for a voltage controlled memristor is presented using a differential difference current conveyor, which is based on a versatile second-generation current conveyor methodology. Although, the voltage-controlled memristor models are of great importance, no significant research has been done to build emulator circuits for this type of memristor. A high-speed low power DDCC in 130 nm RF-CMOS process has been designed and functional simulations have been performed on SPICE environment using Advanced Design System (Keysight Technology). Proposed DDCC then implements the memristor operation with compatible specifications. Finally, the memristor operation and potential has been verified by its application in high speed active filter operations. A universal biquad section has been presented which employs the designed memristor emulator, with 30 mW of power dissipation with ± 1.5 V supply.

Solar energy is a non-depleting source of energy where one hour of solar energy reaching on earth’s surface is enough to meet the world’s demand for a year. In present scenario people need electric power every single minute. Solar energy can be easily generated using photovoltaic panels for any type of purposes i.e., domestic or industrial. It is also very efficient and clean energy system. A lot of researches are going on solar energy to make it more efficient so that maximum energy can be drawn from sunlight. Conversion of solar energy to electrical energy includes a number of converters according to its use. One major issue related to a converter is with respect to switching losses, on state losses and sometimes complex gate circuits. Primarily from few years a lot of emphasis is given to reduce the number of switches in a converter circuit. Nine Switch Converters are a major leap in the world-changing scenario towards the converters that are being employed to the various systems, due to its various advantages which include fewer switching devices than usual, less switching losses and high-power quality. In this paper, a Photovoltaic solar array is used as a source along with a Nine-Switch converter to power a separate three-phase load. The voltage generated by the Photovoltaic solar array is regulated using a dc-dc boost converter whose output is supplied to the input of the nine-switch converter that will ultimately power the loads. The gating signals for the nine-switch converter employs the space vector modulation technique, as space vector modulation has a number of advantages when compared to other modulation techniques which includes less harmonics, higher modulation index etc. A MATLAB simulation is included to show the performance of the system.

The research on the discharge characteristics of PZT under conventional applications has made good progress. In theory, the piezoelectric equation can be used to describe the relationship between stress and electrical output. However, existing studies have shown that the relationship becomes nonlinear under high-pressure stress pulses. To study the effect of the loading frequency and the circuit load on the electrical output performance of PZT under high-pressure stress pulse, the experiments were carried out based on the split Hopkinson pressure bar and a dynamic & static universal test machine. The effects of different circuits on the output voltage under different frequency high-pressure stress pulses are analyzed. Both theory and experiments prove that the critical open-circuit measurement resistance (Rcritial) of PZT decreases with the stress frequency. The output voltage is positively correlated with the load resistance when that is less than Rcritial. It is confirmed by loading different circuits (diodes are added in different positions) that reverse positive charge appears at the negative pole of the material during the stress unloading stage. PZT has the maximum dischargeable strain e E M under the high-pressure stress pulses, and it no longer generates induced charges when the strain is greater than e E M . When constant strain rate loading makes PZT completely release energy, its open-circuit output voltage is proportional to the strain rate.

Summary The major advantages of organic electronics are their solution processability and unique optoelectronic performance. The long-range ordered single-crystal organic semiconductor provides the best device performance, as it guarantees efficient charge injection and transport and minimum defect states. Thus, a facial solution-printing-based method to fabricate single-crystal organic devices and circuits is of great importance to the development of organic electronics, but its development is still challenging. Herein, we propose a general strategy to construct an organic single-crystal device array entirely by solution-based methods. Taking organic field-effect transistors (OFETs) as an example, the recent progress of organic crystal fabrication, patterning, and high-resolution printed contacts is summarized. Finally, future research directions for this field are suggested.

In-Memory computation has received considerable attention in the light of recent advances made in the memristor-based design. Non-volatile memristor devices are compatible with both the crossbar structure, CMOS technology, and can perform logical operations when subjected to suitable voltages. In this work, a generalized synthesis technique is presented to implement the logic functions inside pure memristive-crossbar. To initiate the process, two novel memristive-designs are proposed for 2:1 multiplexer (MUX) that follow Memristor Aided loGIC (MAGIC) design style. Experimental results showed that each design is at least 68.05 %, 35.92 % more energy-efficient than their existing IMPLY, MAGIC-based designs, respectively. One of our proposed MUX designs is optimized in memristor-count, and the other is latency-optimized. The latency-optimized design offers 20 % improvement in performance compared to its existing IMPLY, MAGIC-based peers. Based on the simulation methodology presented in this work, the memristive-MUXes are simulated in Cadence Virtuoso. Subsequently, our proposed MUX designs are used for the technology mapping of the nodes of the Binary Decision Diagrams (optimized in terms of node, path counts) for the logic functions. Our proposed technique optimizes the implemented logic circuits in terms of memristor-count, step-count, and provides the details for – latency, required memristors, energy, area. Comparison of the synthesis results showed that the circuits generated using our proposed MAGIC-MUXes, are at least 82.21 %, 44 % more energy-efficient, and can offer 18.94 %, 18.92 % more performance-improvements than their peers, realized using the existing IMPLY, MAGIC-MUX designs, respectively. Also, our proposed-MUX based circuits need at least 56.73 % lesser crossbar-areas than their existing MAGIC-MUX based peers, which indicates the scope for large scale parallel processing inside a given memristive-memory.

Fin-and-tube heat exchangers can have active circuits directly adjacent to inactive circuits at part load conditions, leading to cross-fin conduction. Cross-fin conduction needs to be accounted for in heat exchanger modelling to accurately predict heat exchanger performance. This study explores how refrigerant circuitry can influence cross-fin conduction in multi-circuit evaporator coils. Our advanced segment-by-segment heat exchanger model is validated against two-phase refrigerant data obtained from our experimental facility. Three, custom designed, multi-circuit fin-and-tube heat exchanger coils with distinct circuities were used for validation purposes, including an interleaved, vertical and block circuited coils, respectively. A total of 162 experiments with several refrigerant and air inlet conditions, at full load (all circuits active) and part load (some circuits active) were carried out. At full load, for all coils, differences in coil capacity between simulated and experimental capacities were no greater than 10%, for part load the differences are larger. For the test coil with interleaved circuitry, operating with 3 of 8 circuits active, the mean average percentage error (MAPE) between experimental and simulated capacity was 2.7% when cross-fin conduction was considered, increasing to 7.7% when it was ignored. Similarly, for test coil with block circuitry, operating with 2 out of 4 circuits active, the MAPE between experimental and simulated capacity was 1.7% when cross-fin conduction was considered, and 3.4% when ignored. Results suggest that the effect of cross-fin conduction on coil capacity is directly proportional to number of inactive circuits, and it is more pronounced on interleaved circuitry compared to block circuitry.

This article introduces a kind of aperiodically sampled-data intermittent control to investigate the synchronization issue of stochastic multi-links network. Therein, the sampling intervals are variable in the aperiodically intermittent control, while the actuator saturation is taken into consideration. Distinguish from previous control methods, by combining with the advantages of both the sampled-data and actuator saturating control and the aperiodically actuator saturating intermittent control, we design the sampled-data and actuator saturating intermittent control. Meanwhile, the aperiodically sampled-data intermittent control and the sampled-data and actuator saturating control are used to settle the synchronization problem of stochastic multi-links network. After that, some sufficient conditions are obtained based on Lyapunov method, some techniques of inequalities and a graph-theoretic approach. The control law is determined simultaneously, which depends on the coupling strength, the perturbed intensity of noise, the upper and lower bounds of sampling intervals, the lower bound of intermittent control intervals and the maximum rest time ratio. Then, our theoretical results are used in the synchronization issue of stochastic multi-links Chua’s circuits network. Ultimately, a numerical example is presented to illustrate the validity of the theoretical results.

Gallium nitride (GaN)-based power conversion systems exhibit striking competitivity in realizing compact and high-efficiency power management modules. Recently emerging GaN-based p-channel field-effect transistors (FETs) and monolithic integration techniques enable the implementation of GaN-based complementary logic (CL) circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functionality. In this article, holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems, based on the material limit of GaN and state-of-the-art experimental results. It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT (high-electron-mobility transistor) platform could be as short as sub-nanosecond, which sufficiently satisfies the requirement of power conversion systems with operating frequencies less than 10 MHz. By replacing the currently adopted n-FET-based logic gates (e.g., directly coupled FET logic) with CL gates, the power consumption of peripheral logic circuits could be substantially suppressed by more than 103 times, mainly due to the elimination of the pronounced static power loss. Consequently, the energy efficiency of the entire system could be substantially improved.

We study the effect of noise on the classical simulatability of quantum circuits defined by computationally tractable (CT) states and efficiently computable sparse (ECS) operations. Examples of such circuits, which we call CT-ECS circuits, are IQP, Clifford Magic, and conjugated Clifford circuits. This means that there exist various CT-ECS circuits such that their output probability distributions are anti-concentrated and not classically simulatable in the noise-free setting (under plausible assumptions). First, we consider a noise model where a depolarizing channel with an arbitrarily small constant rate is applied to each qubit at the end of computation. We show that, under this noise model, if an approximate value of the noise rate is known, any CT-ECS circuit with an anti-concentrated output probability distribution is classically simulatable. This indicates that the presence of small noise drastically affects the classical simulatability of CT-ECS circuits. Then, we consider an extension of the noise model where the noise rate can vary with each qubit, and provide a similar sufficient condition for classically simulating CT-ECS circuits with anti-concentrated output probability distributions., 19 pages, 2 figures

Adaptive response to the timely constant stimulus is the common feature of real neurons. The circuit of the adaptive neuron model consumes less power and requires less data transmission bandwidth compared to the circuit of the non-adaptive neuron model, especially for encoding time-varying signals. Memristor is a good candidate for mimicking the behavior of neurons so that the simple memristor-based circuit can directly emulate many specific behaviors of the neurons with low power and low area consumption. In this work, for the first time, we show that as the nonvolatile switching property of the memristor can be useful for representing long-term adaptation behavior in the memristor-based neuron, the short-term adaptation behavior can also be emulated directly using the same memristor-based circuit due to the volatile switching property of the memristor. Here, short term adaptation is realized using the volatile property of memristor, unlike neuron circuits where adaptation is realized using leakage modulation. As a result, in the memristor-based neuron extra power dissipation can be reduced. Two different types of memristors are used for implementing the proposed circuit of adaptive leaky integrate-and-fire neuron, the volatile/non-volatile memristor and threshold switching memristor are in the charge and discharge path of the capacitor, respectively. Results show that the volatile or non-volatile resistance change of charging memristor upon different input patterns to the neuron circuit determines the type of adaptive behavior of the neuron response, i.e. the neuron may show short-term adaptation or long-term adaptation or does not show an adaptation behavior at all. Comparison with similar works shows that the energy consumption per spiking of the proposed neuron is relatively low, while the circuit is very area-efficient.

Surprisingly, no investigation has been explored relationships between operating variables and metallurgical responses of coal column flotation (CF) circuits based on industrial databases for under operation plants. As a novel approach, this study implemented a conscious-lab “CL” for filling this gap. In this approach, for developing the CL dedicated to an industrial CF circuit, SHapley Additive exPlanations (SHAP) and extreme gradient boosting (XGBoost) were powerful unique machine learning systems for the first time considered. These explainable artificial intelligence models could effectively convert the dataset to a basis that improves human capabilities for better understanding, reasoning, and planning the unit. SHAP could provide precise multivariable correlation assessments between the CF dataset by using the Tabas Parvadeh coal plant (Kerman, Iran), and showed the importance of solid percentage and washing water on the metallurgical responses of the coal CF circuit. XGBoost could predict metallurgical responses (R-square > 0.88) based on operating variables that showed quite higher accuracy than typical modeling methods (Random Forest and support vector regression).

Approximate computing has emerged as an efficient design methodology for improving the performance and power-efficiency of digital systems by allowing a negligible loss in the output accuracy. Dedicated hardware accelerators built using approximate circuits can solve power-performance trade-off in the computationally complex applications like deep learning. This paper proposes an approximate radix-4 Booth multiplier and hardware accelerator for deploying deep learning applications on power-restricted mobile/edge computing devices. The proposed accelerator uses approximate multiplier based parallel processing elements to accelerate the workloads. The proposed accelerator is tested with matrix–vector multiplication (MVM) and matrix–matrix multiplication (MMM) workloads on Zynq ZCU102 evaluation board. The experimental results show that the average power consumption of the proposed accelerator reduces by 34% and 40% for MVM and MMM respectively, as compared to the conventional multiply-accumulate unit that was used in the literature to implement similar workloads. Moreover, the proposed accelerator achieved an average performance of 5 GOP/s and 42.5 GOP/s for MVM and MMM respectively at 275 MHz, which are 14 × and 5 × respective improvements over the conventional design.

Monotone Boolean circuits are circuits where each gate is either an AND gate or an OR gate. In other words, negation gates are not allowed on monotone circuits. This class of circuits has sparked the attention of researchers working in several subfields of combinatorics and complexity theory. In this work, we consider the notion of certification-width of a monotone Boolean circuit, a complexity measure that intuitively quantifies the minimum number of edges that need to be traversed by a minimal set of positive weight inputs in order to certify that a given circuit is satisfied. We call the problem of computing this invariant as Succinct Monotone Circuit Certification (SMCC) . We prove that SMCC is NP-complete even when the input monotone circuit is planar. Subsequently, we show that k -SMCC , the problem parameterized by the size of the solution, is W[1]-hard, but still in W[P]. In contrast, we show that k -SMCC is fixed-parameter tractable when restricted to monotone circuits of bounded genus.

This paper evaluates the benefits of explicitly integrating online mineral liberation data in control systems for grinding–separation circuits. Although liberation is a critical variable for separation processes, this endeavour has not been attempted mainly because sensors providing continuous online or even at line measurements are yet to be developed. The ore particle size is seen as the key variable influencing mineral liberation. In this study, a phenomenological two-stage comminution circuit simulator previously calibrated from industrial and laboratory data was supplemented with a three-cell flotation line in open circuit. An economic real-time optimisation (RTO) layer coordinates the setpoints of a linear model predictive controller (MPC) of the grinding circuit. Assumed measurable, mineral liberation data feeds the RTO to update the particle size target parameter in an internal model predicting the flotation concentrate mass flow rate, grade, and recovery. Profits, derived from concentrate production rate, grade, and metal recovery, can improve by up to +5% compared with the standard approach, i.e. keeping the flotation feed particle size target constant.

In this paper, a novel hardware attack based on principal component analysis (PCA) is proposed to break a leakage power analysis (LPA)-resistant cryptographic circuit (CC) efficiently. Although the added false keys which are used for masking the secret key of the LPA-resistant CC are secure and effective against regular LPA attacks, they may be precisely modeled by eigenvalues and eigenvectors under PCA. After performing the proposed PCA on the LPA-resistant CC, all the added false keys can be removed to expose the corresponding secret key. As shown in the result, only 2000 number of plaintexts are sufficient to crack an LPA-resistant CC by utilizing the proposed PCA-assisted LPA attacks.

It is a big challenge to construct large-scale, high-resolution and high-performance inkjet-printed metal oxide thin film transistor (TFT) arrays with independent gates for the new printed displays. Here, a self-confined inkjet printing technology has been developed to construct large-area (64 × 64 array), high-resolution and high-performance metal oxide bilayer (In2O3/IGZO) heterojunction TFTs with independent bottom gates on transparent glass substrates. Inkjet printing In2O3 dot arrays with the diameters from 55 to 70 μm and the thickness of ∼10 nm were firstly deposited on UV/ozone treated AlOx dielectric layers, and then IGZO dots were selectively printed on the top of In2O3 dots by self-confined technology to form In2O3/IGZO heterojunction channels. When the inkjet-printed IO layers treated by UV/ozone for more than 30 min or oxygen plasma for 5 min prior to print IGZO thin films, the mobility of the resulting printed In2O3/IGZO heterojunction TFTs are correspondingly enhanced to be 18.80 and 28.44 cm2 V−1 s−1 with excellent on/off ratios (>108) and negligible hysteresis. Furthermore, the printed N-Metal-Oxide-Semiconductor (NMOS) inverter consisted of an In2O3/IGZO TFT and an IGZO TFT has been demonstrated, which show excellent performance with the voltage gain up to 112. The strategy demonstrated here can be considered as general approaches to realize a new generation of high-performance printed logic gates, circuits and display driving circuits.

It is of great significance for absorber designers to correctly understand impedance matching and its related calculation methods, because excellent impedance matching effect is an important prerequisite for absorber to consume electromagnetic wave (EMW). However, there are some problems in literatures, such as the lack of deep understanding of impedance matching and application conditions of Eq. (3) for the calculation of reflection loss (RL). Based on the transmission line theory of electronic circuit, this paper expounds the definition, symbol, property of various impedances and their influence on impedance matching effect. On the basis of simplifying the actual situation in the process of EMW absorption to the correct transmission line model, the original transmission line model of RL calculation formula and its limitation are pointed out. The doubts about the validity of the quarter wavelength theory in literatures are explained from three aspects: the reduction of EMW length, the multiple reflection and the impedance transformation of absorber.

Laser-induced graphitic carbon (LIGC) is a promising technology to manufacture conductive carbon in a cost-effective manner on a flexible substrate with a scanned laser. One limitation preventing the widespread adoption of LIGC in electronic devices and circuits has been its relatively high sheet resistance. Here, we report the lowest sheet resistance to date for LIGC engraved on flexible polyimide of 6.14 ± 0.11 Ω/□. Several general strategies are identified to minimize sheet resistance. Most importantly, the total laser energy per unit area delivered to the substrate needs to be maximized. This can be achieved by increasing laser power, decreasing laser scan speed and increasing overlap between adjacent pulses. Pulse overlap can be increased by increasing linewidth (raster rather than vector mode) and increasing the dots per cm resolution, i.e., decreasing spacing between pulses, which also improves LIGC uniformity. Further, decreasing scan speed increases the ablation threshold because of increased cooling between pulses enabling more energy to be delivered without the material ablating. These insights were obtained using a combination of electrical measurements, thermal modeling and material characterization. With optimized energy delivery, a domain size (La) of about 60 nm was obtained, which highlights the high quality of the obtained LIGC material.

BACKGROUND: SARS-CoV-2 aerosolization during noninvasive positive-pressure ventilation may endanger health care professionals. Various circuit setups have been described to reduce virus aerosolization. However, these setups may alter ventilator performance. RESEARCH QUESTION: What are the consequences of the various suggested circuit setups on ventilator efficacy during CPAP and noninvasive ventilation (NIV)? STUDY DESIGN AND METHODS: Eight circuit setups were evaluated on a bench test model that consisted of a three-dimensional printed head and an artificial lung. Setups included a dual-limb circuit with an oronasal mask, a dual-limb circuit with a helmet interface, a single-limb circuit with a passive exhalation valve, three single-limb circuits with custom-made additional leaks, and two single-limb circuits with active exhalation valves. All setups were evaluated during NIV and CPAP. The following variables were recorded: the inspiratory flow preceding triggering of the ventilator, the inspiratory effort required to trigger the ventilator, the triggering delay, the maximal inspiratory pressure delivered by the ventilator, the tidal volume generated to the artificial lung, the total work of breathing, and the pressure-time product needed to trigger the ventilator. RESULTS: With NIV, the type of circuit setup had a significant impact on inspiratory flow preceding triggering of the ventilator (P < .0001), the inspiratory effort required to trigger the ventilator (P < .0001), the triggering delay (P < .0001), the maximal inspiratory pressure (P < .0001), the tidal volume (P = .0008), the work of breathing (P < .0001), and the pressure-time product needed to trigger the ventilator (P < .0001). Similar differences and consequences were seen with CPAP as well as with the addition of bacterial filters. Best performance was achieved with a dual-limb circuit with an oronasal mask. Worst performance was achieved with a dual-limb circuit with a helmet interface. INTERPRETATION: Ventilator performance is significantly impacted by the circuit setup. A dual-limb circuit with oronasal mask should be used preferentially.

A novel self write-terminated driver is proposed for the hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuits based on logic-in-memory (LIM) structure. Using continuous write monitoring mechanism, the novel circuitry completely eliminates the unnecessary flow of write current which abolishes the wastage of write energy in the proposed write driver. Hence, the total energy required for writing process is reduced noticeably by 63.32% in novel write driver compared to the con�ventional write circuit. Monte-Carlo simulation is then performed by incorporating process and mis�match variations for CMOS and extracted parameters of MTJ. Simulations are also carried out for the proposed write driver, by varying the transistor sizes and supply voltage to analyze its switching prob�ability to obtain safe operating region. Further, the proposed write driver is integrated with hybrid full adder to demonstrate its feasibility in low-power VLSI circuits.

The development and use of cloud based tools in virtual learning has been increasing in recent years. Electronic Design Automation (EDA) or Electronic Computer-Aided Design (ECAD) is one of the most important tools that are used for electronic circuit design and simulation. There is a number of available cloud based EDA tools that are used in industry and educational institutions. This paper introduces a hybrid-circuits cloud-based platform that enables students to design, simulate, and model both analog and digital electronic systems. Circuits-cloud became one of the top best electronic circuit cloud tools, it is ranked as number one in Google search for the “top list of electronic circuit cloud tools”. It integrates the Internet of Things (IoT) and cloud based tools by adding sensors, actuators, and interact with the physical design in the laboratory in the real time. This platform acts as a comprehensive laboratory device to capture components, draw circuits, integrate different components, apply different inputs, simulate, measure, and detect any defect or heated elements. This cloud-based platform introduces an integrated environment for digital, analog and IoT modeling. The platform has a laboratory device that can be integrated into circuits level with the cloud system to test the physical circuits in real-time remotely. This enables in-browser cloud platform for schematic capture, circuit simulation, and emulation. As a testimony of the platform of the modeling and simulation discipline, a list of about 100 types of equipment?s were included and tested. The cloud service is provided by Amazon Web Services (AWS) with high data protection service, AWS also provides encryption, key management, and threat detection that continuously monitors and protects user accounts and workloads. It is estimated to be able to serve approximately 2000 active students and tutors on a monthly average. This platform can be used in distance and blended learning as well.

High power consumption of Field-Programmable Gate Arrays (FPGAs) makes them a less attractive choice for ultra-low-power applications. Depending on the power source, ultra-low-power systems could either be constrained by power (energy harvesting systems) or by energy (battery-powered systems). In this work, we are evaluating four different FPGA tiles to find the one that is better suited for both power-constrained and energy-constrained systems. Ultra-low-power systems apply voltage downscaling to reduce the power consumption. However, the operational limits of different blocks do not allow conventional FPGA to be operated at very low voltage. Therefore, their logic capacity can only be increased by 2–4 times by applying voltage downscaling. In this work, we identified the blocks in FPGA tiles that are vulnerable at low voltage and replace them with alternate circuits. The results indicate that, by slight modifications in the conventional FPGA tiles, logic capacity can be increased up to 8 times, whereas power-delay-product can be reduced up to 74%.

The proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (back-end-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation on resistance and capacitance intermixed with resistance variation on vias between them, a very high dimensional design space exploration is necessary to synthesize a representative critical path circuit which is able to provide an accurate performance prediction. To this end, we propose a BEOL-aware methodology of synthesizing a representative critical path circuit, which is able to incrementally explore, starting from an initial path circuit on the post-Si target circuit, routing patterns (i.e., BEOL reconfiguring) as well as gate resizing on the path circuit. Precisely, our synthesis framework of critical path circuit integrates a set of novel techniques: (1) extracting and classifying BEOL configurations for lightening design space complexity, (2) formulating BEOL random variables for fast and accurate timing analysis, and (3) exploring alternative (ring oscillator) circuit structures for extending the applicability of our work. In summary, our synthesis framework is able to reduce the prediction error by 54% and 19% on average over that using the conventional critical path replica and using the conventional method exploiting gate sizing only, respectively.

Although this decade is witnessing tremendous advancements in fabrication technologies for quantum circuits, this industry is facing several design challenges and technological constraints. Nearest Neighbor (NN) enforcement is one such design constraint that demands the physical qubits to be adjacent. In the last couple of years, this domain has made progress starting from designing advanced algorithms to improved synthesis methodologies, even though developing efficient design solutions remains an active area of research. Here, we propose such a synthesis technique that efficiently transforms quantum circuits to NN designs. To find the NN solution, we have taken help of an ant colony algorithm which completes the circuit conversion in two phases: in the first phase, it finds the global qubit ordering for the input circuit and, in the second phase, a heuristic driven look-ahead scheme is executed for local reordering of gates. The proposed algorithm is first fitted into a 1D design and, later, mapped to 2D and 3D configurations. The combination of such heuristic and the meta-heuristic schemes has resulted promising solutions in the transformation of quantum circuits to NN-compliant architectures. We have tested our algorithm over a wide spectrum of benchmarks and comparisons with state-of-the-art design approaches showed considerable improvements.

By the reduction in the size of transistors and the development of submicron technology, as well as the construction of more integrated circuits on chips, leakage power has become one of the main concerns of electronic circuit designers. In this article, we first review techniques presented in recent years to reduce leakage power and then present a new technique based on the gate-level body biasing technique and the multi-threshold CMOS technique to minimize leakage power in digital circuits. Afterward, we develop another new method by improving the first proposed technique to achieve higher efficiency and simultaneously reduce leakage power and propagation delay in digital circuits. In the proposed technique, we use two dynamic threshold MOSFET transistors to reduce leakage current. In this paper, the body biasing generator structure is applied to reduce propagation delay. The proposed technique has been successfully validated and verified by post-layout simulation with Cadence Virtuoso based on the 32 nm process technology. We evaluate the efficiency of the proposed techniques by examining factors including power, delay, area, and the power delay product. The simulation results using HSPICE software and performance analysis to process corner variations based on the 32 nm process technology show that the proposed technique, in addition to having proper performance in different corners of the technology, significantly reduces leakage power and propagation delay in logic CMOS circuits. In general, the proposed technique has a very successful performance compared to previous techniques.

Three-dimensional printing (3D-printing) is an asset for rapid prototyping. Therefore, this technology is applied in amateur, fundamental as well as in applied research communities. Moreover, the fused deposition modeling even allows a cheap and fast 3D-printing of functional filaments such as conductive or ferro-magnetic materials. Further applicable materials enable the production of electronic circuits, electrodes or even complete analytical sensors. Here, a 3D-printed stand-alone drift tube ion mobility spectrometer (IMS) completely manufactured in one process is presented. The ionization chamber, the Bradbury-Nielsen gate, the partly conductive drift tube, and the detector including an aperture grid and a Faraday plate were printed by dual extrusion 3D-printing. Therefore, non-conductive polylactic acid (PLA) was utilized for the housing and conductive PLA was used for the electrodes, the ion gate and the detector. Due to a magnetic quick lock system and a modular design, each part of this innovative ion mobility spectrometer can be exchanged in an instant. All parts were validated individually and as a whole by comparing them to an ion mobility spectrometer produced by computerized numerical control machining consisting of polytetrafluoroethylene (PTFE). To investigate the performance, parameters regarding the resolution, resolving power, signal-to-noise ratio, running-in period and long-term stability were used involving a set of isomeric volatile organic compounds (VOCs). Notably, every single 3D-printed component as well as the completely 3D-printed IMS could keep up with the traditionally produced ones. Furthermore, the signal intensity was comparable to the signal intensity of the PTFE-IMS in exemplary optimization steps. The resolution, resolving power and signal-to-noise ratio could be improved by the variation of the Bradbury-Nielsen gate design, thus demonstrating the potential of the 3D-printing for design optimization and rapid prototyping of analytical instrumentation.

A fundamental challenge in synthetic biology is to create molecular circuits that can program complex cellular functions. Because proteins can bind, cleave, and chemically modify one another, and interface directly and rapidly with endogenous pathways, they could extend the capabilities of synthetic circuits beyond what is possible with gene regulation alone. However, the very diversity which makes proteins so powerful also complicates efforts to harness them as well-controlled synthetic circuit components. Recent work has begun to address this challenge, focusing on principles such as orthogonality and composability that permit construction of diverse circuit-level functions from a limited set of engineered protein components. These approaches are now enabling the engineering of circuits that can sense, transmit, and process information, dynamically control cellular behaviors, and enable new therapeutic strategies, establishing a powerful paradigm for programming biology.

The paper introduces a step-up multiple-input multi-stage dc-dc converter with a soft-switching for Photovoltaic (PV) applications. The proposed topology is constructed from series connection of switched capacitor circuits to minimize the effects of partial shading and mismatch between PV modules. A soft switching is achieved for the entire switches in the converter with no need for additional components. The applied technique utilizes the stray inductance of PCB traces to create a LC circuit so that the zero current switching is achieved for all switches. Moreover, the converter will take advantage of the superior features of Wideband gap devices in order to operate at high switching frequency. As a result, bulky capacitors in switched-capacitor circuits are significantly reduced, hence, small size multilayers ceramic capacitors with high temperature capability will be employed. Furthermore, with the lower losses and the higher temperature capability of Wideband gap devices, the thermal requirements will be reduced and with fast reverse recovery time, the snubber circuit are not required. Simulation results are presented, laboratory prototype is constructed, and experimental results are given at rated power to validate the feasibility of proposed dc-dc converter under soft switching operation.

In the present work, a solar cooking system that makes the controlled cooking possible inside the kitchen has been developed. This cook-friendly device introduces a new solar heat transfer concept for indoor cooking by providing a heater plate installed inside the kitchen to which solar heat is transferred from a parabolic collector by means of a heat transfer fluid. An LDR-based electronic solar tracker is integrated with the parabolic collector to automatically adjust its position so that it always remains directed towards the sun to collect maximum solar radiations. A solar P-V panel continuously charges a 12 V battery through charge controller. The battery supplies electricity to the solar tracker and to a DC motor-pump set which circulates heat transfer fluid through the heating coil of the heater plate. The pump is thermostatically operated to maintain correct temperature of the heater plate for effective cooking and for maintaining the nutritional value of food. The system is equipped with an electronic circuit, a digital thermometer, a pressure gauge and a relief by-pass valve in the heat transfer fluid line to ensure its safe and smooth operation. Exergy and enviroeconomic analyses of this device are also carried out to evaluate its efficiency and CO2 mitigation potential.

Biological circuits are responsible for transitions between cellular states in a timely fashion. For example, stem cells switch from an undifferentiated (unstable) state to a differentiated (stable) state. Conversely, cell cycle and circadian clocks are completed through transitions among successive (stable) states, i.e. waves, with (unstable) states switching them at definite timing. These transitions irreversibly determine the biological response or fate of a cell, to commit to reversible switches or to generate periodic oscillations of its state. Here, we review synthetic circuits that, in silico and in vivo, allow a cell to ‘make a decision’, i.e. to select which state to reach, among multiple ones available, through definite network designs. Specifically, we propose and discuss the designs, and their constituents motifs, which we consider to be more prone to reprogram cell behaviour, and whose parameters can be fine-tuned through systems biology and tested experimentally through Synthetic Biology. For these designs, exploration of the parameter space and of the influence of (external) cellular signals – which modulate circuit parameters – allows for the prediction of the circuit's response and its consequent impact on cell fate.

With the development of system-on-chip (SoC) chips, more and more design houses are cooperating with each other's. How to achieve benefit sharing and key management for multiple intellectual properties (IPs) has become an emergency problem. This work proposes an orthogonal obfuscation method to protect multiple IPs. The proposed method permits cooperators to control the project using different security keys, protects the patterns with an orthogonal key, and be convenient for the user to manage the key. For reasons of increased security, the proposed method hides the original keys to prevent information leakage. Multi-port Physical Unclonable Function (MPUF) circuit is used as the additional orthogonal key to cluster membership. It protects the IPs from hardware attacks such as brute-force attack, member leakage attack, reverse engineering and so on. The security analyzes results show that the proposed method reduces the key retrieval time by 36.3% over the baseline. The proposed obfuscation methods have been successfully applied to ISCAS′89 benchmark circuits and cryptographic algorithms. Experimental results indicate that the orthogonal obfuscation only increases the area by 3.43% and consumes 2.77% more power than the baseline.

In this paper, a method based on Green's function is proposed for the dynamic analysis of a rotor-bearing system with electromechanically coupled boundary conditions. The rotor system is supported by two ring-shaped piezoelectric dampers, which has been manufactured in our previous research. Based on the piezoelectric shunt resonant circuits, e.g., current flowing shunt circuit, the rotor system's boundary condition will become complicated and electromechanically coupled. The Laplace transform method is applied to solve the partial governing equations with such boundary conditions and the steady-state whirl Green's function is derived subsequently. Since the Green's functions are fundamental solutions of the system, the steady-state whirl solutions can be obtained by applying the superposition principle. Owing to the solutions’ concise form, it is convenient and suitable for analysis and computation. Validation of the proposed method is demonstrated by comparison with the finite element method (FEM). The simulated results show that the analytical solutions possess high accuracy and the piezoelectric damper has significant damping performance.

We present a design technique, Partial evaluation-based Triple Modular Redundancy (PTMR), for hardening combinational circuits against Single Event Upsets (SEU). The basic ideas of partial redundancy and temporal TMR are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. We have designed a fault insertion simulator to evaluate partial redundancy technique on the designs from MCNC′91 benchmark. Experimental results demonstrate that we can reduce the area overhead by up to 39.18% and on average 17.23% of the hardened circuit when compared with the traditional TMR. For circuits with a large number of gates and less number of outputs, there is a significant savings in area. Smaller circuits or circuits with a large number of outputs also show improvement in area savings for increased rounding range.

The globe is presently perusing technologies that entirely automate the processes with negligible losses. To achieve this, the world has initiated their automation from private bodies like home, school, etc. Thus, our paper is created to aid their process. This paper describes the solid-state switching using wireless networks. The proposed paper deals with the replacement of solid-state device instead of application of relays in home automation, as the performance of relays are not very effective in switching at higher inrush currents and they require an adequate environment for its better performance. Solid state devices have advantages like less power consumption, better life span, easy control, etc. Thus, the use of solid-state devices improves the performance of the entire home automation system. This proposed paper uses a protocol DALI (Digitally Addressable Lighting Interface) which controls switching of light resistive loads and improves communication. The soft switching operation of the circuit operates with the wireless network and improves the ability of carrying loads and has a strong controlling ability. The design and circuit framework can be adapted to any of the switch-controlled circuits which is relayed on solid state device.

Given an assignment of real weights to the ground elements of a matroid, the min–max weight of a ground element e is the minimum, over all circuits containing e , of the maximum weight of an element in that circuit with the element e removed. We use this concept to answer the following structural questions for the minimum weight basis problem. Which elements are persistent under a given weighting (belong to all or to none of the optimal bases)? What changes of the weights are allowed while preserving optimality of optimal bases? How does the minimum weight of a basis change when the weight of a single ground element is changed, or when a ground element is contracted or deleted? Our answer to this latter question gives the tropical ( min , + , − ) analogue of Kirchhoff’s arithmetic ( + , × , ∕ ) effective conductance formula for electrical networks.

Now days, electric vehicles play an essential role, and these are the most promising technologies that can significantly improve energy consumption effectively. In this investigation, Robust Electric Vehicle (REV) methodology has been used for high-performance rate, long operating range and throughput. Moreover, this REV automates the hardware mechanism and electric circuit efficiently. The improved ANFIS controller has designed for enhancing the circuit operations. This work reviews the present technologies and implemented model challenging the available electric vehicle designs. At the final performance, measures are calculated, i.e. accuracy, efficiency and throughput.

Tribo-electric nanogenerator proved a better alternative energy resource for many electronic accessories because of its flexible nature and optimized device properties. It opens up the use of polymer materials (PMs) for harvesting mechanical energy. The disadvantage of the Tribo-Electric Nano Generator (TENG) is likely lower durability, limited short circuit output current, structural changes, post-stress conditions, etc. The purpose of this review article is more focused on systematic and detailed descriptions of TENGs. It gives an overview of tribo-electric polymer-based material formation and triboelectricity generation, structural modes of tribo-electric polymer-based nanogenerators, and its comparisons, measurement, and quantification of tribo-electric polymer-based nanogenerators based on structural and load conditions. Also, this article focused on TNEG efficiency enhancement techniques using various charge control circuit techniques. Possible applications of TNEG for various self-powered devices such as sensor, actuators and bio-harvesting utilities are discussed in detail.

Smartphone's functional use is versatile in a modern-day application, which causes a prone in electronics performance; this is mainly due to gamming, high power camera applications, and increased usage of the internet. The continuous usage causes high power dissipation level in smartphones to increase by about 2–6 W. Depending on the scale of application, the cooling strategy is used in smartphones. In the present paper, a passive phase change material cooling strategy is proposed which can utilize the advantage of isotopic heat conduction from the electronic element. It changes its phase from solid to liquid to give an optimum cooling strategy over the electronic element which help in keeping the temperature of the electronic element below 85 °C. The economic mid-range customer segment smartphones are embedded with cooling strategy such as natural convection, indirect heat-pipe cooling and forced convection which typically fails for high power usage applications.

The nanoscale memristor device SPICE modeling is significant for memristive circuits and neuromorphic system design applications. In this paper, a novel modified piece-wise linear (PWL) window function proposed for the nonlinear property of the memristor SPICE model. The PWL window function used here can address the shortcoming of the parabola and Heaviside- step function based typical window functions proposed in the literature, those are established by symmetrical functions. However, in most of the typical window functions, the monotonically increasing and the asymmetrical functions have not been addressed. Also, using this PWL-window function based memristor model, a binary-weighted memristor-based artificial synaptic circuit has been designed. The performance of the device model demonstrated by the efficiency of designed artificial synapse sensitivity to the external input signal.