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Abstract: We present a novel wavelength multiplexing concept for an integrated sensor array based on SOI photonic MachZehnder interferometers. The characteristics of the entire device are discussed and the design, performed on the basis of FEM and 3D FDTD simulations, as well as first measurements of the nanophotonic key components–micro ring resonators and a photonic wire Bragg gratings–are presented. [ABSTRACT FROM AUTHOR]

A dual gate metal oxide semiconductor field effect transistor (MOSFET) with electrically variable shallow junctions (EJ-MOSFET) has been fabricated on silicon on insulator (SOI) substrates. This kind of transistor allows testing the limits of scalability at relaxed process requirements. Transistor gate lengths down to 12 nm have been structured by electron beam lithography (EBL) and specific etching processes. The coupling of the upper gate to the inner transistor is carefully investigated. [Copyright &y& Elsevier]

Abstract: Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd2O3 and TiN gate electrodes are presented. [Copyright &y& Elsevier]

Abstract: In this work, double-gated field effect transistors manufactured from monolayer graphene are investigated. Conventional top–down CMOS-compatible processes are applied except for graphene deposition by manual exfoliation. Carrier mobilities in single- and double-gated graphene field effect transistors are compared. Even in double-gated graphene FETs, the carrier mobility exceeds the universal mobility of silicon over nearly the entire measured range. At comparable dimensions, reported mobilities for ultra-thin body silicon-on-insulator MOSFETs cannot compete with graphene FET values. [Copyright &y& Elsevier]

Abstract: Novel gate stacks with epitaxial gadolinium oxide (Gd2O3) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10–7 Acm–2 are observed at a capacitance equivalent oxide thickness of CET=1.8nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86nm at a Gd2O3 thickness of 3.1nm yield current densities down to 0.5Acm−2 at V g=+1V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd2O3 gate stacks for future material-based scaling of CMOS technology. [Copyright &y& Elsevier]

Abstract: Epitaxial gadolinium oxide (Gd2O3) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time. [Copyright &y& Elsevier]

Abstract: Metal gate electrodes of sputtered aluminum (Al), titanium nitride (TiN) and nickel aluminum nitride (NiAlN) are investigated in this work. They are compared with respect to their compatibility with metal organic chemical vapor deposited (MOCVD) hafnium dioxide (HfO2) gate dielectrics. TiN, with a midgap work function of 4.65eV on SiO2, exhibits promising characteristics as metal gate on HfO2. In addition, encouraging results are presented for the ternary metal NiAlN, whereas classic Al electrodes are found unstable in conjunction with HfO2. [Copyright &y& Elsevier]

The fabrication of n-type multi-wire MOSFETs on SOI material with triple-gate structures is presented. The output and transfer characteristics of devices with a gate length of 70 nm and a MESA width of 22 nm demonstrate clearly the suppression of short channel effects (SCE). In addition, these triple-gate structures are compared with planar SOI devices of comparable dimensions. The influence of biasing the substrate (back gate) is analyzed and compared to simulation data. [Copyright &y& Elsevier]

Electrically variable shallow junction (EJ) MOSFETs with a channel length of 50 nm, source–drain distances between 150 nm and 9 μm, and different channel dopings have been systematically investigated by means of 2D device simulation. SOI EJ-MOSFETs with a highly doped channel show a subthreshold behavior similar to the comparable bulk version. By decreasing the source–drain distance down to 150 nm and lowering the channel doping the on-currents of EJ-MOSFETs can be increased by more than two orders of magnitude. [Copyright &y& Elsevier]