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Abstract: This paper reports on the integration of vertical nTunnel FETs (TFETs) with SiGe hetero-junction and analyzes the presence of trap-assisted tunneling impacting the device behavior. Temperature measurements are used to distinguish the band-to-band tunneling (BTBT) from the trap-assisted tunneling (TAT). It is shown that TAT degrades the onset characteristic and the subthreshold swing of the devices. TCAD simulations are in good agreement with experimental data for a germanium content up to 44%, when including non-local TAT model and properly tuning the model’s parameters. Simulations also suggest that boosting the BTBT component, for example by further bandgap decrease (Ge source), or by other means should be beneficial in lowering the impact of trap-assisted tunneling, provided that the material defectivity does not worsen. [Copyright &y& Elsevier]

Abstract: We report on the process integration of vertical silicon Tunnel FETs (TFETs) and analyze the impact of process and geometrical parameters on the device behavior. The gate–source overlap is shown to be a critical parameter, especially when the overlap is marginal. The temperature dependence also suggests that trap-assisted tunneling injection mechanism is at the origin of the degraded onset characteristic of the vertical TFET, likely due to a large interface trap density and that improvement in the passivation of the surface of the vertical nanowires should be beneficial. [Copyright &y& Elsevier]

Abstract: This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20nm wide fins are fabricated using 193nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300nm and the electrically active fin height is 40nm. [Copyright &y& Elsevier]

Abstract: We show the impact of process parameters on the electrical performance of complementary Multiple-Gate Tunnel Field Effect Transistors (MuGTFETs), implemented in a Multiple-Gate Field Effect Transistors (MuGFETs) technology compatible with standard CMOS processing. Firstly, we assess the impact of the gate oxide thickness on the tunneling performance. Secondly, we investigate the effect of the doping concentration and profile by implementing different doping conditions. Thirdly, three different annealing conditions are compared: spike anneal, sub-ms laser anneal and low temperature anneal for Solid Phase Epitaxy Regrowth (SPER). In case of SPER anneal a record drive current of 46μA/μm at V DD of −1.2V and I OFF of 5pA/μm for Si pTFETs is reported. The enhanced current is given by the position of the silicide at the n+side close to the gate. Silicide engineering opens a new opportunity to optimize tunnel devices. [Copyright &y& Elsevier]

Abstract: High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate FETs with narrow fins. Reduction of specific contact resistance by selective epitaxial growth of Si in heavily doped S/D regions of a multiple gate FET helps with achieving low S/D resistance. This paper addresses integration of low temperature selective epitaxial growth process into multiple gate FET processing. Our experimental results show more than 30% reduction in the parasitic S/D resistance for 16-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate NFETs with less than 20-nm wide fins. A follow up of this work with HfO2-TiN gate stack shows more than 20% improvement in the drive current at a constant I OFF for 40-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate FETs. [Copyright &y& Elsevier]

We study in this paper the epitaxial growth and electrical characterization of an n+In 0.5 Ga 0.5 As/p+GaAs 0.5 Sb 0.5 Esaki diode lattice matched to (001)-oriented InP substrate. First, the effects of molecular beam epitaxy growth temperature and group-V growth rates on the GaAs x Sb 1− x composition are characterized by means of X-ray diffraction (XRD). It is found that GaAs x Sb 1− x lattice constant is mainly determined by the Sb 4 incorporation rather than the As 4 one. After optimization, high quality In 0.54 Ga 0.46 As(Si)/GaAs 0.52 Sb 0.48 (Be) heterostructure is confirmed by XRD, Transmission electron microscope (TEM) and Secondary Ion Mass Spectroscopy (SIMS) profiles meeting requirements for sub-60 mV/dec operating devices. Esaki tunnel diodes are then fabricated to be used as a prediction of Band-To-Band Tunneling (BTBT) for Tunnel Field-Effect transistors (TFETs). The results are compared to previously reported n+/p+In 0.5 Ga 0.5 As homojunction diodes, showing a ×60 factor improvement of BTBT current density for the same electric field with an excellent average Peak-to-Valley Current Ratio (PVCR) of 14. [ABSTRACT FROM AUTHOR]

Abstract: The performance of nanoelectronic devices critically depends on the distribution of charge carriers inside such structures. High-vacuum scanning spreading resistance microscopy (HV-SSRM) has established as the method of choice for quantitative 2D-carrier mapping in nanoscale devices during the last decade. However, due to the 3D-nature of these nanoscale device architectures, dopant incorporation and dopant diffusion mechanisms can vary for any of the three dimensions, depending on the particular processes used. Therefore, mapping of carriers in three dimensions with high spatial resolution is inevitable to study and understand the distribution of active dopants in confined 3D-volumes and ultimately to support the process development of next generation devices. In this work, we present for the first time an approach to extend the capabilities of SSRM from an inherent 2D-carrier profiling technique towards a quantitative 3D-characterization technique based on the example of a nanowire (NW)-based heterojunction (SiGe–Si) tunneling transistor. In order to implement a 3D-methodology with a 2D-imaging technique, we acquired 2D-carrier concentration maps on successive cross-section planes through the device of interest. This was facilitated by arranging several devices in a staggered array, allowing to produce a series of cross-sections with incremental offset by a single cleave. A dedicated interpolation algorithm especially suited for structures with rotational symmetry like NWs was developed in order to reconstruct a 3D-carrier distribution map. The validity of the method was assessed by proving the absence of variations in carrier distribution in the third dimension, as expected for NWs etched into a blanket stack. [Copyright &y& Elsevier]

Abstract: This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, Gm max, and analog figures of merit, such as transconductance over drain current ratio, Gm /ID , output conductance, GD , Early voltage, V EA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data obtained on FinFETs. We show that the presence of negative charges at the gate edges while degrading the subthreshold behavior and analog figures of merit (especially for long-channel devices) can result in apparent improved control of short-channel effects and higher Gm max. The origin of such twofold impact of negative charges at the gate edges on the device behavior is also analyzed by 2-D device simulations and a simplified two-transistors model. [Copyright &y& Elsevier]

Abstract: At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 ]. In addition, their undoped channels allow a substantial reduction of the threshold voltage (V T) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width (W fin) and gate length (L g) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance (R SD) engineering become more challenging. In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial R SD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10nm. [Copyright &y& Elsevier]

Abstract: Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased V T statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32nm technology node on, planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET-based multi-gate devices for the 32nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed. [Copyright &y& Elsevier]

Abstract: This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110nm long channel achieve an intrinsic gain of 25dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body. [Copyright &y& Elsevier]

Abstract: In this work, we extend the modified shift and ratio method, originally used for extracting the effective channel length in standard short channel MOSFETs, to the extraction of the fin width in FINFET devices. Using devices with different fin widths, the electrical width of the devices can be extracted. The method is adapted in such a way that it takes into account the difference in mobility due to the different crystal orientation of the fin sidewalls and top surface, the width dependence of the threshold voltage and the influence of the increasing source/drain resistance for narrow fin devices. [Copyright &y& Elsevier]