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• The gate-induced drain leakage (GIDL) in stacked nanowire transistors for temperatures of operation between 300 K and 580 K is experimentally assessed for devices with different channel lengths and fin widths. • The temperature rise increases the current due to GIDL and its dependence on the device width. • For a fixed negative gate voltage the channel length reduction increases the GIDL current for nanowires independent of the temperature, except for devices suffering from threshold voltage roll-off due to short-channel effect. • Three-dimensional TCAD simulations showed that drain leakage is mainly composed of band-to-band tunneling rather than junction leakage, even at high temperatures. • The band-to-band generation rate intensity is larger in the bottom nanowire, with Ω-gate architecture than in the top GAA nanowire. • Band-to-band generation becomes higher as length is reduced and fin width is increased and is larger in the drain extension and gate overlap regions. • The temperature rise changes valence and conduction energy levels causing the reduction of the lateral distance between the two levels, favoring the transversal band-to-band tunneling. This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling. [ABSTRACT FROM AUTHOR]

• This work presents experimental results of the series resistance variability in junctionless and inversion-mode nanowire transistors. • Due to series resistance, drain-current variability is larger than Y-function variability both in junctionless and inversion mode nanowires. • The influence of source-drain series resistance is higher on drain-current variability for junctionless than inversion mode, presenting an increase of up to 50% depending on the width and channel length. • Results suggest that series resistance variation impacts junctionless more than inversion mode nanowire transistors. This work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors. [ABSTRACT FROM AUTHOR]

Electrical transport and resistance noise spectroscopy measurements are performed on individual, single crystalline Bi 2 S 3 nanowires in the field-effect geometry. The nanowires exhibit n-type conduction and device characteristics such as activation energy, ON/OFF ratio, and mobility are calculated over a temperature range of 120–320 K and at several bias values. The noise magnitude is measured between 0.01 and 5 Hz at several gate voltages as the device turns from it's OFF to ON state. The presence of mid-gap states which act as charge traps within the band gap can potentially explain the observed transport characteristics. Sulfur vacancies are the likely origin of these mid-gap states which makes Bi 2 S 3 nanowires appealing for defect engineering as a means to enhance its optoelectronic properties and also to better understand the important role of defects in nanoscale semiconductors. [ABSTRACT FROM AUTHOR]

This work presents the formation of intrinsic and dopant-segregated Schottky barrier nanowire transistors using microwave-annealed silicidation. To gain a sound understanding of applying the microwave annealing on fabricating metallic source/drain nanowire devices, three metals, nickel, ytterbium, and titanium, were utilized to form the Schottky barrier source/drain. Effects of microwave annealing on silicidation as well as segregation were intensively examined by comparing with those using rapid-thermal annealing. The drain current of ytterbium-based examples depend mildly on the applied microwave power from 200–400%, whereas the higher 300% or 400% power is most appropriate to optimize nickel-based nanowire transistors. The maximum 500% power is required on forming titanium silicidation for intrinsic or dopant-segregated nanowire devices. Relatively, temperature of 600 ℃ is required to form the nanowire source/drain with nickel or ytterbium, and temperature of 900 ℃ is needed for titanium-based devices. Experimental results show that the microwave annealing offers low-temperature processing against the rapid-thermal method to ensure favorable device characteristics, serving as a promising approach for 3D integration of CMOS technologies. [ABSTRACT FROM AUTHOR]

In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations 〈1 1 0〉 and 〈1 0 0〉 and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90° on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5 nm, 6 nm, 7 nm and 8 nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions. [ABSTRACT FROM AUTHOR]

The increase of hot carrier degradation with decreasing wire width in nanowire gate-all-around (GAA) MOSFETs has been investigated through experiment and device simulation. From the systematical analysis of measurement and simulation, it is found that the increase of device degradation in narrow devices is dominantly governed by the increased current density, the large lateral and vertical fields, and the increased interface state generation rather than by the reduced floating body effects. The more significant hot carrier degradation with decreasing wire width is likely to be proportional to the surface-to-volume ratio of nanowires. [ABSTRACT FROM AUTHOR]

Abstract: We report a numerical study of both donor- and acceptor doping impurity effects in the quantum transport of silicon nanowire metal-oxide-semiconductor (MOS) transistors. The code is based on a full three-dimensional (3D) real-space non-equilibrium green function (NEGF) formalism self-consistently coupled with the 3D Poisson equation. The general results show that the influence of an impurity strongly depends on its type. Indeed, an acceptor or a donor will create a repulsive or attractive potential, giving rise to tunneling effect or resonances, respectively. Our calculations analyze the impact on electron density, transmission coefficient and drain current (ID ) which undergoes variations up to 50%. This pinpoints the importance of intrinsic fluctuations due to doping in ultimate nano-transistors whose magnitude cannot be neglected in the next generations of integrated circuits. [Copyright &y& Elsevier]

In this paper, we present the fabrication and characterization of gate-all-around (GAA) junctionless (JL) poly-Si nanowire (NW) transistors with a dual-gated configuration, in which a sub-gate is placed over a shorter main-gate in order to control the NW potential for the offset regions between the main-gate and S/D regions. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. Inevitable misalignment of lithographic patterning for the main-gate structure leads to asymmetrical channel offsets between the main-gate to source pad and to drain pad, respectively. That is, the length of un-gated NW close to the source pad differs from that to the drain pad. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end. Such a trend become less profound as the sub-gate bias increases. • The fabrication of GAA JL poly-Si NW transistors with a dual-gated configuration. • The influence of asymmetric offsets on I D becomes less profound with increasing V sub-gate. • TCAD simulation is used to verify the mechanism of the experimental results. [ABSTRACT FROM AUTHOR]