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Abstract: Phase change memory (PCM) is the most performing non-volatile memory-technology alternative to FLASH. In order to design optimized cells, in term of geometry and materials, for present and future technological nodes, physics-based models for readout, programming and data retention are required. In this work, transport and phase-change modeling in PCM cell is reviewed and used to discuss (1) the programming-current reduction through geometry optimization, (2) the trade-off between programming current and readout resistance and (3) the program disturb phenomenon. In particular, scaling of PCM is extensively investigated, comparing the impact of isotropic and non-isotropic scaling on cell programming-current and program-disturb. Recent developments and open issues in PCM physical modeling are finally presented. [Copyright &y& Elsevier]

Abstract: Among the emerging non-volatile technologies, phase change memories (PCM) are the most attractive in terms of both performance and scalability perspectives. The paper reviews the physics underlying PCM operation, the scaling potentials of these devices and some options recently proposed for the cell structure. The paper also addresses the main challenges for the PCM to become fully competitive with standard Flash technology. [Copyright &y& Elsevier]

Abstract: Emerging phase-change memory (PCM) technology for non-volatile applications presents many potential advantages in terms of scalability, endurance and program/read speed. While several integration issues have still to be solved before achieving volume-production stage, the fundamental physics of chalcogenide switching and phase-change behaviour has still to be comprehensively understood. This paper provides an in-depth analysis of the switching and programming transient in PCM cells. It is shown that the cell parasitic capacitance can lead to a marked current overshoot in the programming transient. As evidenced by experiments, this overshoot is able to melt and quench the active material as in a reset operation. The parasitic reset results in a series distribution of crystalline and amorphous phases after program. The analysis of array cell capacitance instead indicates that no parasitic reset is to be expected, allowing for a localized crystallization during program, as previously obtained by numerical simulations. [Copyright &y& Elsevier]

This paper highlights that cycling-induced threshold-voltage instabilities in nanoscale NAND Flash technologies display a non-negligible dependence on the background pattern of the memory array during idle/bake periods. Experimental results clearly reveal, in fact, that instabilities in a (victim) cell do not depend only on its memory state, but also on the memory state of its first neighboring (aggressor) cells. The magnitude of this new cell-to-cell interference effect, moreover, appears to depend on the memory state of the victim cell, decreasing with the increase of its threshold-voltage level. From all of the gathered experimental evidence a physical picture explaining the phenomenon is provided, which is, finally, confirmed with the help of numerical simulations. [ABSTRACT FROM AUTHOR]

Abstract: This paper investigates the impact of lateral charge migration on the retention performance of charge-trap memories whose storage layer is not patterned self-aligned with the channel area of each cell. Experimental results on planar SONOS devices reveal an important contribution of lateral charge migration at 150°C and are used to calibrate a new numerical model accounting for both the vertical and the lateral charge loss from the silicon nitride. This new model was used to simulate 3D vertical SONOS devices, where multiple cells are stacked in a cylindrical structure and process constrains the adoption of a self-aligned charge storage layer. A string of three cells and two select transistors has been simulated, evaluating, for different channel length and temperatures, the impact on string operations of the charge migrating in the nitride located between different gates. [Copyright &y& Elsevier]

Abstract: In order to validate phase change memory (PCM) technology, the programming reliability, in terms of reading window between the programmed and erased state, must be guaranteed at array level with an error less then 1 part-per-billion. The reset distribution is significantly influenced by the quenching operation [Mantegazza D, Ielmini D, Pirovano A, Gleixner B, Lacaita A L, Varesi E, et al. Electrical characterization of anomalous cells in phase change memory arrays. IEDM Tech Dig 2006:53–56]. In this paper this phenomenon is explained in terms of PCM active material crystallization statistics. A significant spread in the crystallization times among PCM cells is detected both in the write-reset operation from the melted-amorphous state (quenching) and in the erase-set operation from the solid-amorphous state. At statistical level, a correlation between set at high and low temperatures and quenching behavior of cells is found, allowing to describe the programming distributions uniquely in terms of crystallization times statistics. [Copyright &y& Elsevier]

Abstract: We present results of 3D Monte Carlo simulation of nanocrystal memory cells, investigating the impact of edge and percolation effects on the achievable threshold voltage window. While edge effects reduce the performance for narrow cells, percolation can play a beneficial role for W scaling, but is critical when scaling L. To reduce edge effects, a structure with non-overlapped trenches is proposed and investigated, showing that it can improve the performance by about 20% in terms of . [Copyright &y& Elsevier]