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Organic cocrystals with charge-transfer (CT) properties are more competitive to tune the physicochemical properties. Mechanochemical preparation is the easiest way to prepare clean and green cocrystals among most common crystal engineer field. A new CT complex of trans- N-benzylideneaniline (NBA)-1,2,4,5-tetracyanobenzene (TCNB) cocrystal (NTC) is prepared by grinding the mixed powders. The NTC enhances the photoluminescence quantum yield (PLQY) from non-fluorescent NBA and intermolecular CT interactions between NBA and TCNB facilitate the two-photon excited fluorescence. Furthermore, the hydrolysis reaction of NBA and cocrystal-to-cocrystal transformation of TCNB-aniline complex realize large-range fluorescence color adjustment. • A new NTC cocrystal was prepared by a simple one-step mechanochemical grinding method. • NTC enhances the PLQY from non-fluorescent NBA, and shows two-photon-excited fluorescence (TPEF) property. • Hydrolysis reaction of NBA realizes cocrystal-to-crystal transformation and tunable emission colors. [ABSTRACT FROM AUTHOR]

Artificial intelligence algorithms play important roles in image classification to speech recognition, which contains enormous Boolean logic and multiplication operations. Traditional von Neumann architecture separates computing and storage units, which leads to "power walls" and "memory walls" problems. In-memory computing (IMC) is a promising method to solve these problems. In this work, we propose an IMC macro based on customed 9T-SRAM, which can be configured in memory, Boolean logic and multiply-and-accumulate (MAC) modes. The 9T-SRAM adopts read/write decoupled and a tail transistor structure, which enhances the read stability and reduces power consumption. With the bias rows, Boolean logic results are obtained from the differential voltages on two bitlines, reducing the peripheral circuit for reference voltage generation. Furthermore, the bias rows replace analog to digital converter (ADC) to binarize the MAC result, reducing the area overhead. In a 55 nm process, simulations manifest the 9T-SRAM shows enhanced read static noise margin, and the macro exhibits stable IMC operations and high energy-efficiency. [ABSTRACT FROM AUTHOR]

For low voltage CMOS static random access memory (SRAM) cells, the leakage current on bit-lines will slow down the reading operation and even lead to error reading. Herein we report a 4B4C circuit composed of 8T SRAM arrays, four bit-lines and four coupling capacitors to track and compensate the bit-line leakage current (BLLC). The assistant bit-lines are used to control the connection of capacitors. The coupling capacitors are used to compensate voltage losses caused by the BLLC, and improve the maximum tolerable current from primary bit-line. The timing diagram and output waveforms verify the compensatory effects of coupling capacitors. The 4B4C circuit shows fast reading operation and increases the maximum tolerable leakage current to 17.8 times compared with conventional circuit at FS process corner. The 4B4C circuit can keep 100% correct reading till 200 μA from Monte Carlo simulations. The 4B4C circuit enhances SRAM reading reliability and shows huge potential in very-large scale memory arrays. [ABSTRACT FROM AUTHOR]

Exciplex-based thermally activated delayed fluorescence (TADF) materials show long luminescence lifetimes and high quantum efficiency by converting the non-radiative triplets into the radiative singlets. Here, strong upconverted fluorescence from the amorphous thin films of TADF donor-acceptor (D-A) exciplexes is observed under near-infrared excitation. The spectroscopic studies demonstrate that the enhanced upconversion in exciplex emission combines a series of excited state processes including the two-photon absorption (TPA) of donors and the TADF of D-A pairs. The comparison between donor-only and D-A systems indicates that the upconversion is greatly facilitated by the energy harvesting mechanisms existing in the exciplex-based TADF materials. The results reveal the formation mechanism of exciplex excited-states following the two-photon excitation in D-A blends, and consequently the potentials of exciplex materials in nonlinear optics applications. Moreover, a maximum D-A distance of ~6.9 nm for two-photon excited exciplex formation is obtained. • A strategy for TADF exciplex-based two-photon-excited fluorescence was proposed. • Enhanced upconverted fluorescence was observed in films of D-A exciplex. • The mechanisms of enhanced upconverted fluorescence in TADF exciplex was explained. • A maximum D-A distance of ~6.9 nm for two-photon excited exciplex formation was obtained. [ABSTRACT FROM AUTHOR]

In the emerging field of Computing-in-Memory (CIM), this study introduces a 28-nm CMOS-based Static Random Access Memory (SRAM) CIM macro capable of various computational modes, potentially offering a solution to the Von Neumann bottleneck. Beyond traditional SRAM read and write operations, to enhance the flexibility of the CIM macro, a 9T cell is proposed for performing AND, OR, and XNOR operations; a new capacitive weighting module is introduced to reduce the area of conventional ladder capacitors; and a redundant array-assisted Analog-to-Digital Converter (ADC) is proposed to improve linearity during ADC quantization. The proposed architecture can achieve multi-bit multiplication and accumulation (MAC), OR accumulation (ORA), and XNOR accumulation (XNORA). Simulated using a 28-nm CMOS process, the architecture demonstrated a minor standard deviation in BL voltage of 16.27 mV at the SS process corner, as evidenced by Monte Carlo simulation. At the TT process corner, the energy expenditure for MAC, XNORA, and ORA operations was 5.76, 5.85, and 5.82 fJ/op, respectively. [ABSTRACT FROM AUTHOR]

Traditional von Neumann architecture, characterized by separate memory and processing units connected by a limited-capacity memory bus, faces challenges in handling tasks with high energy efficiency requirements. In contrast, the compute-in-memory (CIM) architecture offers a promising alternative, facilitating high parallelism in data processing while integrating storage functions, thereby significantly reducing memory access frequency and power consumption. This study presents a fully digital CIM macro featuring a novel self-write-back 12T cell. This bitcell is capable of performing Boolean logic operations and autonomously writing back results into the in-situ cell, thereby significantly improving energy efficiency.This can be used for binary logical operations between each pixel of two images without requiring additional storage area. A bidirectional read/write architectural design enables matrix transposition. This can achieve image rotation.Additionally, this novel 12T cell also offers the option to choose not to write back the results of logical operations, thereby providing the flexibility and configurability for image processing. Combined with an adder tree, it enables multiply-and-accumulate (MAC) operation for convolutional neural networks(CNNs). This can be used for feature extraction. We propose an 18T full adder structure with lower power-delay product than current state-of-the-art full adders, which is advantageous for improving the synthesis performance of the adder tree.The CIM macro supports a 4-bit × 4-bit MAC operation. The proposed CIM macro, designed and simulated using a 28 nm CMOS process with a 16 Kb static random access memory (SRAM), demonstrates promising results. At VDD = 0.9 V, the logic operation energy consumption is 1.35 fJ/bit with an energy efficiency of 740TOPS/W, and MAC operation energy consumption is 15.91 fJ/bit with an energy efficiency of 62.85 TOPS/W. [ABSTRACT FROM AUTHOR]

Resistive random access memory (RRAM) is viewed as the next-generation memory model, surpassing the constraints of traditional random access memory. Given its non-volatile nature, which lessens static power consumption, RRAM boasts significant computing-in-memory (CIM) potential. We herein present a four-transistor/two-resistor cross-coupling structure based on RRAM. In this structure, two RRAMs are situated in opposite directions, a configuration referred to as reverse coding. This structure provides the flexibility and reconfigurability to adjust the RRAM connections, facilitating various CIM operations in fewer cycles. A full adder design was developed and its feasibility was validated through simulations. Monte Carlo analysis ensures the accuracy of logic operations, even while encountering significant resistance fluctuations. This approach effectively mitigates the resistance crossover observed in existing RRAM CIMs. Compared with previous methodologies, the proposed structure achieves greater robustness with fewer cycle counts and RRAM numbers, The comparison of our approach with state-of-the-art Boolean logic circuits for RRAM architecture shows significant improvement in both delay (1.4–4.1 ×) and the number of RRAM (1.2–6.6 ×). [ABSTRACT FROM AUTHOR]

The proposal of compute-in-memory (CIM) is a breakthrough for the traditional von Neumann architecture to achieve efficient computing research. This architecture has unique advantages in the computing field thanks to supporting multi-line computing and without data transmission between processor and memory. In this paper, an in-memory computing structure based on 9T SRAM unit is proposed, which can both operate on memory and computing mode. Compared with the previous works, thanks to the redundant units, the computational structure can directly complete XNOR operations and storage of the whole SRAM array in only one cycle, without the need of extra digital logic circuits (such as AND, OR circuits), which can significantly improve the parallelism of the computation. Meanwhile, the architecture can map the XNOR logical operation into the binary multiplication, and then add up the one-bit multiplication results through the addition tree, thus realizing the binary convolution calculation. A 64-bit × 64-bit (4 Kb) SRAM array with the proposed scheme is designed and simulated in 55 nm CMOS technology. Simulation results show excellent stability and write yields in SRAM memory mode at an operating frequency of 200 MHz. In computing mode, the SRAM array power consumption for logical operation is 52.68 fJ/bit at 1.2 V supply voltage. At a minimum supply voltage of 0.8 V, the power consumption is only 5.58 fJ/bit, with an energy efficiency 179.21 TOPS/W. [ABSTRACT FROM AUTHOR]

This paper proposed a radiation-hardened memory cell (RHMC12T) by polar design for space applications. The proposed cell has the following advantages: (1) it can tolerate all single-node upset and partial double-node upset based on combining radiation hardened by polar design technology together with reasonable layout topology; (2) comparing with the state-of-the-art radiation hardened SRAM cells, simulation results show the proposed RHMC12T cell has lower write access time, higher wordline write trip voltage, larger static noise margin, and larger critical charge. And Monte Carlo simulation results have shown that RHMC12T has good robustness; (3) electrical quality metric is widely used to evaluate the overall performance of SRAM cells. And RHMC12T has the largest EQM compared with the state-of-the-art radiation hardened SRAM cells, which suggests the proposed RHMC12T exhibits good circuit performance (including write/read access time, static noise margin et al.) as well as good radiation resistance performance with sacrificing a large area overhead. [ABSTRACT FROM AUTHOR]