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Curved-line folding, the act of folding paper along a pattern of curved lines to obtain a 3D shape, is an interesting starting-point for the design of innovative pliable structures. There exists a kinematic connection between two surfaces linked through a curved crease that can be used to generate a folding motion. However, due to the interdependency of geometry, forces and material properties the design of pliable structures based on curved-line folding is very complex. To facilitate the design process, adequate computational modelling methods are essential. This paper presents two ways of modelling: a geometric modelling method based on discretisation of the crease pattern and a method based on Finite Element Analysis (FEA). The proposed methods are validated by means of a case study in which a physical model is compared to digital ones. It can be concluded that the method based on FEA corresponds very well with the physical model, proving its potential. The accuracy of the geometric modelling is improved by the introduction of a set of guidelines based on the direction of the principal bending moments in the pliable structure. Furthermore, the case study exposes how the material-dependent behaviour of pliable structures increases the complexity of the design and should certainly be part of future research. [ABSTRACT FROM AUTHOR]

Transistor scaling has continued to yield significant performance gains. The general-purpose architecture will not suffice in this dark silicon era with the big data boom and growing emphasis on performance. Artificial neural networks and deep learning are sophisticated computing activities that cannot be optimally executed (accuracy, performance, and energy) on today's general-purpose computer architecture. The demand for domain-specific computer architectures is increasing. This paper suggests and evaluates a highly reconfigurable domain-specific design for deep learning and artificial neural networks to overcome these problems. An FPGA-based soft-core processor for deep neural network (DNN) acceleration is suggested in this paper. Using a combination of unicast and multicast for collective operations, the proposed FPGA accelerates the performance of the deep learning network. The suggested design outperforms the current general-purpose processor by 6.6 times, according to a thorough examination and comparison. The existing architecture's level of accuracy is retained. [ABSTRACT FROM AUTHOR]

RISC-V is a computer architecture that has recently attracted considerable attention due to its advantageous qualities: it is an open instruction set, based on reduced and simple instructions. For this reason it has become an appealing choice for a wide range of computing applications and has positioned it as a disruptive force in a wide variety of fields, including those that involve the development of safety–critical software, as in the space sector. The ability to evaluate the activities performed within a processor is of paramount importance in this type of systems to ensure the fulfillment of the requirements during space missions. The monitoring of these events inside the processor is managed by an instrument called Hardware Performance Monitor (HPM). This work shows the implementation of the Sscofpmf extension of the HPM compliant to the RISC-V privileged specification. The paper details the redesign of the existing performance counters from a RISC-V baseline version previously implemented. A comparison between the two versions of both resource utilization data and power consumption is also provided. As expected, the Sscofpmf extension version has a higher resource utilization. Nevertheless, the paper shows that the additional functionalities included in the system have been validated without any changes in the processor clock frequency, so the extension does not introduce any performance overhead. [ABSTRACT FROM AUTHOR]

Simultaneous Multithreading (SMT) allows for a processor to concurrently execute multiple independent threads while sharing certain data path components to optimize resource waste. Speculative execution allows for these processors to take advantage of Instruction-Level Parallelism but the penalty for a miss speculation includes the wasting of resources amongst these shared resources where clock cycles are wasted at a time. In this paper we show that an average of 13 % of instructions are flushed as a result of incorrect predictions. These flushed out instructions could have potentially taken up shared resources which other non-speculative threads could have used. This paper proposes a technique that can dynamically adjust how many speculative instructions a thread can rename and decode aiming to diminish the waste of the shared resources. Our simulation results show, with the proposed technique, that the average flushed out instruction rate is reduced by 23 % and average throughput is improved by 13 %. [ABSTRACT FROM AUTHOR]

The security of device drivers should be verified by system testing. This paper presents QDFaultInjector, a fault injection tool that can work on three architectures (x86 64, AArch64 and MIPS64) to test Linux kernel modules (including device drivers) at runtime. Firstly, overall framework of QDFaultInjector is introduced in this paper, along with monitoring of LKM operation based on notifier chain and callback function and flexible mechanisms of retriggering faults and automatic recovering based on debugfs pseudo file system. Moreover, it is explained in detail how instruction replacement is implemented for fault injection on different architectures, because it is architecture-specific, i.e., it is related to the machine codes and the formats of instructions. Thereafter, a char device driver is used to verify every function of QDFaultInjector on the above architectures respectively and the results show that QDFaultInjector can inject faults successfully and effectively. In addition, a few of realistic network card drivers such as hns3 and pcnet32 are used to do the tests and some events of system breakdown occur when some faults that have been injected into device drivers by QDFaultInjector are triggered. That means that some potential problems are existed in the corresponding device drivers, which ought to be revised and perfected. Finally, QDFaultInjector is compared with some other fault injection tools and a conclusion is drawn that it supports more computer architectures and it is more flexible for testing operations. [ABSTRACT FROM AUTHOR]

Turing (1937) introduces a model of code that is followed by other pioneers of computing machines (such as Flowers 1983, Eckert, Mauchly, Brainerd 1945 and others). One of them is John von Neumann, who defines the concept of optimal code in the context of the conception of EDVAC. He later uses it to build on in his theoretical considerations of the universal constructor (von Neumann 1966). Von Neumann (1963) further presents one of the first neural network models, in relation to the work of McCulloch and Pitts (1943), for both theoretical purposes (von Neumann probe) and practical applications (computer architecture of EDVAC). The aim of this paper is (1) to describe the differences between Turingʼs and von Neumannʼs conceptualizations of code and the mechanical computing model. Between von Neumann's abstract technical conception (von Neumann 1963 and 1966) and Turingʼs more concrete biochemical conception (Turing 1952). Furthermore, (2) we want to answer the question why these influential models of mechanisms (predominantly in computer science) have so far been ignored by philosophers of the new mechanism (Machamer, Darden, Craver 2000, Glennan 2017). We will show that these classical models of machines are not only compatible with the new mechanism, but moreover complement it, since they represent a completely separate type of model of mechanism, alongside producing, maintaining and underlying (Zámečník 2021). The final (3) and main goal of our paper will be an attempt to relate von Neumannʼs and Turingʼs notion of mechanism to Barbieriʼs notion of extended mechanism (Barbieri 2015). [ABSTRACT FROM AUTHOR]

Highlights • A new multi-agent dynamic system MADS architecture for the complex computer vision tasks. • An adaption of the proposed architecture to online multi-face tracking in video sequences. • A logical representation model of relations and mental attitudes of agents involved in the MADS. • The integration of two cognitively different type of agents for specific problem solving. • The integration of state-of-the-art methods for face detection and tracking with BDI agents. Abstract The paper presents a new architecture framework in the field of expert and intelligent systems which is based on four paradigms: a novel multi-agent dynamic system architecture (MADS), an extended Belief Desire Intention (EBDI) agent community, autonomy-oriented entities (AOEs), and deep learning concepts. The main impact of the proposed framework is a new approach, or even a new way of thinking, which enables integration of the concepts of deep learning, a conventional approach to solving the domain problem, cognitive agents with mental attitudes, and concepts of nature-inspired computing. All these allow the effective use of the framework in the field of intelligent and expert systems. The significance of the framework lies in its flexibility and adaptability based on the formal logical description of EBDI agents, the definition of the behaviour of AOEs, the use of classical modules for domain problem solving, and modules based on deep-learning concepts. We believe that the example of the adaptation of the proposed architecture framework to robust multi-face tracking illustrates the significance of the proposed framework. In this paper, MADS is adapted to the first two stages of a face de-identification pipeline: robust face detection and multi-face tracking. The proposed architecture of MADS has a two-level hierarchical organization. At the first level there is a manager designed as an Extended Belief Desire Intention (mEBDI) agent. The extension of a manager BDI agent consists of a convolutional neural network-based face detector, a set of autonomous-oriented entities for the elimination of false positive face detections, and a trajectory memory. At the second level, there are many tracking agents (trEBDIs) which consist of a basic BDI agent extended with a face tracker based on position and scale correlation filters, a visual appearance memory, and a trajectory memory. The mEBDI and trEBDI agents are defined by the modal logic and are described at the implementation level. The proposed architecture for a robust multi-face tracking system was tested on a subset of YouTube music videos. The qualitative results, as well as the preliminary quantitative results expressed by the standard testing metrics, demonstrate the effective adaptation of the proposed multi-agent dynamic architecture to a robust multi-face tracking system. [ABSTRACT FROM AUTHOR]

The performance of software running on parallel or distributed architectures can be severely affected by the location of data. In shared memory multicore architectures, data movement between caches and main memory is driven by data accesses from tasks executing in parallel on different cores and by a protocol to ensure cache coherence. This paper integrates cache coherence in a formal model of data access, to capture such data movement from an application perspective. We develop an executable model which captures cache coherent data movement between different cache levels and main memory, for software described by task-level data access patterns. The proposed model is generic in the number of cache levels and cores, and abstracts from the concrete communication medium. We show that the model guarantees expected correctness properties for cache coherence, in particular data consistency. This paper further presents a proof-of-concept implementation of the proposed model in rewriting logic, which allows different choices for the underlying hardware architecture of dynamically created parallel data access patterns to be specified and compared at the modelling level. • A formal, operational model of data access in multicore architectures with multilevel caches. • Correctness properties of the formal model, expressed as invariants over an arbitrary number of cores and caches. • A proof-of-concept implementation of the model to compare executions based on penalties, an abstract performance indicator. [ABSTRACT FROM AUTHOR]

Abstract This study looks at the growth of eExams in five countries. An eExam is defined as 'a timed, supervised, summative assessment conducted using each candidate's own computer running a standardised operating system' (eExam, 2017), but local interpretations varied significantly. The literature revealed five main areas for the study: the scale of eExam adoption; assessment integrity (student cheating/security/reliability); eExam accessibility for students with disabilities; eExam architecture and affordances for assessing higher order thinking; and inter-sectoral relationships between universities and schools concerning eExam assessment environments. The methodology was qualitative and interpretist, using the constant comparison method from grounded theory for analysis (Corbin & Strauss, 1990, p. 9). Data were collected through interviews with 17 key individuals and from observations at sites which were purposively identified from the literature as diverse in eExam experience. The results provided a thick and robust description of practical eExam implementation. Adoption scales varied from less than 1% to 40% of examinations. Assessment integrity shared common concerns with pen-on-paper exams, and had some additional features, but were overall no more or less secure. eExams offered access to students with disabilities. The relationship between eExam architectures, affordances and assessment of higher order thinking was complex and contested, closely linked with perceived barriers and enablers. The quality of inter-sectoral relationships with respect to eExams was found to be generally poor. Academic workload reduction was a major enabler of eExams, and the policy drivers for curriculum transformation through improved affordances poorly articulated. Hurdles included lack of prior student experience of eExams. A clear enabler was the national adoption of a pathway to replacing pen-on-paper exams with eExams. Highlights • Provides a rich description of eExams in schools and universities in five countries at a very early stage of adoption. • Identifies enablers and hurdles for the expansion of eExams. • Describes eExam adoption scales, assessment integrity, accessibility, affordances and inter-sectoral relationships. • Reveals tension between the administrative conveniences and pedagogical affordances of eExams. • Shows there are insufficient data on whether curricula being transformed by the adoption of eExams. [ABSTRACT FROM AUTHOR]

Abstract Non-negative tensor factorization (NTF) algorithm is an emerging method for high-dimensional data analysis, which is applied in many fields such as computer vision, and bioinformatics. This paper presents an effective method to accelerate NTF computations and proposes a corresponding hardware architecture, which consists of multiple processing units. The decomposed factors are calculated by using shared intermediate results. By using the proposed method, NTF can be implemented in parallel and hardware resources can be saved by sharing. In this paper, we evaluate the proposed architecture on Xilinx Virtex-6 FPGA XC6VLX760T and apply it into 2 applications, i.e. video background estimation and facial images processing. The experimental results show that the proposed hardware architecture achieves over 80 times faster than CPU implementation of NTF. Compared with the implementations on GPGPU, the proposed architecture achieves nearly the same speedup. While the strategy in this paper is applied to GPU platforms, the execution time can be reduced by a half, due to the computational sharing in this paper. [ABSTRACT FROM AUTHOR]

Highlights • Proposal of integration of OPC UA with REST architecture. • Definition of a web application-based platform able to map OPC UA services to RESTful web services and vice versa. • Definition of RESTful web services and related mapping algorithms to offer OPC UA data to common users on the web. • Implementation of the proposed platform. The source code is available on Github at the address. https://github.com/OPCUAUniCT/OPCUAWebPlatformUniCT. Abstract The so-called fourth industrial revolution features the application of modern Information & Communication Technology (ICT) concepts and technologies in industrial contexts to create more flexible and innovative products and services leading to new business models and added value. The emerging Industrial Internet of Things (IIoT) is one of the main results of this revolution. One of the most known and adopted communication protocol in the context of the fourth industrial revolution is OPC UA (IEC 62541). Although this standard already combines features coming from both industrial and ICT contexts, current literature presents several approaches aimed to introduce ICT enhancements into OPC UA in order to further improve its usability in industrial environments. Some of these approaches are based on the proposal to make OPC UA RESTful, due to many advantages of RESTful services in industrial settings. OPC UA is based on a client/server architecture and adopts an information model at the server side, whose access from the client side requires knowledge of a data model, whose structure is sometimes complex, creating some difficulties for a resource-constrained device acting as client. The paper proposes the definition of a web platform able to offer access to OPC UA servers through a REST architecture. The approach presented in the paper differs from other existing solutions, mainly because it allows to realise a lightweight OPC UA RESTful interface reducing the complexity of the basic knowledge to be held by a generic user of the platform. For this reason, the solution presented allows enhancement of OPC UA interoperability towards resource-constrained devices. The web platform has been implemented and the relevant code is available on GitHub. [ABSTRACT FROM AUTHOR]

Highlights • We attempted to replicate the results of Hohnerbach on a GPU-enabled cluster. We found using CPU tests of accuracy that the optimization is still quite accurate, though there may be a decline in accuracy of the single and mixed precision versions at large timesteps. However, this decline is quite small and though a trend is present, we replicate the order of accuracy produced in the original paper. • When examining performance differences using GPUs, we found significant performance increases due to our V100 GPUs. We found similar relative performance in the various precision and optimization cases for GPU offloading. As a result, we were able to replicate this outcome • On the scale of a many CPU core node, we test scaling a 48-core Skylake node and find a poorer scaling than that found in Hohnerbach across multiple nodes. However, we could not directly compare these cases, as the scaling measurements across nodes in Hohnerbach were performed using offloading to Xeon Phi co-processors. Abstract This paper satisfies the reproducibility challenge of the Student Cluster Competition at SC17. 1 1 http://www.studentclustercompetition.us. We attempt to reproduce the results of a vectorized code for the Tersoff multi-body potential kernel of the molecular dynamics code Large-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS). In addition, we outline a series of performance measurements across a number of different processing architectures. We investigated accuracy, optimization, performance, and scaling with our Intel CPU and NVIDIA GPU based cluster. [ABSTRACT FROM AUTHOR]

Abstract Emotions play an important role in human cognition and therefore need to be present in the Common Model of Cognition. In this paper, the emotion working group focuses on functional aspects of emotions and describes what we believe are the points of interactions with the Common Model of Cognition. The present paper should not be viewed as a consensus of the group but rather as a first attempt to extract common and divergent aspects of different models of emotions and how they relate to the Common Model of Cognition. [ABSTRACT FROM AUTHOR]

Abstract A Common Model of Cognition needs to be open so as to encompass a broad range of approaches and provide a firm fundament to which researchers who study one particular aspect of cognition at more detail can refer. It should also be open to incorporate new findings even, or in particular, if they come from an unconventional angle. A recent cognitive systems experiment has surprisingly shown that there is a fundamental link between logic and analogous representations. This paper discusses a field of functionality called here the Canvas, comprising or overlapping what is called in other models the Visual Buffer, the Visuospatial Sketchpad, the Spatial Visual System, or Imagery, leveraging this recent result. The paper suggests that a module like the Canvas is a fundamental component for any model of cognition and of crucial importance to understanding the origins of higher cognitive abilities, such as language or geometry. The paper also demonstrates, how a fine-level research result benefits from the Common Model as a common context within which fine-level research can be embedded, relieving the author from having to provide a full cognitive architecture beyond the aspect studied. [ABSTRACT FROM AUTHOR]

Abstract The paper considers the well known cognition emotion primacy debate between Zajonc and Lazarus in the period 1980-1982. The paper also considers the less known contribution to that debate, given in the same time, in 1981, by an Artificial Intelligence system, the Crossbar Adaptive Array (CAA) artificial neural network. The CAA system was the first artificial neural network that implemented cognitive processing together with emotion processing. While Zajonc proposed that emotion is computed first, and Lazarus proposed that cognition is computed first, the CAA architecture suggested that both emotion and cognition are computed simultaneously. This paper reviews the cognition-emotion primacy problem stated by Zajonc and Lazarus in 1980-82, and also reviews the 1981-82 CAA solution of that problem. [ABSTRACT FROM AUTHOR]

Energy efficiency has become one the most important factors in today's processing platforms. Coarse-grained reconfigurable architectures (CGRAs) have turned out to perform well in this area. In this paper, we have proposed two methods to enhance their energy efficiency. The first method decreases the power consumption of a CGRA by reducing the number of occurring transitions of the context switching process. The second one decreases the energy consumption of a CGRA through volume shrinkage of its context memory. Our results show up to 83% of the context memory energy can be reduced by using our proposed method. In addition, a high level instruction-set simulator for CGRA has been presented in this paper. [ABSTRACT FROM AUTHOR]

A paper of SC ’16 entitled “ The Vectorization of the Tersoff Multi-Body Potential: An Exercise in Performance Portability ” Höhnerbach et al. (2016) [1] implemented reduced precision calculation and cross-platform vectorization for Tersoff potential, which the authors claimed as accurate, efficient, scalable and portable. In this report, we focus on recently released computing architectures, Intel Skylake and NVIDIA Volta, to present our results and compare them with the Tersoff paper. With new input provided by Porter et al. (1997) [2], we run the given testcases on our cluster and obtain results that not consistent with the performance improvements and scalability claimed in the original publication. Deeper analysis demonstrate that it is the communication bottleneck caused by special characteristics of the new input data that limit the reproducibility. [ABSTRACT FROM AUTHOR]

In a superscalar processor, instructions of various types flow through an execution pipeline, traversing hardware resources which are mostly shared among many different instruction types. A notable exception to shared pipeline resources is the collection of functional units, the hardware that performs specific computations. In a trade-off of cost versus performance, a pipeline designer must decide how many of each type of functional unit to place in a processor’s pipeline. In this paper, we model a superscalar processor’s issue queue and functional units as a novel queuing network. We treat the issue queue as a finite-sized waiting area and the functional units as servers. In addition to common queuing problems, customers of the network share the queue but wait for specific servers to become ready (e.g., addition instructions wait for adders). Furthermore, the customers in this queue are not necessary ready for service, since instructions may be waiting for operands. In this paper we model a novel queuing network that provides a solution to the expected queue length of each type of instruction. This network and its solution can also be generalized to other problems, notably other resource-allocation issues that arise in superscalar pipelines. [ABSTRACT FROM AUTHOR]

Quality is one of the most vital aspects of a construction project, and inspection is the most important task in construction quality management. Despite the application of advanced information technologies, the omission of check items and in-efficiency of entering inspection results from paper-based inspection records into computers and collaboration among the construction stakeholders remain to be major problems. This paper proposes an approach to make the process of construction quality management more effective and collaborative by developing a system based on the integrated application of building information modeling (BIM) and indoor positioning technology. First, the system requirements of the collaboration platform are analyzed based on the standards for construction quality inspection in China, the technologies to be used for its implementation are justified, and a process model for the collaboration of multiple stakeholders is established. Next, the system architecture is developed, and the algorithm for generating inspection tasks and the technique for integrating with indoor positioning technology are formulated. Finally, the implementation of a prototype system is presented, and the effectiveness and efficiency of the approach for construction quality management are verified by using the system in an on-site test. [ABSTRACT FROM AUTHOR]

Nowadays, satellites are becoming increasingly software dependent. Satellite Flight Software (FSW), that is to say, the application software running on the satellite main On-Board Computer (OBC), plays a relevant role in implementing complex space mission requirements. In this paper, we examine relevant technical approaches and programmatic strategies adopted for the development of the Meteosat Third Generation Satellite (MTG) FSW. To begin with, we present its layered model-based architecture, and the means for ensuring a robust and reliable interaction among the FSW components. Then, we focus on the selection of an effective software development life cycle model. In particular, by combining plan-driven and agile approaches, we can fulfill the need of having preliminary SW versions. They can be used for the elicitation of complex system-level requirements as well as for the initial satellite integration and testing activities. Another important aspect can be identified in the testing activities. Indeed, very demanding quality requirements have to be fulfilled in satellite SW applications. This manuscript proposes a test automation framework, which uses an XML-based test procedure language independent of the underlying test environment. Finally, a short overview of the MTG FSW sizing and timing budgets concludes the paper. [ABSTRACT FROM AUTHOR]

Optical Packet Switched (OPS) technology is under study as a promising solution for addressing the rapid growth of network-intensive applications having different Quality of Service (QoS) requirements. By employing Optical Circuit Switched (OCS) networks, an optimized Packet Loss Ratio (PLR), delay and Packet Delay Variation (PDV) performance can be obtained. It is, however, very demanding to offer a QoS comparable to OCS network through the OPS network in order to support a significant and growing number of applications. Thus, moving from OCS to OPS network, QoS is a critical issue. Hence, this paper analyzes the QoS requirements of network-intensive applications and services. Moreover, the paper derived an expression for performance metrics of a single OPS switch and ring OPS network. It is found that the International Telecommunication Union - Telecommunication (ITU-T) classification is extended with the new requirements of applications and services. For example, the upper bound delay, PDV and PLR of video streaming requires (100 ms, 400 ms), 50 ms and 1 E − 05 respectively. In this work, these values are improved as delay within 10 ms, PDV in micro seconds and PLR of 1 E − 07 at full load. It is also shown that a Fixed Delay Line (FDL) has to be considered when low PLR is required and when PDV and delay are not critical issues. [ABSTRACT FROM AUTHOR]

Various methods have been developed for automated and semi-automated architecture generation in the computer aided ship design processes. The question remains as to how this can speed up the design process without losing the requirement elucidation intent for concept phase. This paper presents a novel approach with a software toolset to develop design and analysis approaches to early stage ship design and provide a sketching tool. This was done by enhancing the user interface and experience of the UCL Network Block Approach to achieve a "thinking sketch" in a way that is "quick" and "fluid" enough to promote inventive and creative sketching comparable to hand sketching. The UCL Network Block Approach draws on the UCL Design Building Block (DBB) approach and uses network methods applied to the synthesis of distributed ship service systems (DS3) and Computer Aided Ship Design (CASD) to expand DS3 definition in early stage ship design. The UCL originated inside-out/DBB approach to sketch driven synthesis has been made translatable to both DBB ship descriptions and ensuring early stage naval architectural "balance". The proposed approach has been used for the first time successfully to not only carry out a rapid sketching exercise for a naval ship design but also enable quick preliminary analysis of a set of DS3 networks. • The proposed approach enabled rapid sketching exercises and analysis of ship systems in a concept warship design study. • Sketching directly on the computer gave advantages and enabled a quick system network analysis in early stage of ship design. • The proposed approach could be applied to any capable ship design software that can facilitate its philosophy. [ABSTRACT FROM AUTHOR]

The Personal Cloud paradigm has emerged as a solution that allows individuals to manage under their control the collection, usage and sharing of their data. However, by regaining the full control over their data, the users also inherit the burden of protecting it against all forms of attacks and abusive usages. The Secure Personal Cloud architecture relieves the individual from this security task by employing a secure token (i.e., a tamper-resistant hardware device) to control all the sensitive information (e.g., encryption keys, metadata, indexes) and operations (e.g., authentication, data encryption/decryption, access control, and query processing). However, secure tokens are usually equipped with extremely low RAM but have significant Flash storage capacity (Gigabytes), which raises important barriers for embedded data management. This paper presents a new embedded search engine specifically designed for secure tokens, which applies to the important use-case of managing and securing documents in the Personal Cloud context. Conventional search engines privilege either insertion or query scalability but cannot meet both requirements at the same time. Moreover, very few solutions support data deletions and updates in this context. In this paper, we introduce three design principles, namely Write-Once Partitioning, Linear Pipelining and Background Linear Merging, and show how they can be combined to produce an embedded search engine matching the hardware constraints of secure tokens and reconciling high insert/delete/update rate and query scalability. Our experimental results, obtained with a prototype running on a representative hardware platform, demonstrate the scalability of the approach on large datasets and its superiority compared to state of the art methods. Finally, we also discuss the integration of our solution in another important real use-case related to performing information retrieval in smart objects. [ABSTRACT FROM AUTHOR]

Multi-core mixed-criticality systems are complex solutions that provide benefits regarding lower power consumption, size, weight and cost and better performance and scalability, compared with single-core architectures. However, these systems where virtualization mechanisms such as hypervisors are used for integrating functionalities with different criticality levels into the same hardware platform and where on-chip and off-chip communication systems are implemented for communicating, imply certification challenges due to their complexity. Those challenges to certification are supported by the fact that today’s safety-related standard focus on single computing systems where spatial and temporal interferences are quite probable. Multi-core architectures enable sharing resources (e.g., cache memory, I/Os) between more than one processor at the same time, facilitating the appearance of interferences which may hinder the achievement of the spatial and temporal independences. This paper analyses the certification challenges in mixed-criticality systems and identifies some reusable generic solutions to overcome those challenges. The solutions presented in this paper are integrated into a safety wind turbine system that follows the design style introduced in European project DREAMS. [ABSTRACT FROM AUTHOR]

This paper presents the biologically inspired approach to time series forecasting area. We consider the most important characteristics of modular architectures of neural networks and their advantages under traditional monolithic neural networks. The main idea of this paper is take answer - why modular neural networks have so high performance in many tasks. In addition, we present few examples of modular approaches, which can be applicable for time series forecasting problem. Also we presenting forecasting system which now developing. [ABSTRACT FROM AUTHOR]

Chip Multiprocessors (CMP) have emerged during last decades as a very attractive solution in using the ever-increasing on-chip transistor count. However, classical parallelization techniques failed to fully exploit parallelization from existing sequential applications due to false data dependencies. This paper focuses on the Thread-level Speculation (TLS) technique, an alternative way to exploit the transistor budget in a CMP. With TLS, even possibly data dependent threads can run in parallel as long as the semantics of the sequential execution is preserved. A special hardware support monitors the actual data dependencies between threads at run time and, if they are violated, misspeculation effects are undone usually through replay. This kind of system is known as speculative CMP. However, the TLS mechanism requires complex protocols that integrate cache coherence and speculation to maintain program order among multiple versions of data. Current TLS protocol evaluations are usually inadequate because they are not done low-level enough. A realistic evaluation of speculative CMPs requires either to be performed on a real hardware or very detailed cycle-accurate simulator models. In this paper we are particularly focused on a low-level evaluation of the write-invalidate TLS protocol Speculation Integrated with Snoopy Coherence (SISC) protocol proposed in [1] . This evaluation relies on cycle-level simulation environment with detailed cycle-level cache memories, cache controller and system bus. On top of this, a speculative four core architecture is simulated and three new modules (Scheduler, Squash Arbiter and Supplier Arbiter) are provided to support low-level implementation of the SISC protocol. The overall cost of the SISC protocol is evaluated by means of CACTI tool for the three different domains: the access latency cost, the area cost, and the power cost. The evaluation goal was to keep the cache access time to remain below cycle latency as well as the area and power overheads below an acceptable budget overhead. The SISC protocol has been compared against regular MESI-based architecture in both 32-bit and 64-bit versions. We kept the cache access time below the cycle latency, and we managed to keep both data cache area and static power overheads respectively below 32% and 35%. [ABSTRACT FROM AUTHOR]

Multi-core processors support all modern electronic devices nowadays. However, power management is one of the most critical issues in the design of today’s microprocessors. The goal of power management is to maximize performance within a given power budget. Power management techniques must balance between the demanding needs for higher performance/throughput and the impact of aggressive power consumption and negative thermal effects. Many techniques have been proposed in this area, and some of them have been implemented such as the well-known DVFS technique which is used in nearly all modern microprocessors. This paper explores the concepts of multi-core, trending research areas in the field of multi-core processors and then concentrates on power management issues in multi-core architectures. The main objective of this paper is to survey and discuss the current power management techniques. Moreover, it proposes a new technique for power management in multi-core processors based on that survey. [ABSTRACT FROM AUTHOR]

To compact the architecture of extreme learning machine (ELM), two incremental learning algorithms are proposed in this paper. The previous incremental learning algorithms for ELM recruit hidden nodes randomly, which is equivalent to implementing a random selection from a candidate set of infinite size. Hence, it is impossible to recruit good hidden nodes, and thus it usually requires more hidden nodes than traditional neural networks to achieve matched performance. To improve the quality of the hidden nodes recruited, an incremental learning algorithm for ELM is presented based on Gram--Schmidt process (GSI-ELM), which recruits the best hidden node from a random subset of fixed size via defining an evaluating criterion at each learning step. However, the “nesting effect” exists in the GSI-ELM, that is to say, the hidden nodes once recruited by GSI-ELM can not be later discarded. To treat this “nesting problem”, the improved GSI-ELM (IGSI-ELM) is generated with an elimination mechanism. At each learning step IGSI-ELM eliminates the worst hidden node from the already-recruited group if it is not the newly-recruited one. Finally, to verify the efficacy and feasibility of the proposed algorithms, i.e. GSI-ELM and IGSI-ELM, in this paper, experiments on regression and classification benchmark data sets are investigated. [ABSTRACT FROM AUTHOR]

Although technology advancement can pack more and more physical registers in processors, the numbers of architectural registers defined by the instruction set architectures (ISAs) remain relatively small on most modern processors. Exposing more architectural registers to compilers and programmers can improve the effectiveness of compiler optimization and the quality of code. However, increasing the number of architectural registers by simply adding extra bits to the register fields of instructions will expand the code size. Therefore, a better way of exposing more ISA registers without significantly expanding the code size is needed. This paper presents a new ISA called Floating Accumulator Architecture ( FAA ) that can expand the number of ISA registers without increasing the instruction length. Unlike the accumulator architecture whose accumulator is a fixed, special register, FAA dynamically chooses a register from the general-purpose register file as the accumulator. In other words, the accumulator in FAA is an alias to some register in the register file at any instruction, and the alias relation can be dynamically updated by FAA at any program points. Since the accumulator implicitly stores the result, the destination register field can be omitted from FAA instructions, resulting in a saving of 3 to 5 bits for each instruction. This new free instruction bit space can be utilized in two possible ways: doubling the number of ISA registers of modern 32-bit RISC processors or maintaining the number of ISA registers for 16-bit instructions on embedded processors. This paper presents the result of utilizing the free bit space to double the number of ISA registers from 16 to 32 on ARM processors, and experimental results show that performance can be improved by 7.6% on average for MediaBench benchmarks. [ABSTRACT FROM AUTHOR]

The usage of locating systems in sports elevates match and training analysis to a new level. By tracking players, balls and other sports equipment during matches or training, the performance of players can be analyzed, the training can be adapted and new strategies can be developed. The radio-based RedFIR system equips players and balls in soccer with miniaturized transmitters, while antennas distributed around the playing field receive the transmitted radio signals. A cluster computer processes these signals to determine the exact positions based on the signals’ Time Of Arrival (TOA) at the back end. While such a system works well, it is neither scalable nor inexpensive due to the required computing cluster. Also the relatively high power consumption of the GPU-based cluster is sub optimal. Moreover, high speed interconnects between the antennas and the cluster computers introduce additional costs and increase the installation effort. However, a significant portion of the computing performance is not required for the synthesis of the received data, but for the calculation of the unique TOA values of every receiver line. Therefore, in this paper we propose a smart sensor approach: By integrating some intelligence into the antenna (smart antenna), each antenna correlates the received signal independently of the remaining system and only a comparably small amount of resulting data is sent to the backend. While the idea is quite simple, the question of a well suited computer architecture to fulfill this task inside the smart antenna is more complex. Therefore, this paper provides an evaluation of embedded architectures, such as FPGAs, GPUs, ARM cores as well as a many core CPU (Epiphany), regarding processing performance and energy consumption. Additionally, we show that performance and energy consumption can be improved through heterogeneous computing techniques. Thereby, we are able to achieve the required 50.400 correlations per second in each smart antenna. As a result, the backend becomes lightweight, cheaper interconnects through data reduction are required and the system becomes more scalable, since most processing power is already integrated in the antenna. In addition, the evaluation results indicate that Software Defined Radio (SDR) approaches in general might benefit from a more diverse application of processing platforms. [ABSTRACT FROM AUTHOR]

In software-defined networks (SDN), most controllers do not have an established control function for endpoint users and access terminals to access network, which may lead to many attacks. In order to address the problem of security check on access terminals, a secure trusted access method in SDN is designed and implemented in this paper. The method includes an access architecture design and a security access authentication protocol. The access architecture combines the characteristics of the trusted access technology and SDN architecture, and enhances the access security of SDN. The security access authentication protocol specifies the specific structure and implementation of data exchange in the access process. The architecture and protocol implemented in this paper can complete the credibility judgment of the access device and user's identification. Furthermore, it provides different trusted users with different network access permissions. Experiments show that the proposed access method is more secure than the access method that is based on IP address, MAC address and user identity authentication only, thus can effectively guarantee the access security of SDN. [ABSTRACT FROM AUTHOR]

Although Internet of Things (IoT) brings significant advantages over traditional communication technologies for smart grid and smart home applications, these implementations are still very rare. Relying on a comprehensive literature review, this paper aims to contribute towards narrowing the gap between the existing state-of-the-art smart home applications and the prospect of their integration into an IoT enabled environment. We propose a holistic framework which incorporates different components from IoT architectures/frameworks proposed in the literature, in order to efficiently integrate smart home objects in a cloud-centric IoT based solution. We identify a smart home management model for the proposed framework and the main tasks that should be performed at each level. We additionally discuss practical design challenges with emphasis on data processing, as well as smart home communication protocols and their interoperability. We believe that the holistic framework ascertained in this paper can be used as a solid base for the future developers of Internet of Things based smart home solutions. [ABSTRACT FROM AUTHOR]

The biology-inspired intelligent computing system for the neuromorphic hardware implementation is useful in high-speed parallel information processing. However, the traditional Von Neumann computer architecture and the unsatisfactory signal transmission approach have jointly limited the overall performance of the specific hardware implementation. In this paper, a compact extreme learning machine (ELM) architecture synthesized with the spintronic memristor-based synaptic circuit, the biasing circuit, and the activation function circuit is presented. Notably, due to the threshold characteristic of the memristive device, the synaptic circuit has a bimodal behavior. Namely, it is capable to provide the constant and adjustable network weights between the adjacent layers in the ELM. Furthermore, two major limitations (process variations and sneak path issue) are taken into account for the detailed robustness analysis of the whole network. Finally, the entire scheme is verified with case studies in single image super-resolution (SR) reconstruction. [ABSTRACT FROM AUTHOR]

Advancements in computer vision research have put transformer architecture as the state-of-the-art in computer vision tasks. One of the known drawbacks of the transformer architecture is the high number of parameters, this can lead to a more complex and inefficient algorithm. This paper aims to reduce the number of parameters and in turn, made the transformer more efficient. We present Sparse Transformer (SparTa) Block, a modified transformer block with an addition of a sparse token converter that reduces the dimension of high-level features to the number of latent tokens. We implemented the SparTa Block within the Swin-T architecture (SparseSwin) to leverage Swin's proficiency in extracting low-level features and enhance its capability to extract information from high-level features while reducing the number of parameters. The proposed SparseSwin model outperforms other state-of-the-art models in image classification with an accuracy of 87.26%, 97.43%, and 85.35% on the ImageNet100, CIFAR10, and CIFAR100 datasets respectively. Despite its fewer parameters, the result highlights the potential of a transformer architecture using a sparse token converter with a limited number of tokens to optimize the use of the transformer and improve its performance. The code is available at https://github.com/KrisnaPinasthika/SparseSwin. • Proposing Sparse Transformer Block with limited latent tokens to enhance Swin Transformer efficiency and performance. • We examined the effect of regularization on the attention weight obtained in SparTa Block. • We obtained accuracy improvement on ImageNet100, CIFAR10, and CIFAR100 benchmark datasets. • We obtained a smaller parameter size compared to the state-of-the-art Transformer model. [ABSTRACT FROM AUTHOR]

In recent years, deep learning algorithms have rapidly revolutionized artificial intelligence, particularly machine learning, enabling researchers and practitioners to extend previously hand-crafted feature extraction procedures. In particular, deep learning uses adaptive learning processes to learn more complex and informative patterns from datasets of varying sizes. With the increasing availability of multimodal data streams and recent advances in deep learning algorithms, multimodal deep learning is on the rise. This requires the development of complex models that can process and analyze multimodal information in a consistent manner. However, unstructured data can come in many different forms (also known as modalities). Extracting relevant features from this data remains an ambitious goal for deep learning researchers. According to the literature, most deep learning systems consist of a single architecture (i.e., standalone deep learning). When two or more deep learning architectures are combined over multiple sensory modalities, the result is called a multimodal hybrid deep learning model. Since this research direction has received much attention in the field of deep learning, the purpose of this survey is to provide a broader overview of the topic. In this paper, we provide a comprehensive review of recent advances in multimodal hybrid deep learning, including a thorough analysis of the most commonly developed hybrid architectures. In particular, one of the main challenges in multimodal hybrid analysis is the ability of these architectures to systematically integrate cross-modal features in hybrid designs. Therefore, we propose a generic framework for multimodal hybrid learning that focuses mainly on fusion methods. We also identify trends and challenges in multimodal hybrid learning and provide insights and directions for future research. Our findings show that multimodal hybrid learning can perform well in a variety of challenging computer vision applications and tasks. • We categorize these methods based on hybrid deep architectures. • We review recent advances in unimodal and multimodal hybrid deep learning. • We consider multimodal and hybrid fusion techniques. • We highlight several challenging application-driven hybrid architectures. • We discuss current trends and challenges in multimodal hybrid learning. [ABSTRACT FROM AUTHOR]

In the early stages of system of systems (SoS) meta-architecture concept development, it is greatly beneficial to have a formal method of architecture assessment to ensure compliance to stakeholder needs and requirements. Key performance attributes (KPAs) and key functional attributes (KFAs) are linguistic terms that represent the non-functional and functional requirements of the architecture. KPAs and KFAs can be assessed and converted into numeric values that can be used as fuzzy inputs to Mamdani-type rule based fuzzy inference systems (MRBFIS) to make fuzzy assessments of SoS meta-architecture concepts. This paper details an application of an assessment model featuring the integration of two separate MRBFISs; each with five inputs, five membership functions (MFs), twenty five If-Then rules, and a single output that is determined by the fuzzy rule base. Each unique MRBFIS used in the assessment was developed using the MATLAB Fuzzy Logic Designer application. The numeric outputs of each MRBFIS were then combined to provide an integrated KPA and KFA total architecture assessment score. The assessment model detailed in this paper provides a formal method of architecture assessment to be used in conjunction with trade space exploration, systems scoping, and the concept generation phase. This assessment model may help prevent costly project failures, system ambiguity late in development, unacceptable risks, cost overrun, and the inability to develop critical systems. [ABSTRACT FROM AUTHOR]

This paper proposes a complex, adaptive System of Systems architecture whose goal is to intelligently and dynamically host Massive Multi-Player Online (MMO) games. Furthermore, the use of a Perceptron employed with a Sigmoidal Membership Function trained by the Least Mean Squares learning algorithm is proposed. The network intelligently manages communications and interactions between equal, subordinate, and client level servers based on a reward returned by each respective neural network. The success of these techniques allows for a fully open and interactive world with minimal server/client maximums, minimal load times, and minimal network down-time. This freedom is due to the dynamic trading of resources and/or hosted clients during execution. This paper also outlines a proof of concept application designed to demonstrate the viability of this concept. Experimental results show that the complex system of systems is able to quickly adapt to the quickly changing environment thereby proving its plausibility as an adaptive and dynamic server management system. [ABSTRACT FROM AUTHOR]

A novel histogram generation hardware architecture, which can develop histogram for all types of grayscale images of size (256 x 256), is presented in this paper. The histogram produced from the proposed hardware gives exactly the same information as obtained from a histogram plot using simulation tool like Matlab with 100 percent accuracy. Hardware realization of the architecture makes it suitable for generating real-time histogram in medical and military applications which is practically difficult in software based implementations. Experimental results shows that the frequency of operation of the proposed architecture is very high both for Field Programmable Gate Array (FPGA) as well as for Programmable SoC (PSoC) based implementation. To the best of our knowledge, this is the first hardware implementation for grayscale image histogram generator for the selected histogram generation algorithm mentioned in this paper. [ABSTRACT FROM AUTHOR]

This paper presents design of novel embedded computational architectures for real time, in-motion mapping based on ultrasound sensors for use in resource constrained autonomous rovers. Autonomous rovers are a class of real time systems that are constrained for size, weight, on-board computational resources and power. Embedded computing architectures designed for implementing the mapping and navigational algorithms must optimize the use of these resources. In the process of map generation, raw sensor data obtained from an array of ultrasound sensors is filtered for sensor noise using probabilistic sensor model, and probabilistic data fusion methods are employed for spatial and temporal correlation of data for improving the map. In this paper, we present a System-on-Chip design based design space exploration of embedded computational architectures for implementation on field programmable gate arrays. We seek to exploit system level, region level and sensor level parallelism in the mapping algorithm for enhancing the throughput. Design space exploration is carried out by employing existing soft core processors, designing custom co-processors and data path modules and integrating them using parallel and pipelined data flow approaches. Results of mapping a test area on all the architectures are compared to characterize the performance and suitability of the proposed architectures. [ABSTRACT FROM AUTHOR]

This paper presents an extensive performance study of the implementation of Hardware Transactional Memory (HTM) in the Haswell generation of Intel x86 core processors. It evaluates the strengths and weaknesses of this new architecture by exploring several dimensions in the space of Transactional Memory (TM) application characteristics using the Eigenbench (Hong et al., 2010 [1]) and the CLOMP-TM (Schindewolf et al., 2012 [2]), benchmarks. This paper also introduces a new tool, called htm- pBuilder that tailors fallback policies and allows independent exploration of its parameters. This detailed performance study provides insights on the constraints imposed by the Intel’s Transaction Synchronization Extension (Intel’s TSX) and introduces a simple, but efficient policy for guaranteeing forward progress on top of the best-effort Intel’s HTM which was critical to achieving performance. The evaluation also shows that there are a number of potential improvements for designers of TM applications and software systems that use Intel’s TM and provides recommendations to extract maximum benefit from the current TM support available in Haswell. [ABSTRACT FROM AUTHOR]

A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 219 MHz for Xilinx Virtex 6 and is capable to process real time 110 1080p frames per second or 24 4K frames per second. [ABSTRACT FROM AUTHOR]

In the converging world of High Performance Computing and Big Data, moving data is becoming a critical aspect of performance and energy efficiency. In this paper we present the Advanced DAta Movement Analysis Toolkit (ADAMANT), a set of tools to capture and analyze data movement within an application, and to aid in understanding performance and efficiency in current and future systems. ADAMANT identifies all the data objects allocated by an application and uses instrumentation modules to monitor relevant events (e.g. cache misses). Finally, ADAMANT produces a per-object performance profile. In this paper we demonstrate the use of ADAMANT in analyzing three applications, BT, BFS, and Velvet, and evaluate the impact of different memory technology. With the information produced by ADAMANT we were able to model and compare different memory configurations and object placement solutions. In BFS we devised a placement which outperforms caching, while in the other two cases we were able to point out which data objects may be problematic for the configurations explored, and would require refactoring to improve performance. [ABSTRACT FROM AUTHOR]

Performance Monitoring is an integral part of maintenance. Requirements for a monitoring solution for Cloud are totally different from a legacy and virtualized environment monitoring solution. There are many third party tools/solutions available for monitoring a cloud. But there are no standard models exist for such a solution as what all parameters needs to be covered in the solution so that an exhaustive performance report can be produced for the service provider. In the context of Cloud Computing becoming the most sought after technology, there is a need for such a standard model. This paper is intended to provide a very brief introduction about Cloud computing and its architecture, illustrates how Cloud Performance monitoring differs from traditional monitoring, the different types of monitoring in cloud and metrics of interest to various users. The paper also proposes a high level view of a model which can be used as a guideline while coming up with performance monitoring solutions for cloud. [ABSTRACT FROM AUTHOR]

Formal methods and verification technique are often used to develop mission-critical systems. Cloud computing offers new computation models for applications and the new model can be used for formal verification. But formal verification tools and techniques may need to be updated to exploit the cloud architectures. Multi-Tenant Architecture (MTA) is a design architecture used in SaaS (Software-as-a-Service) where a tenant can customize its applications by integrating either services already stored in the SaaS database or newly supplied services. This paper proposes a new concept VaaS (Verification-as-a-Service), similar to SaaS, by leveraging the computing power offered by a cloud environment with automated provisioning, scalability, and service composition. A VaaS hosts verification software in a cloud environment, and these services can be called on demand, and can be composed to verify a software model. This paper presents a VaaS architecture with components, and ways that a VaaS can be used to verify models. Bigragh is selected as the modeling language for illustration as it can model mobile applications. A Bigraph models can be verified by first converting it to a state model, and the state model can be verified by model-checking tools. The VaaS services combination model and execution model are also presented. The algorithm of distributing VaaS services to a cloud is given and its efficiency is evaluated. A case study is used to demonstrate the feasibility of a VaaS. [ABSTRACT FROM AUTHOR]

For many years, scheduling problems have been concerned either with parallel processor systems or with dedicated processors—job shop type systems. With a development of new computing architectures this partition is no longer so obvious. Multi-core (processor) computers equipped with GPU co-processors require new scheduling strategies. This paper is devoted to a characterization of this new type of scheduling problems. After a thorough introduction of the new model of a computing system, an extension of the classical notation of scheduling problems is proposed. A special attention is paid to preemptions, since this feature of the new architecture differs the most as compared with the classical model. In the paper, several scheduling algorithms, new ones and those refining classical approaches, are presented. Possible extensions of the model are also discussed. [ABSTRACT FROM AUTHOR]

The main theme of this paper is to provide a cognitive architecture, MHP/RT (Model Human Processor with Realtime Constraints), that is appropriate for describing the idea, “The agent would not be getting an informational input or a reinforcement, but the inputs would be better described as perturbations on a self-organizing complex systems”, as stated in the call for the workshop, Enaction, Complex Systems and Cognitive Architectures. MHP/RT describes a cyclic process of action selection and memorization while one lives in the world, and the memory is gradually structured as multi-dimensional frames as one interacts with the environment. Behavioral processing constraints are imposed by conscious and unconscious processes, and behavior must be synchronized with the ever-changing external and internal environments. This paper provides a brief explanation of MHP/RT and multi-dimensional memory frames, followed by how memory is structured as one develops. [ABSTRACT FROM AUTHOR]

This paper describes the CIRANO platform, a cloud Integrated Development Environments (IDE) that substantially supports Model Driven Development (MDD) and team collaboration, in order to facilitate the development of cloud–based applications. The paper presents the state of the art in the field and discusses the technical details of CIRANO architecture and its modular implementation. The main features of the proposed platform are presented as a case study application concerning the update and porting of an existing collaboration system, called Comidor. The paper discusses the findings in comparison with existing tools and proposes extensions of the platform as future work. [ABSTRACT FROM AUTHOR]

End users urgently request using mobile devices at their workplace. They know these devices from their private life and appreciate functionality and usability, and want to benefit from these advantages at work as well. Limitations and restrictions would not be accepted by them. On the contrary, companies are obliged to employ substantial organizational and technical measures to ensure data security and compliance when allowing to use mobile devices at the workplace. So far, only individual arrangements have been presented addressing single issues in ensuring data security and compliance. However, companies need to follow a comprehensive set of measures addressing all relevant aspects of data security and compliance in order to play it safe. Thus, in this paper at first technical architectures for using mobile devices in enterprise IT are reviewed. Thereafter a set of compliance rules is presented and, as major contribution, technical measures are explained that enable a company to integrate mobile devices into enterprise IT while still complying with these rules comprehensively. Depending on the company context, one or more of the technical architectures have to be chosen impacting the specific technical measures for compliance as elaborated in this paper. Altogether this paper, for the first time, correlates technical architectures for using mobile devices at the workplace with technical measures to assure data security and compliance according to a comprehensive set of rules. [ABSTRACT FROM AUTHOR]