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The goal of this thesis is to analyze how MPEG-2 encoder can be optimized for real-time streaming applications Hw/Sw design re-configurable platform is chosen, where part of algorithm runs on CPU or on re-programmable hardware as a hardware accelerator. The structures is based on block level pipelining(BLP) where each frame is divided in 8X8 pixel blocks and each block is processed through the MPEG-2 video compression algorithm designed in a pipeline fashion and optimized so at to achieve maximum throughput. Here, we have designed an encoder for a Xilinx Zynq7000 series SoPC FPGA platform named as Zedboard. Initially, the encoder is designed in C and run on ARM cortex A-9 processor. This code is then profiled for ARM processor based on computational requirements. The results are analyzed and the computationally intensive subsystems are implemented as hardware accelerators to attain the desired features.

Road detection is an important machine vision problem with applications to driver assistance systems and autonomous vehicles. We carried out a literature survey of the state of the art road detection algorithms. Simulations of these algorithms were performed on road images taken from multiple datasets which revealed certain limitations such as failure under shadows or in the absence of lane markers. This is why the past few years saw the emergence of illuminant invariant based road detection techniques as the state of the art. As the name suggests, illuminant invariant is a feature which contains the colour information of the surface being captured independent of the illumination source. However, the derivation of illuminant invariant image from the RGB image makes use of the assumption that the surface being captured is lambertian. The smooth road surfaces that reflect sunlight are specular and they violate the lambertian assumption. Thus, the algorithms based on illuminant invariant feature fail to detect the road region containing specularities. The road detection algorithm functions by building a road model in the illuminant invariant feature space for each frame. The white markings that are painted over the roads in the form of zebra crossings, lane markers and arrows are not included into the road model. Hence, the algorithm fails to detect them as a part of road region. The first contribution of this thesis is to address the limitations of specularities and lane markers, thus improving the robustness of the state of the art road detection algorithm. We propose a novel specularity detection and removal method for road scenes which also removes the white markings present in the road image. The region of the image containing specularities/ markers is filled with same shade as its surrounding region. Any road detection algorithm has two aspects- the first is robustness and next is real time implementation. The second contribution of this thesis is implementation of the proposed algorithm on BeagleBone Black and Rapsberry pi-2, which are low cost, low-power single-board computers. This provides a proof-of-concept of real time computation. Thus, the thesis improves the accuracy of the state of the art path detection and provides means of real time implementation on mobile platforms.

System on Chip are processor centric platform that offer hardware, software and I/O programmability on a single chip. A SoC basically consists of two parts - The Processing System and Programmable Logic. Processing System is formed around a processor while Programmable Logic section is FPGA logic fabric. The Software Defined Radio has become a main area of interest in wireless communication technology due to its re-configurability as per requirement using software. In SDR some physical layer functionalities have very high degree of computational complexity so software can be used to define the behaviour of these elements: it is unsuitable for implementing the processing itself. The less complex functionality such as encoding, modulation etc. can be performed either in software of hardware. This is the reason that SDR calls for a close integration of processor running software to control the physical layer functionality and a high speed reconfigurable resource to manage the physical layer processing. The work done here presents the idea of partitioning hardware and software parts of software defined radio (SDR) and it also includes functionality validation by implementation on a system on chip (SoC). The design used here is a multi mode multi band digital modulator which supports BPSK and QPSK modulation schemes.

This thesis presents a Digital Costas Loop project which is used to demodulate BPSK modulated digital signal. Field Programmable Gate Array(FPGA) technology is flexible enough to perform Digital Signal Processing tasks. Direct Digital Synthesizer(DDS) is used to generate carrier frequency and is act as a local oscillator whose oscillating frequency is controlled by feedback loop. The system is analysed using logic analyser tool, ChipScope Pro, provided by Xilinx to analyse internal signals of design. Various waveforms are presented in this report for better visualization of the working of design.

There are many sensors and devices inside the satellite. All these devices need to communicate with each other, those devices can be sensor nodes or control device. According to current technology communication between different sensor nodes inside the satellite is wired, which adds the weight of the harness cable. It will be reliable if the communication between them is made wireless. Protocol satisfying communication standards at low data rate and short range wireless networking must be developed. Protocol which is suitable to meet our requirements is available in the market in commercial packages, but the commercial standard devices cannot provide the efficient functionality in space as they are not resistant to the various radiation effects taking place in space. So our aim is to design a protocol in hardware description languages which can be embedded in radiation resistant series of space Grade FPGA. The baseband transceiver proposed in this thesis uses OQPSK modulation, Pseudo noise spread spectrum is used for coding and sinusoidal pulse shaping having theoretical bandwidth efficiency of 2bits/Hz same as QPSK and OQPSK is used for baseband processing. The transceiver is initially simulated in MATLAB Simulink and then in Verilog HDL by the MODELSIM simulator.

In absence of atmospheric protection, electronics involved in space systems are exposed to radiation effects. For maintaining the proper functioning of the device in space various distinct techniques are put in use. A prominent radiation effect called Single Event Upset (SEU) is capable of changing the state of data or any component within the system. Thus, if not rectified even a single error may lead to system failure. Further, the space system must have flexibility for easy modification and upgradation. Hence, the idea of developing a fault tolerant system in FPGA based on TMR scheme stands justified. The TMR scheme, which involves execution of same program in three redundant processors with majority voters to produce output, is used for SEU mitigation. Moreover, using softcore processors and FPGA provides the space system with wide flexibility for reconfiguration. This study provides a discussion on various Radiation effects on electronics in space environment, and the techniques used in mitigation of these effects for fault tolerance. In this thesis, a new context recovery algorithm for TMR-based system to detect and correct an SEU is proposed. Further, a hardware implementation of a trivial context recovery strategy (Checkpointing and Rollback scheme) is realized in Spartan-6 FPGA SP601 Evaluation kit for a MicroBlaze soft core processor system and tested.

Nowadays, Application Specific Integrated Circuit (ASIC) design are becoming complex, even designs based of Field Programmable Gate Array (FPGA) are also complex. So it is very difficult to verify the design through waveform or log files. For that, some self-checking environment is needed to verify the functionality of the design. In my thesis work, I have worked upon developing the verification environment using System Verilog. In signal processing, most of the transformation uses multiply and addition function frequently. So Multiply-Accumulate (MAC) is the dedicated hardware to improve the speed of Digital Signal Processor (DSP). In this thesis, I have written a Verilog HDL code for MAC unit of DSP in ModelSim SE 6.3f and synthesized in Xilinx ISE 8.1i. System Verilog is used to verify MAC unit. Simulations are done using tool named ModelSim SE 6.3f of Mentor Graphics®. The constrained-randomised inputs and direct inputs are fed to the Design Under Test (DUT) as well as reference model. The output from both systems are compared to check functionality. The functional coverage and code coverage are measured for correctness of the design. The constrained random vectors and direct test cases are used to achieve higher coverage.

Verification of the digital systems become important part in the industry. In this thesis I verified two modules of ASIP DSP processor using System Verilog. The Thesis describes the design of Address Generation Unit (AGU) and Register File (RF) of Application Specific Instruction Set DSP and it is separated in two parts. Some theoretical background, description of the different steps for the designing of AGU and its verification plan has been shown in first part of the thesis - in chapter 2 and in chapter 3. Here AGU is designed for generating address for convolution process where circular addressing mode is used. The second part contains Register File theoretical background and its general designing steps, its simulation result and its verification plan in System Verilog. Both AGU and RF which are the DUTs in this thesis, have been implemented in Verilog, and their simulation and verification done in ModelSim® software.

A fundamental competence of any mobile robot system is the ability to remain localized while operating in an environment. For unknown/partially known environments there is a need to combine localization with automatic mapping to facilitate the localization process. The process of Simultaneous Localization and Mapping (SLAM) is the topic of this thesis. SLAM is a topic that has been studied for more than two decades using a variety of different methodologies, yet it deployment has been hampered by problems in terms of computational complexity, consistent integration of partially observable features, divergence due to linearization of the process, introduction of topological constraints into the estimation process, and efficient handling of ambiguities in the data-association process. Purpose of this study is to understand the basic problem of SLAM. Using ultrasonic sensor and wheel encoder only, implementation of SLAM is approached. This is a very basic method of SLAM, but it is necessary to understand the problem of SLAM. The method used in this study is very simple to understand and is based on modified SLAM [3].

In digital communication, the signal to noise ratio (SNR) of the channel is one of the major limitations on the operating performance. Solution in terms of coded data and errorcorrecting code has been introduced to improve the performance. Forward error correction technique with Convolution encoding and Viterbi decoding has been introduced here for this purpose. A Convolution encoder and Viterbi decoder of code rate 1/2, constraint length (K) of 7, 8 & 9 has been designed using Verilog HDL and incorporated with our application Software defined radio using black box in MATLAB Simulink. It is important to improve the performance and reduce the power and area of the decoder. In this project, Viterbi decoder adopted the Process Element (PE) technique which made it easy to adjust the throughput of the decoder by increasing or decreasing the number of PE. By the method of Same Address Write Back (SAWB), the number of registers reduced to half in contrast with the method of ping-pong.

The work presented here, deals with the carrier synchronization in digital communication system. The transmitter and receiver are two separate circuits located at a distance end and rarely share same carrier frequency oscillator and hence it required to synchronize these two carrier frequency oscillator. This task is performed by the circuit called carrier recovery at receiver end. In this document, different sub modules required to implement carrier recovery structure at receiver end is discussed in detail and each sub module is tested separately using Xilinx® ISE tool. Then these sub modules are used as black boxes, to realize complete carrier recovery structure in Matlab Simulink® tool. By using Matlab Simulink® tool one would get better idea of signal processing at each stage of the carrier recovery structure. Then this complete carrier recovery model of Simulink® is translated to Modelsim® model and verified for functionality. Here this carrier recovery model is used for Software Defined Radio (SDR) application so the complete model of SDR is realized in Matlab Simulink® environment and recovered carrier is used for demodulation part of the SDR

Now a days Software Defined Radio(SDR) is becoming popular for wireless communication because of it’s flexibility to change as per requirement through software. The work presented here describes the different methods of designing a Multiband and Multimode MODEM, implementation on programmable device like FPGA and verification for different functionality and specification. The design presented here has ability to switch between different modulation scheme and different data rate. Multiband and Multimode modem includes BPSK and QPSK modulator and demodulator with Forward Error Correction and other base band processing

Verification is major concern in product development life cycle. The number of human hours required writing a test bench and choice of verification approach is the major contributor in the Non Recurring Engineering (NRE) cost. There are too many techniques for verification. Register Transfer level (RTL) verification is too slow. Transaction based verification technique is used for faster verification of any Intellectual Property core. Transaction-based verification allows simulation and debugging at the transaction level, in addition to signal or pin level. All possible transaction types between different modules in a system are created and systematically tested. Design under test (DUT) operates at a binary stimulus level (e.g. Zeros and Ones). Test bench includes one model to define the transactions at a high level and another model to interpret transaction and translates them into the binary level. DUT is implemented in lower abstraction language like Verilog and test bench is created in higher abstraction language like C++. The JPEG Encoder Intellectual Property (IP) core is used as a DUT. This IP is taken from opencores.org website. Whole system is verified on ZeBu emulator.

Field Programmable Gate Array (FPGA) can be used to enhance the efficiency and the flexibility of digital controller. FPGA implementation of digital controllers leads to real time realizations with small size and high speed. Also it offers advantages such as complex functionality, fast computation, and low power consumption for high volume production. This thesis presents realization of FPGA based speed control of brushless dc (BLDC) motor - a real time application. The construction and the operation of the BLDC motor are described. The different control strategies for speed controller and digital pulse width modulation (PWM) control technique are implemented and tested on BLDC motor. Also their performance is evaluated. Proportional Integral (PI) controller and Fuzzy Logic Controller (FLC) are implemented in FPGA as a digital controller. The PI controller is governed by the values of proportional gain and integral gain, while FLC behaves in much similar way as human controls the system. Logics of both controllers: PI controller and fuzzy logic controller are written in High Description Language (HDL). The performance of the PI controller is better than the fuzzy logic controller in case of the complete known plant.

Serial communication is widely being used from PCs to handheld mobile phones due to very less hardware, low cost, easier design process in comparison to parallel communication. For bit by bit, reliable transmission and receiving at the physical layer it is important for data sequences to have high transition density, low power spectral density, less bit error and reduced bandwidth. This thesis implements the universal serial bus 2.0 (USB 2.0) transceiver Macro cell interface (UTMI) in a generic form to use different low level signaling protocol blocks in other serial communication standards. The code written is synthesizable and verified for correct functionality. The HDL code is a state machine (Mealy machine) implementation from the specification of UTMI. The challenging part of the work was to implement clock and data recovery block as it involved a lot of engineering concepts like control theory, digital electronics and analog circuits. The work presents intricacies in the design of PLL for recovery of clock and data. UTMI helps in faster development of ASIC and provides an abstraction layer for the peripheral developers who are not involved in low level details of physical layer. Finally the results for UTMI implementation are presented.

Verification is major concern in product development life cycle. The number of human hours required writing a test bench and choice of verification approach is the major contributor in the Non Recurring Engineering (NRE) cost. There are too many techniques for verification. Register Transfer level (RTL) verification is too slow. Transaction based verification technique is used for faster verification of any Intellectual Property core. Transaction-based verification allows simulation and debug at the transaction level, in addition to signal or pin level. All possible transaction types between different modules in a system are created and systematically tested. It does not require detailed test benches with large vector. Device under test (DUT) operates at a binary stimulus level(e.g. Zeros and Ones). Test bench includes one model to define the transactions at a high level (e.g. READ) and another model to interpret transaction and translates them into the binary level. DUT is implemented in lower abstraction language like Verilog and test bench is created in higher abstraction language like C++. The Discrete Wavelet Transform’s (DWT) Intellectual Property (IP) core is used as a DUT. DWT is implemented by Lifting scheme based Daubechies 9/7 filter. Lifting scheme has an advantage over conventional convolution method like time complexity of operation. Wishbone transactor is designed for verification of IP core. Whole system is verified on ZeBu emulator. The same Wishbone transactor is used for verification of different Wishbone compatible IP core.

Signal Integrity (SI) and Power Integrity (PI) are the most critical issues as semiconductor industry is moving towards higher operational speeds. Signal integrity and power integrity are such issues that should be looked at system level rather than looking at active and passive networks separately. System level analysis becomes a necessity when the individual subsystems work according to specifications, and even after that complete system doesn't work well. System level signal integrity and power integrity problems for high speed serial links have been taken into account in this thesis. Serial links are being used more and more rather than parallel links due to lesser skew and lower pin counts. Specifically USB 2.0 IP is used for this thesis work, but the analysis is generic for all serial links. This thesis considers SI and PI as a dual and a common model is used which considers both SI and PI. A statistical co-analysis of SI and PI for high speed serial links is used, which can be used for a cost effective solution too. Statistical methods are used for efficient simulations and to extract maximum information contents in the least simulation combinations. Based on this co-analysis, the system is diagnosed or modified for better SI and PI. In the end, reflection gain concept is also taken in to account for the diagnosis of the system. All in all, USB 2.0 system is diagnosed for better SI and PI. System level robustness analysis of high speed serial links are taken into account with effect of external environment. A strong correlation between measured and simulated results is shown. A generic methodology for SI and PI for high speed serial links is presented with complete analysis of package, board, termination, squidd card, decoupling network etc..

Fast Fourier Transform (FFT) processors are today one of the most important blocks in communication systems. They are used in every communication system from broadband to 3G and digital TV to Radio LANs. This master’s thesis project deals with the pipelined, radix-2 algorithmic exploration and the hardware solution for the FFT processor with the FFT size of 2N points, the selection of the scaling schemes based on application requirement is discussed. The designed architecture is functionally verified in Simulink® and the Xilinx® ISE simulator. How to encapsulate the C++ coded algorithms or functions into the Simulink. This FFT processor is used in OFDM based BPSK modulated communication system for the WHD WVAN standard at the Low Rate Physical (LRP) lay. This thesis project presents the design of the 128 point fixed–point F streaming processor. The final architecture used is the SDF (single path with delay feedback) that implements the radix-2 FFT algorithm. Since the FFT processor can’t be used standalone, so in this thesis it is employed in an OFDM Transmitter and the performance is measured for SNR over a range of PAPRs. The goal of this report is to outline the knowledge gained during the master’s thesis project, to describe a design methodology for the fixed point pipelined FFT processors, the scaling choices and how to encapsulate the existing C code into the Simulink environment to measure the performance of fixed-point systems.

Transaction based verification is used for faster verification purpose. Reusable transactors are designed and designs are verified at transaction level using these transactors. The test bench are written in higher level language and applied to design via Transactor. Hardware emulators accelerate the use of transaction advantages for the verification people. A number of SoCs and components can be verified with this methodology. The Device under test (DUT) used here is 5th order signed DA-FIR filter and the Transactor designed is AMBA® AHB™ from ARM. The Transactor is designed as Bus functional model in Verilog and state machine model in C++. The C++ based test bench gives the command (input) for verifying design. The Transactor takes care of the signal needed for applying to DUT. The tool used for the verification is Eve’s ZeBu. The verification environment and methodology has been described and compared with the present scenario. Complexity and speed performance are the main constraints for the comparison.

The communication system using the OFDM principle is today one of the most important application in communication field. This system has various applications from broadband to 3G and digital TV to Radio LANs. This master’s thesis project deals with the implementation of certain specification, algorithmic exploration for WVAN (wireless video area network) in Simulink®. The implemented model and its specification is the reference for the hardware designing and verification. The model used in OFDM based QPSK/16-QAM modulated communication system for the WHD WVAN standard at the High Rate Physical (HRP) layer. This thesis project describes the functionality of the various communication blocks and the method of data transmission through these blocks. The main purpose of this model is to calculate the BER (Bit Error Rate). The final design which supports the different HRP mode for different code rate and different Modulation scheme can take different length of sub-packets which depends on the HRP mode of Transmission. This model also implements the radix-2 FFT algorithm for fixed point FFT processor. Since the FFT processor cannot be used standalone, so in this thesis it is employed in an OFDM Transmitter and Receiver. The goal of this report is to outline the knowledge gained during the master’s thesis project, to describe a design methodology for the OFDM based communication system for high throughput and best error protection. The functionality of each block of the communication system is written in „C‟ code and the output data of each block of Simulink Model is compared to 'C' code written output for the same input.

As cellular wireless communication becomes a worldwide communication standard, it is important in studying how data communications happens in a cellular system. In this Thesis work CDMA transmitter and receiver have been designed including the communication channel which include effects of multipath fading and noise. Effectiveness of rake receiver have been verified for varying SNR and with varying the number of fingers. Also the functionality of each block is analyzed.

This work presents the performance, noise analysis and FPGA implementation of Direct Sequence Spread Spectrum technique. Performance of signal increases as increasing parity bits in Hamming code algorithm. Increasing parity noise goes reduce therefore received signal close to its original value, but adding parity band-width requirement also increases. This work is bases on the IS-95 standard for CDMA (Code Division Multiple Access) Digital Cellular.

In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power consumption has become an important factor. Battery operated portable devices which performing the high performance processing task also consumes lots of power. The various methodologies are used to reduce the power dissipation by optimizing the parameters that are related to power consumption of circuit. The Static RAM is used as a cache memory in the processor and also has an application in the embedded system. Due to continuous advances in the integrated circuit technology, the density of SRAMs in embedded application has grown substantially in recent years. The SRAM block is becoming indispensable block in the system-on-chips (SoCs). The larger density SRAM block has a highly capacitive bit lines and data lines. The dynamic power of SRAM is mainly due to charging and discharging of highly capacitive lines. To perform the write operation in the SRAM cell to flip the data value, nearly full voltage swings is required on the bit line. This full voltage swing on the highly capacitive bit lines will consumes a greater amount power according to law of CV2f. Thus voltage swing reduction is an effective way to decrease the power dissipation. The current mode sensing technique is proposed to give the small voltage swing on the bit lines during write operation. In the proposed method the layout and simulation is done for the one bit line pair for three different methodologies. The bit line interference of selected cell with adjacent selected and non selected cell is also checked out. The proposed current conveyor method has shown an improvement in terms power dissipation over the voltage write and current read (VWCR) and current write and current read (CWCR) method without comprising the performance.

Dolby AC-3 is a flexible audio data compression technology capable of encoding a range of audio channel formats into a low rate bit stream. AC-3 is the de facto audio standard for high-end digital consumer multimedia equipment. In this thesis work we have implemented 8 point FFT module using radix-2 algorithm. This work also shows the implementation of 128 point IFFT module using split radix algorithm.

This work presents, the complete ASIC implementation of Discrete Covariance Kalman ¯lter, on a Parallel and Pipelined Bitrapezoidal Systolic Array architecture. The Kalman Filter equations are mapped on the designed architecture. This mapping requires, decomposing the overall equations, to calculate the Schur's complement, using Faddeev's algorithm. This facilitates an approach, to avoid the iterative process of calculation of matrix inverse. The designed Parallel and Pipelined architecture caters to high speed applications, by computing the single iteration of the filter in just 6 steps, each step individually taking only O(n) clock cycles. Further the processing efficiency is increased, by computing equations of O(n3) complexity in just O(n2) complexity only, where n is the order of the filter. Other unique feature of the designed architecture includes, increased robustness to rounding errors and resolving the reiterative Data input problem. The ASIC implementation was done by, Modelling the architecture using Verilog HDL,its Functional Verification was done, Logic Synthesis was done on Cadence RC 5:2 Synthesizer and Physical Synthesis on Cadence SOC Encounter. The implementation methodology presented for logic and physical synthesis resulted in efficient implementation of architecture in silicon. The design was mapped to target technology of 180nm and the synthesis results were analyzed. Physical synthesis was carried out for the same technology and the design gives final timing closure for 50MHz, which is quite high for a compute intensive algorithm like Kalman filter.

This work presents the design and ASIC implementation of Discrete Fourier Transform Processing Module. The performance of designed DFT processing module is better than radix-2 and radix-4 FFT algorithms, and is comparable to Split radix FFT algorithm, in terms of computational requirements. Different architectures are proposed for DFT processing module, and their comparative analysis is done. ASIC implementation of Discrete Fourier Transform processing module includes, its modelling using Verilog HDL, gate level synthesis of the modelled design and physical synthesis of netlist generated by gate level synthesis. The functionality of Design after physical synthesis is verified. Designed DFT processing module is retargetable and can be used as an IP.

Application Specific Instruction-set Processors (ASIP), also referred as extensible processors, represent the state-of-the-art microprocessor architecture. ASIPs are practically leading towards the realization of System-on-a-Chip (SoC) concept; as processor, customised for an application, can be easily integrated in a SoC as pre-designed and pre-verified soft RTL block. Most significant and challenging part for these flexible or programmable processors is the design methodology. The challenge lies in providing a simple configurable design space such that the outcome is optimised, efficient and customised application specific processor hardware, with very short design cycle time. The bottle neck for a processor is chiefly the data path design, as it has computational intensive functional units which add to the major portion of hardware area along with timing. In case of ASIP as well, data path modification is to be achieved as per the requirements. Current electronic design automation (EDA) tools are intelligent and if exploited well can actually help in providing various optimizations in the design. The implemented design approach is based on these aspects of selection of accurate data path elements along with distributed control path and exploiting the inbuilt functionality of EDA tools for generating user defined architecture. In this project a non-pipelined as well as five stage pipelined processor fabrics are implemented with configurable parameters. A library of basic arithmetic functional units is created from which a component of desired characteristic is selected and integrated in the data path. Synthesis of modified processor core is performed with a set of constraints to achieve required trade off between area, power and timing. Multi-supply voltage feature of the synthesis tool is exploited to meet the timing closure of the generated processor core.