Transaction based verification of multimedia IP

Verification is major concern in product development life cycle. The number of human hours required writing a test bench and choice of verification approach is the major contributor in the Non Recurring Engineering (NRE) cost. There are too many techniques for verification. Register Transfer level (RTL) verification is too slow. Transaction based verification technique is used for faster verification of any Intellectual Property core. Transaction-based verification allows simulation and debugging at the transaction level, in addition to signal or pin level. All possible transaction types between different modules in a system are created and systematically tested. Design under test (DUT) operates at a binary stimulus level (e.g. Zeros and Ones). Test bench includes one model to define the transactions at a high level and another model to interpret transaction and translates them into the binary level. DUT is implemented in lower abstraction language like Verilog and test bench is created in higher abstraction language like C++. The JPEG Encoder Intellectual Property (IP) core is used as a DUT. This IP is taken from opencores.org website. Whole system is verified on ZeBu emulator.