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In this work, we have fabricated the nanostructured p-Si/n-TiO2 hetero-junction diode by using a facile spin-coating method. The XRD analysis suggests the presence of well crystalline anatase TiO2 film on Si with small grain size (∼16 nm). We have drawn the band alignment using Anderson model to understand the electrical transport across the junction. The current-voltage (J-V) characteristics analysis reveals the good rectification ratio (103 at ± 3 V) and slightly higher ideality factor (4.7) of our device. The interface states are responsible for the large ideality factor as Si/TiO2 form a dissimilar interface and possess a large number of dangling bonds. The study reveals the promises to be used Si/TiO2 diode as an alternative to the traditional p-n homo-junction diode, which typically require high budget.

This experiment demonstrates the electrical behaviors of fully solution processed HfO2(MOS) in presence of different optical illumination. The capacitance voltage measurement was performed at frequency of 100 kHz with a DC gate sweep voltage of ±5V (with additional AC voltage of 100mV) in presence of deep UV (wavelength of 365nm with power of 25W) as well as white light (20W). It is found that there is a large shift in flatband voltage of 120mV due presence of white light during the CV measurement. However there is negligible change in flatband voltage (30mV) has been observed due to illumination of deep UV light.

We demonstrate the fabrication of a high performance photo detector by fully solution processed technique. The detector is fabricated with photo sensitive, low temperature (200˚C) and sol-gel processed titanium dioxide (TiO2) dielectric material on silicon substrate in the form of MIS structure with top aluminum gate. The optical detection experiment is performed on Al—TiO2—Si (MIS) device by measuring the capacitance—voltage (CV at 100 kHz) curve within the visible region of light (365 — 700 nm). The presence of light shift the flat band voltage (VFB) from 290 mV to 360 mV due to the generation of photo activated charge carriers by UV (365 nm) and white light, respectively. Moreover, the generation of the charge carrier increases drastically by the combination of UV and white, which resulting as a very large shift (600 mV) in the VFB. The entire experiment was performed in normal lab conditions with open air environment, without any clean room facility.

We studied channel scaling behavior of fully spin coated, low temperature solution processed thin film transistor (TFT) fabricated on p(++) - Si (similar to 10(21) cm(-3)) as bottom gate. The solution processed, spin coated 40 um thick amorphous Indium Gallium Zinc Oxide (a-IGZO) and 50 nni thick amorphous zirconium di-oxide (a-ZnO2) has been used as channel and low leakage dielectric at 350 degrees C respectively. The channel scaling effect of the TFT with different width/length ratio (W/L= 2.5, 5 and 15) for same channel length (L = 10 mu m) has been demonstrated. The lowest threshold voltage (V-th) is 6.25 V tbr the W/L=50/10. The maximum field effect mobility (mu(FE)) has been found to be 0.123 cm(2)/Vs from WiL of 50/10 with the drain to source voltage (V-D) of 10V and 20V gate to source voltage (V-G). We also demonstrated that there is no contact resistance effect on the mobility of the fully sol-gel spin coated TFT

Post-deposition annealing (PDA) is the inherent part of sol-gel fabrication process to achieve the optimum device performance, especially in CMOS applications. The annealing removes the oxygen vacancies and improves the structural order of dielectric films. The process also reduces the interface related defects and improves the interfacial properties. In this work, we have integrated the sol-gel spin-coating deposited high-κ TiO2 films in MOS. The films are fired at 400°C for the duration of 20, 40, 60 and 80 min. The thicknesses of the films were found to be of ∼ 30 nm using ellipsometry. The (Al/TiO2/p-Si) devices were examined with current-voltage (I-V) and capacitance-voltage (C-V) at room temperature to understand the influence of firing time. The C-V and I-V characteristic showed a significant dependence on annealing time such as variation in dielectric constant and leakage current. The accumulation capacitance (Cox), dielectric constant (κ) and the equivalent oxide thickness (EOT) of the film fired...

The continuous downscaling leads the search of high-gate dielectrics. The films amorphous in nature offered good mechanical flexibility, smooth surfaces and better uniformity associated with low leakage current density. In this work, 16 nm thick amorphous Al2O3 films on silicon substrate are fabricated by E-beam evaporation. The high value of refractive index (1.76) extracted from ellipsometry analysis directs the deposition of compact film. The AFM analysis reveal a flat surface with small RMS surface roughness 1.5 angstrom. The band gap is extracted from O-1s electron loss spectra and was found 6.7 eV and band alignment of Al2O3/Si is derived from the UPS measurements. The films are incorporated in Metal Insulator -Semiconductor (MIS) capacitor to perform the electrical measurement. The flat band voltage (V-FB), dielectric constant () and oxide trapped charges (Q(ot)) extracted from high frequency (1 MHz) C-V curve are - 0.4 V, 8.4 and 2 x 10(11) cm(-2), respectively. The small flat band voltage - 0.4 V, narrow hysteresis and very little frequency dispersion suggest an exceptional good Al2O3/Si interface with small quantity of trapped charges in the oxide. The leakage current density was 4.27 x 10(-8) A/cm(2) at 1 V. The moderate dielectric constant and low leakage current density with ultra-smooth surface is quite useful towards its application in future CMOS and memory devices.

Low leakage current density and high relative permittivity (dielectric constant) are the key factors in order to replace the SiO2 from Si based technology towards its further down scaling. HfO2 thin films received significant attention due to its excellent optoelectronic properties. In this work, ultra - thin (17 nm) HfO2 films on Si substrate are fabricated by RF sputtering. As deposited films are amorphous in nature and in order to get the reasonable high dielectric constant the films are annealed (700 degrees C, 30 min) in nitrogen environment. A high refractive index (2.08) and small grain size (similar to 10) nm was extracted from ellipsometry and XRD, respectively. The AFM study revealed a small RMS surface roughness 9 angstrom. Towards electrical exploration, the films are integrated in Metal-Insulator-Semiconductor (MIS) capacitors structure. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), and oxide trapped charges (Q(ot)) calculated from high frequency (1 MHz) C-V curve are 490 pF, 183 pF, 1.33 V and 1.61 x 10(-10) C, respectively. The dielectric constant calculated from accumulation capacitance is 17. The films show a very low leakage current density 4.3 x 10(-8) A/cm(2) at +/- 1 V.

In the present work, we have fabricated the zirconium doped TiO2 thin (ZTO) films from a facile spin - coating method. The addition of Zirconium in TiO2 offers conduction band offset to Si and consequently decreased the leakage current density by approximately two orders as compared to pure TiO2 thin (TO) films. The ZTO thin film shows a high dielectric constant 27 with a very low leakage current density similar to 10(-8) A/cm(2). The oxide capacitate, flat band voltage and change in flat band voltage are 172 pF, -1.19 V and 54 mV. The AFM analysis confirmed the compact and pore free flat surface. The RMS surface roughness is found to be 1.5 angstrom. The ellipsometry analysis also verified the fact with a high refractive index 2.21.

Dielectric degradation as low as 0.3 % has been observed for a highly reliable Titanium dioxide (TiO2) film after constant voltage stressing (CVS) with -4 V for 10(5) second at room temperature (300 K). The film was fabricated by sol-gel spin-coating method on a lightly doped p-Si (similar to 10(15) cm(-3)) substrate. The equivalent oxide thickness (EOT) is 7 nm with a dielectric constant 33 (at 1 MHz). Metal-Oxide-Semiconductor (MOS) capacitors have been fabricated with an optimum annealing temperature of 800 degrees C for one hour in a preheated furnace. The dielectric degradation is annealing temperature dependent. A degradation of 1.4 %, 1.2 % and 1.1 % has been observed for 400 degrees C, 600 degrees C and 1000 degrees C temperature annealed MOS respectively. The dielectric degradation increases below or above the optimum temperature of annealing.