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The alleviation effect on the Schottky barrier height (SBH) (ΦB) using ultrathin titanium dioxide and hafnium dioxide dielectrics in a single layer and a bilayer stack was demonstrated. ΦB in the Pt/n-Si contact was reduced from 0.53 to −0.058, 0.3, and −0.12 eV using 3 nm TiO2, 1 nm HfO2, and high-k/high-k bilayer insertion, respectively. A maximum of 122% reduction in ΦB was obtained using bilayer dielectric insertion, which is the highest ever reduction reported so far in a Schottky diode. This was achieved by effectively passivating the semiconductor surface states by HF cleaning followed by inserting an ultrathin film produced from the novel Atomic Layer Deposition (ALD) technique. The Gaussian distribution (GD) of barrier heights all over the interface has been investigated for both Metal–Semiconductor (M–S) and Metal–Insulator–Semiconductor (M–I–S) contacts. The nonlinear behavior in a conventional Richardson plot was observed with lower values of the Richardson constant (A*). We have reported the surface inhomogeneity in both M–S and M–I–S contacts through temperature dependency of diode characteristics. The standard deviation (σ) as evidence for the Gaussian distribution of barrier heights was determined using the ln(Is/T2) vs q/2kT plot. The results were validated by a modified Richardson plot where the values of A* obtained were found to be in close agreement with the known values. As the ALD technique is known for conformity and uniformity of thin films, the dielectric insertion has proved effective in mitigating the SBH. However, the inhomogeneity in both M–S and M–I–S points to the role of dipole formation at the interface.

The electrical and thermo-electric (TE) properties of the bismuth telluride (BiTe) -based two-dimensional (2D) thermoelectric (TE) devices with different thin film thicknesses are analyzed systematically. The studied thin film thicknesses are covered from 100 nm to 400 nm. The accurate measured systems for the Seebeck coefficient (S) and electrical conductivity (σ) extractions are also built up in this work. When the thickness of the BiTe-based thin film in the TE device is scaled from 400 nm to 100 nm, the occurred optimized temperature (T) for the highest S value in these devices is found to be shifted from 60°C to 100°C. On the other hand, the best σ is observed in the thinner (100 nm) BiTe-based thin film devices under the higher T (130°C). Based on the understanding of S and σ values, the power factor and the figure of merit (ZT) – i.e., the ability of a TE material to efficiently produce electricity – are also investigated further. Compared with the commercial bulk BiTe TE device, we demonstrate that the ZT value can be improved ∼50% with the thinner (100 nm) BiTe-based thin film devices in the higher T (>100°C) region.

The self-heating effect on Si1-xGex based FinFETs is analyzed and investigated with different device structures/dimensions, Ge concentration, and operated voltages. The module-level material properties of the thermal conductivities (k) in Si and Ge with different operated temperature (T), material thickness (t), and impurity concentration (N) are calibrated by the experimental thermo-electric measurement firstly in our simulation model. The maximum chip temperature in the Ge FinFETs is found to be ∼50 °C higher than in the Si FinFETs due to the poor intrinsic material property of k in Ge material. This seriously limits the development of the Ge FinFETs in the future scaled logic devices even Si1-xGex material (x>0.8) has the higher intrinsic carrier mobility than pure Si. One of the possible solutions to avoid this self-heating effect in Si1-xGex based FinFETs is to reduce the operated voltage (

The vertical gate-all-around (V-GAA) Si nano-tube (NT) devices with different diameter dimensions are studied in this work with the promising device performance. The V-GAA structure makes the transistor easy to be scaled down continuously to meet the complementary metal-oxide-semiconductor (CMOS) scaling requirements of the 7/10 nm technology node and beyond. The Si NT device with the hollow structure is demonstrated to have the capability to “deplete” and “screen-out” the out-of gate control carriers in the center of the NT and further result in the better device short channel control. Based on the study in this work, the V-GAA Si NT device with the optimized diameter dimension (=20 nm) can benefit the Ion-state current and reduce the Ioff-state stand-by power simultaneously, due to the less surface roughness scattering and the better short channel control characteristics. The proposed V-GAA Si NT device is regarded as one of the most promising candidates for the future application of the sub-7/10 nm logic era.

Five different kinds of insulators including BaTiO3, TiO2, Al2O3, CdO and ZnO on the n-type InGaAs metal-insulator-semiconductor (M-I-S) ohmic contact structure are studied. The effect for the dielectric constant (ε) of inserted insulator and the conduction band offset (CBO) between an insulator and semiconductor substrate is analyzed by a unified M-I-S contact model. Based on the theoretical model and experimental data, we demonstrates that the inserted ZnO insulator with the high electron affinity and the low CBO (∼0.1 eV) to the InGaAs substrate results in ∼10 times contact resistivity reduction, even the ε of ZnO is not pretty high (∼10).

An approximately 31% Id,sat improvement and 42% mobility enhancement are achieved on the planer Ge n-Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) by implementing the dislocation-stress memorization technology (D-SMT) stressor for the first time, based on an investigation of crystal re-growth velocities along different directions and the optimization of the dislocation angle (θ) in Ge. Ultra-high stress (>3 GPa) capping SiN film is found to be essential for modifying the crystal re-growth velocities along the [100] and [110] directions to optimize the θ. The change of crystal re-growth velocities and the mobility enhancement ratio with the stress along the assigned directions in Ge is also discussed, respectively.

The promising magnetic Ge metal-oxide-semiconductor field-effect transistor (MOSFET) is demonstrated by the implement of the BaTiO3 as the gate dielectric layer and the magnetic FePt film as the metal gate (MG) on the Ge (100) substrate. The designed magnetic FePt MG with the intrinsic 0.2 Tesla magnetic field along the vertical direction leads to ∼0.75 nm equivalent-oxide-thickness (EOT) reduction, ∼100X gate leakage (Jg) reduction, and ∼50% on-current (Ion) enhancement in the Ge FET due to the demonstration of the colossal magneto-capacitance effect. The influence of the magnetic field along different directions such as the vertical and the lateral direction on the Ge FET is also investigated in this work. The designed magnetic gate stack scheme on the Ge FET with the better Jg-EOT gate stack characteristics, Ion, and the short channel control behavior (Sub-threshold swing-EOT) provides the useful solution for the future low power mobile device design.

In this work, we demonstrate the ultra-low contact resistivity of 6.7 × 10−9 Ω/cm2 by inserting 0.6-nm-ZnO between Al and InGaAs(Si: 1.5 × 1019 cm−3). The metal-insulator-semiconductor tunneling diode with 0.6-nm-ZnO exhibits nearly zero (0.03 eV) barrier height. We apply this contact structure on the source/drain of implant-free In0.53Ga0.47As quantum-well metal-oxide-semiconductor field- effect transistors. The excellent on-state performance such as saturation drain current of 3 × 10−4 A/μm and peak transconductance of 1250 μS/μm is obtained which is attributed to the ultra-low source/drain resistance of 190 Ω-μm.

The thermo-elastic strain is induced by through silicon vias (TSV) due to the difference of thermal expansion coefficients between the copper (∼18 ppm/ °C) and silicon (∼2.8 ppm/ °C) when the structure is exposed to a thermal ramp budget in the three dimensional integrated circuit (3DIC) process. These thermal expansion stresses are high enough to introduce the delamination on the interfaces between the copper, silicon, and isolated dielectric. A compact analytic model for the strain field induced by different layouts of thermal copper filled TSVs with the linear superposition principle is found to have large errors due to the strong stress interaction between TSVs. In this work, a nonlinear stress analytic model with different TSV layouts is demonstrated by the finite element method and the analysis of the Mohr's circle. The characteristics of stress are also measured by the atomic force microscope-raman technique with nanometer level space resolution. The change of the electron mobility with the consideration of this nonlinear stress model for the strong interactions between TSVs is ∼2–6% smaller in comparison with those from the consideration of the linear stress superposition principle only.

The thin film deposition property and the process difference during the wafer size migration from 12″ (300 mm) to 18″ (450 mm) in the Chemical Vapor Deposition (CVD) equipment is improved and reduced, respectively, when the chamber hardware is designed with the help of 3D full chamber modeling and 3D experimental visual technique developed in this work. The accuracy of 3D chamber simulation model is demonstrated with the experimental visual technique measurement. With the CVD chamber hardware design of placing the inlet position and optimizing the distance between the susceptor edge and the reactor wall, the better thin film deposition property and the larger process compatibility during the wafer size migration from 12″ (300 mm) to 18″ (450 mm) for the industry cost reduction can be achieved. Non-dimensional Nusselt parameter is also found to be the effective indicator to monitor the thin film deposition property.

The Positron Annihilation Spectra (PAS), Raman, and Photoluminescence spectroscopy reveal that Si0.5Ge0.5/Si interface quality can be significantly improved by the low energy plasma cleaning process using hydrogen. In the PAS, the particularly small value of lifetime and intensity near the Si0.5Ge0.5/Si interface in the sample with the treatment indicate that the defect concentration is successfully reduced 2.25 times, respectively. Fewer defects existed in the Si0.5Ge0.5/Si interface result in the high compressive strain about 0.36% in the top epi-Si0.5Ge0.5 layer, which can be observed in Raman spectra and stronger radiative recombination rate about 1.39 times for the infrared emission, which can be observed in the photoluminescence spectra. With better Si0.5Ge0.5/Si interface quality, the SiGe-based devices can have better optical and electrical characteristics for more applications in the industry. The PAS is also demonstrated that it is the useful methodology tool to quantify the defect information in the SiGe-based material.