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This letter reports an 85 GHz low noise amplifier (LNA) employing derivative superposition based non‐linearity cancellation and a current re‐use topology. The LNA employs a two‐stage stacked architecture, each featuring neutralized differential pairs utilizing the same DC current. In derivative superposition, an auxiliary branch consisting of neutralized differential pairs cells is added in the LNA in parallel to stage 1 to ensure non‐linearity cancellation. Layout‐based capacitive neutralization is implemented to improve GMAX, resulting in simplified routing, reduced parasitics, and a more compact layout. The proposed LNA is fabricated in TSMC 28 nm CMOS process and achieves a peak gain of 8.4 dB at 84.2 GHz with a measured 3 dB bandwidth (BW3dB$\text{BW}_{3\text{dB}}$) from 79.4 to 92 GHz. The minimum measured noise figure is 12.8 dB. The LNA draws 34 mA of DC current from a 1.2 V supply. The highly linear LNA with IIP3 +6.5 dBm is tailored for automotive RADAR and 6G receivers. [ABSTRACT FROM AUTHOR]

This paper presents a power amplifier (PA) with an 8-way series–parallel power combiner for 5G communication. By theoretical analysis of the S-parameters matrix and the equivalence of the impedance network, the design of the multi-port combiner is transformed into a dual-port on-chip transformer, and the bandwidth expansion is achieved without increasing the in-band gain ripple based on the mismatch-consistent magnetically coupled resonator (MCR) technique. As a validation of the methodology, the 8-way series–parallel power combiner PA is implemented in 40-nm CMOS Bulk process. The large-signal performances of the PA at 31 GHz are 21.36 dBm, 17.1 dBm, and 25.7 % for P sat , OP 1dB , and PAE max , respectively. The proposed PA has a peak S 21 of 25.1 dB and a 3-dB bandwidth of 23.5–46.4 GHz, which fully covers the 5G new radio (NR) frequency range2 (FR2) operating band, and the S 21 ripple is less than 1-dB in the range of 26.0–42.3 GHz, which achieves a broadband flat frequency response and supports the feasibility of the design. [ABSTRACT FROM AUTHOR]

A high gain D‐band hybrid integrated on‐chip antenna (OCA) based on a low‐cost printed circuit board (PCB) packaging technology is analyzed and designed in a standard 40‐nm CMOS process in this paper. The proposed OCA is a hybrid structure of a slotted patch OCA with off‐chip PCB ground and off‐chip dielectric resonator (DR). The proposed OCA exhibits a simulated gain of 3.5 dBi and 53% radiation efficiency at 150 GHz. The simulated impedance bandwidth is 20 GHz. The radiation performance and impedance bandwidth of the OCA are observably improved with the proposed techniques. The proposed OCA occupies 0.52 × 0.56 mm2, and addresses the highly desirable yet challenging overall design of future low‐cost integrated millimeter‐wave (mm‐Wave) and terahertz (THz) systems, which hit the mark on cost and compatibility. [ABSTRACT FROM AUTHOR]

In this article, an analytical method for designing transformer matching network of millimeter‐wave (mm‐wave) low noise amplifier (LNA) is presented. In the circuit design, neutralizing capacitors (NCs) structure is used to mitigate the intrinsic gate‐drain feedback capacitance in the transistor for increasing the reverse isolation and available gain, thus allowing the common source (CS) structure can be regarded as an unilateralized active amplification part. The equivalent circuit of the active amplification part and the matching transformer network is modeled, then the analytical matching equations can be established, and the required matching transformer parameter can be determined quickly. As a proof of concept, a Ka‐band LNA operating at 37–43 GHz is designed and implemented in 65 nm complementary metal oxide semiconductor. The measured results show that the small signal gain of the circuit is 19.2–20.5 dB at 37–43 GHz. The noise figure (NF) in the operating band is 3.2–4.2 dB, and the minimum NF is 3.2 dB at 40.2 GHz. The chip area is only 0.08 mm2 excluding pads. [ABSTRACT FROM AUTHOR]

In the paper, a 18–33 GHz wideband low noise amplifier (LNA) with a T-type inductive network is proposed. The T-type inductive network generates two dominant poles at different frequencies for interstage bandwidth extension. As a result, the 3 dB bandwidth of the amplifier is efficiently expanded while maintaining low noise figure (NF), high gain, and a small footprint. For verification, a two-stage cascode LNA operating in K/Ka-band is designed and implemented in a 55 nm bulk CMOS process. The fabricated prototype demonstrates a peak gain 26.7 dB with a 3 dB bandwidth ranging from 17.8 GHz to 33.4 GHz and a fractional bandwidth up to 60.9 %. The measured NF varies between 2.8 and 4.5 dB across the entire 3 dB bandwidth, with a DC power consumption of 16.2 mW. The measured input 1-dB gain compression point is −26 to −20 dBm in the desired operating frequencies. Moreover, the LNA chip occupies a total silicon area of 0.35 mm2 including all testing pads with a compact core size of only 0.15 mm2. [ABSTRACT FROM AUTHOR]