An 8-way series-parallel combiner based power amplifier for mm-wave 5G communication in 40-nm CMOS.

This paper presents a power amplifier (PA) with an 8-way series–parallel power combiner for 5G communication. By theoretical analysis of the S-parameters matrix and the equivalence of the impedance network, the design of the multi-port combiner is transformed into a dual-port on-chip transformer, and the bandwidth expansion is achieved without increasing the in-band gain ripple based on the mismatch-consistent magnetically coupled resonator (MCR) technique. As a validation of the methodology, the 8-way series–parallel power combiner PA is implemented in 40-nm CMOS Bulk process. The large-signal performances of the PA at 31 GHz are 21.36 dBm, 17.1 dBm, and 25.7 % for P sat , OP 1dB , and PAE max , respectively. The proposed PA has a peak S 21 of 25.1 dB and a 3-dB bandwidth of 23.5–46.4 GHz, which fully covers the 5G new radio (NR) frequency range2 (FR2) operating band, and the S 21 ripple is less than 1-dB in the range of 26.0–42.3 GHz, which achieves a broadband flat frequency response and supports the feasibility of the design. [ABSTRACT FROM AUTHOR]