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Pulsed-laser annealing (PLA) was performed on a preformed Pt-doped Ni-rich silicide film (Ni2Si phase), and its microstructural and phase evolution were studied from submelting to melting condition by varying the laser power density (P). Vertically nonuniform compositional profile with an interfacial intermixing was observed under a solid state reaction regime (P

The importance of optimizing the millisecond annealing (MSA) temperature for Pt-doped NiSi ( ${\mathrm {Ni}}_{{1}-{x}}$ Pt x Si) contact formation was highlighted by implementing and characterizing the ${\mathrm {Ni}}_{{1}-{x}}$ Pt x Si films in the static random-access memory (SRAM) cells fabricated with a 28-nm design rule. MSA at 750 °C–900 °C effectively reduced the junction leakage current compared to that with the conventional rapid thermal annealing, because of its efficient suppression of Ni diffusion in the junction region. Moreover, with an increase in the MSA temperature, the beneficial effects of maintaining a low junction leakage, such as interface flattening and grain size increase, were observed. However, the increase in the MSA temperature deteriorated the statistical distribution of the standby leakage current of the SRAM cells by producing more encroachment and spiking defects; this was attributed to the build-up of a high initial film stress and large stress relaxation during the subsequent back-end processes.

Pt-doped NiSi‒NiSi2 thin films in a uniform lamellar structure with a periodicity on the scale of a few tens of nanometers were formed on Si(001) substrates using a continuous laser scanning process. When the Pt-doped NiSi film was melted at high temperatures and was supercooled at high solidification rates (a high scanning speed of over 200 mm/s), a NiSi‒NiSi2 lamellar structure evolved while interacting with the underlying Si substrate and following the classical eutectic solidification path. The lamellar spacing could be easily controlled by the laser scanning speed. In addition, the periodically formed, nearly single-crystalline NiSi and NiSi2 phases exhibited epitaxial relationships with each other and also with the Si(001) substrate. It is believed that this novel NiSi‒NiSi2 lamellar structure can be used as a template for application areas requiring an electrode with a line/space pattern on the scale of a few tens of nanometers that can be prepared without using costly photolithographic processes.

The objective of this study was to determine detailed microstructure of a Ni1–xPtxSi film formed via a melting/quenching process using high temperature laser annealing on a Si(001) substrate. The orthorhombic Ni1–xPtxSi film was found to be able to epitaxially grow with a crystallographic relationship of Ni1–xPtxSi[010]//Si[110], Ni1–xPtxSi(400)//Si(3 3 ¯ 1), and Ni1–xPtxSi (104)//Si(004). Volume expansion of the Ni1–xPtxSi film due to Pt incorporation was mainly accommodated by an increase in only one direction nearly parallel to the film surface (lattice parameter a). This was explained by the minimum coherent strain at the Ni1–xPtxSi (104)/Si(004) interface with an epitaxial growth tendency. Atomic-scale scanning transmission electron microscopy analyses revealed that the interface of Ni1–xPtxSi/Si had a repetitive atomic-step feature with energetically favorable Ni1–xPtxSi(004) terraces and (400) structural ledges that could increase the coherent area. By generating an array of misfit dislocations with an extra half plane of Ni1–xPtxSi(020), the elastic strain was further relieved.

In this letter, we have investigated the properties of In0.53Ga0.47As quantum-well (QW) metal–oxide–semiconductor field-effect-transistors (MOSFETs) on a 300-mm(100) Si wafer. We have explored the impact of scaling down In0.53Ga0.47As channel thickness ( $\text{t}_{\mathrm {ch}})$ from 15 to 5 nm. The fabricated devices show excellent electrostatic integrity, such as subthreshold-swing (SS) $\mu _{\textit {n$\_{}$eff}})$ of the fabricated devices to investigate the carrier transport properties of the InGaAs MOSFETs with different values of $\text{t}_{\mathrm {ch}}$ . The device with $\text{t}_{\mathrm {ch}} = 15$ nm displayed a value of $\mu _{\textit {n$\_{}$eff}} = 2,190$ cm2/V-s at room temperature. This valuewas found to decrease as $\text{t}_{\mathrm {ch}}$ was scaled down.

High density 1Gb embedded STT-MRAM in 28nm FDSOI technology was successfully demonstrated. Based on the highly reliable and manufacturable eMRAM technology, high yield over 90% was achieved at the operating temperature from −40°c to 105°c with satisfying read, write function and 10 years retention at 105°c. These results are mainly attributed to the advanced process for better control of MTJ CD, highly manufacturable process window and robust circuit design for high density chip. MTJ properties can be systematically adjusted by tailoring the MTJ stack and MTJ module process. Improved endurance up to 1E10 cycles was achieved to broaden eMRAM applications to eDRAM replacement.

To synthesize a thermally robust Ni1–xPtxSi film suitable for ultrashallow junctions in advanced metal-oxide-semiconductor field-effect transistors, we used a continuous laser beam to carry out millisecond annealing (MSA) on a preformed Ni-rich silicide film at a local surface temperature above 1000 °C while heating the substrate to initiate a phase transition. The melting and quenching process by this unique high-temperature MSA process formed a Ni1–xPtxSi film with homogeneous Pt distribution across the entire film thickness. After additional substantial thermal treatment up to 800 °C, the noble Ni1–xPtxSi film maintained a low-resistive phase without agglomeration and even exhibited interface flattening with the underlying Si substrate.

Synechococcus is an important photosynthetic picoplankton in the temperate to tropical oceans. As a photosynthetic bacterium, Synechococcus has an efficient mechanism to adapt to the changes in salinity and light intensity. The analysis of the distributions and functions of such microorganisms in the ever changing river mouth environment, where freshwater and seawater mix, should help better understand their roles in the ecosystem. Toward this objective, we have collected and sequenced the ocean microbiome in the river mouth of Kwangyang Bay, Korea, as a function of salinity and temperature. In conjunction with comparative genomics approaches using the sequenced genomes of a wide phylogeny of Synechococcus, the ocean microbiome was analyzed in terms of their composition and clade-specific functions. The results showed significant differences in the compositions of Synechococcus sampled in different seasons. The photosynthetic functions in such enhanced Synechococcus strains were also observed in the microbiomes in summer, which is significantly different from those in other seasons.

Recent advances in high-throughput sequencing technology allow for in-depth studies on microbial genomes and their communities. While multiple strains of the same species could display genomic variations with different gene contents in diverse habitats and hosts, the essential functions for a specific species are conserved as core genes that are shared among strains. We have comprehensively analyzed 238 strains of five different Bacillus species to identify the properties of core and strain-specific genes. Core and strain-specific genes in each Bacillus species show significant differences in their functions and genomic signatures. Using the core genes defined in this study, we have precisely identified the Bacillus species that exist in food microbiomes. Without resorting to culture-based whole genome sequencing, an unexpectedly large portion of the core genes, 98.22% of core genes in B. amyloliquefaciens and 97.77% of B. subtilis, were reconstructed from the microbiome. We have performed a pan-genome analysis on the core gene data of multiple Bacillus species to investigate the Bacillus species in food microbiome. Our findings provide a comprehensive genetic landscape of the Bacillus species, which is also consistent with previous studies on a limited number of strains and species. Analysis based on comprehensive core genes should thus serve as a powerful profiling tool to better understand major constituents in fermented food microbiomes.

We theoretically study and experimentally demonstrate a pseudomorphic Ge/Ge0.92Sn0.08/Ge quantum-well microdisk resonator on Ge/Si (001) as a route toward a compact GeSn-based laser on silicon. The structure theoretically exhibits many electronic and optical advantages in laser design, and microdisk resonators using these structures can be precisely fabricated away from highly defective regions in the Ge buffer using a novel etch-stop process. Photoluminescence measurements on 2.7 μm diameter microdisks reveal sharp whispering-gallery-mode resonances (Q > 340) with strong luminescence.

In-situ phosphorus doped silicon epitaxial film with 2.8 X 1021cm-3 doping level is found to show high tensile stress comparable to carbon doped silicon with 1.8% substitutional carbon. As-grown samples show electrically activated dopant concentration of less than 2 X 1020 cm-3. The high tensile and low activation could be well explained by formation of a pseudocubic Si3P4 structure in silicon lattice. Film resistivity of 0.29 mOhm-cm could be obtained with 0.25 ms annealing at 1200 {degree sign}C, with slight reduction in tensile strain. Also, 0.23 mOhm-cm could be obtained by millisecond anneal at 1300 {degree sign}C, but with 30% reduction in tensile strain.

Si n–i–p tunnel field-effect transistor (TFET) fabricated by plasma implantation and laser annealing is proposed. This TFET has sharp lateral source doping profile, which can reduce the tunneling distance and improve carrier tunneling. Enhanced on-current (12 μA/μm) and improved I ON / I OFF ratio (6 × 10 6 ) are observed in this TFET [ V DS = ( V GS − V BTBT ) = −1.1 V; V BTBT is the V GS at the lowest subthreshold current observed at given V DS ] at T = 300 K. In addition, the TFET fabricated by laser annealing shows improved subthreshold characteristics, reduced tunneling resistance and smaller threshold voltage than TFET fabricated by rapid thermal annealing. Low-temperature measurements of this TFET were also performed to confirm the carrier injection mechanism of band-to-band tunneling. Plasma implantation and laser annealing are effective and suitable to be applied in current CMOS technology for low power devices.

We report on the characterization of high Sn-content (∼10% Sn) GeSn films grown on (001) Ge/Si substrates using reduced-pressure chemical vapor deposition. Pseudomorphic 30 nm GeSn films were grown on relaxed Ge buffers, exhibit a smooth surface, and display strong photoluminescence (PL) with cavity-resonance fringes from the Ge buffer. Additional luminescence studies confirm that the measured PL originates from the GeSn film. A study on the effects of rapid thermal annealing is presented along with evidence of Sn surface segregation and formation of surface nanodots for anneals at 450 °C and above. Anneals at 400 °C for up to 500 s showed little change in PL intensity or material properties, which suggest that a critical temperature exists for post-growth thermal-processing of high Sn-content, compressively-strained GeSn films.

Segmented-channel Si1-xGex/Si p-channel MOSFETs are fabricated using a conventional process, starting with corrugated Si1-xGex/Sisubstrates. As compared with the control devices fabricated using the same process but starting with a noncorrugated Si1-xGex/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher ION for IOFF = 10 nA per micrometer layout width) due to enhanced hole mobility and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.

To synthesize a thermally robust Ni

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

3D MOSFET technology, such as FinFETs, is the central semiconductor inflection that brings new challenges and opportunities to the semiconductor industry. Dynamic surface annealing (DSA) enables the IC manufactures to solve many of the challenges. In this paper, we demonstrate DSA can form abrupt source/drain extension, which is essential to minimize the device's parasitic resistance. DSA also improves salicide morphology, minimize salicide piping defects, and reduce junction leakage. (© 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

We describe our work investigating strain relaxation behavior of epitaxial Si0.7Ge0.3 films on silicon (001) substrates beyond the critical thickness by using High Resolution X-Ray Diffraction (HRXRD). The effects of thickness, growth rate, dopant concentration and surface cleaning on strain relaxation on the SiGe films were investigated.

A continuous scaling of transistor devices is carried out by not only increasing the drive current but also reducing the off-state leakage current. For short channel devices, the reduction of leakage current is increasingly difficult and hence the use of multi-gate devices is looking increasingly more promising. One of the main areas of concern for multi-gate devices is the higher junction resistance due to high aspect ratio structures in these devices. Hence the use of epitaxy in these junctions is inevitable. In this work, we study the impact of process parameters on the final epitaxial junction shapes and how this affects the junction resistance. It is shown that the epitaxial junctions for n- and p-MOS have different shapes and hence will have to be controlled differently for the most optimum integration scheme.

Epitaxially grown Silicon Carbon (Si:C) in recessed junction regions has been shown to induce tensile stress in the nMOS channel and thereby enhance the transistor performance. In addition to the stress induced in the channel, this technology also needs to achieve low resistivity junctions for widespread use. This work discusses epitaxially grown heavily doped Si/ Si:C layers which can be used in nMOS junctions and can address both these requirements. Si:C epitaxial layers are shown to have phosphorus concentrations as high as 1.25 X 10^21 cm^-3 with resistivities as low as 0.3 mOhm.cm. Applications of these layers can range from Si:P cap layers for low series resistance to Si:PC layers for inducing stress in the nMOS channel.

In this paper, we review integration of selective epitaxy in advanced logic and memory devices. Embedded SiGe epitaxy has been adapted for logic pMOSFET fabrication from the 90 nm technology node and device performance continues to scale with higher [Ge] in the epitaxial SiGe layer. For nMOSFET performance boost, use of embedded silicon carbon (Si:C) epitaxial layer has been considered. Recent improvements in crystal quality of selective in-situ phosphorus doped Si:C epitaxy enables significant transistor drive current increase. For integration of Si:C epitaxy, effect of various thermal annealing processes on substitutional carbon incorporation and NiSi formation on Si:C epitaxy are described. Also, heavy phosphorus doping in Si and Si:C layers is discussed in terms of film resistivity and strain contribution. Selective epitaxy is being used to form elevated source/drain in DRAM memory devices where it provides immunity against short channel effects and results in improved retention time.

Si:C epitaxy was investigated to increase the substitutional carbon concentration, to achieve selectivity, and to understand growth characteristics on different Si crystallographic planes. A defective microstructure was observed next to the recess sidewalls. It was found that Si:C epitaxial growth on (110) crystallographic plane is heavily defective while the same epitaxy on (100) plane shows defect- free microstructure. By process optimization and using the appropriate chemistries for deposition and etch steps, we have developed a selective Si:C epitaxy process which result in a defect-free epitaxial layer that fills a 60 nm deep recessed area with 1.5 % substitutional [C] with 100 % substitutionality, and 100 % selectivity on dielectrics. Also, thermal stability of the substitutional [C] in Si:C epitaxy was tested with spike annealing at 1050 oC. No loss of substitutional [C] was observed after the spike annealing from a Si:C film with 100 % carbon substitutionality.

Although the development of a monolithically-integrated, silicon-compatible light source has been traditionally limited by the indirect band gaps of Group IV materials, germanium-tin (Ge 1-x Sn x ) is predicted to exhibit direct band gap behavior. In pseudomorphic conditions with materials of smaller lattice constant, the accumulation of compressive strain in Ge 1-x Sn x counteracts this behavior to prevent the direct band gap transition. One possible approach to compensate for this compressive strain is to introduce tensile strain into the system, which can be achieved by applying an external stressing agent to post-fabricated devices. We describe a suspended Ge 0:922 Sn 0:078 multiple quantum well microdisk resonator cavity strained by 140 nm of highly compressively stressed silicon nitride. Raman shifts and photoluminescence redshifts indicate that an additional 0.23-0.30% strain can be induced in these microdisks with this approach. The ability to tune the optical performance of these resonator structures by strain engineering has the potential to enable the development of low threshold Ge 1-x Sn x -based lasers on Si.

INTRODUCTION It is understood that a uniaxial tensile stress along a channel of transistor enhances electron mobility and drive current of NMOS transistors. Typically, a tensile stress-enhanced silicon nitride layer is used to strain the channel [1]. For even further enhancement of transistor drive current, a use of silicon carbon alloy (Si:C) in recessed source/drain (S/D) area has been considered. Alloying Si with C decreases lattice parameters when carbon atoms occupy substitutional sites of Si lattices. Very recently, it has been reported that a use of Si:C epitaxy in recessed S/D generates tensile strain in the channel of NMOS transistor and consequently increases transistor drive current [2]. The Si:C recessed S/D technology has two major challenges in preparing an epitaxy solution: One is how to incorporate carbon atoms into substitutional sites. As the solid solubility of substitutional carbon in silicon is only ~10 cm, carbon atoms at concentrations higher than this easily incorporate into interstitial sites or precipitate as β-SiC, resulting in no strain in the epilayer. Therefore, in order to achieve high substitutional carbon concentration (≥ 1%) with minimizing interstitial carbon concentration, non-equilibrium epitaxial growth conditions such as low temperature (≤ 600 C) are required [3]. The other is to obtain selectivity and reasonable growth rate of selective Si:C epitaxy process with maintaining high substitutional carbons. We have developed selective Si:C epitaxy processes with 1% or higher substitutional carbon concentration and will discuss characteristics of the epitaxy grown on recessed area of patterned wafers.

Integration of recessed Si:C source/drain (S/D) for deep sub- micron nMOSFET devices results in substantial improvement of electron mobility and drive current due to introduction of tensile strain in the channel. The compatibility of Ni-silicide contacts with Si:C source/drain is investigated in this paper. The Ni-silicide morphology and phase formation were studied by means of sheet resistance measurements, X-Ray Diffraction (XRD) and Energy Dispersive Spectroscopy (EDS) analysis, Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) inspection. The carbon concentration and profile in the NiSi:C film was studied by Secondary Ion Mass Spectrometry (SIMS) analysis. The strain in the Si:C substrate and NiSi:C film was studied by high resolution XRD (HRXRD). This paper demonstrates that Ni-silicide is compatible with Si:C. The tensile strain in Si:C is maintained after Ni-silicidation. The addition of carbon to silicon is found to stabilize the silicide morphology.

Germanium tin (GeSn) pMOSFETs with channel Sn composition of 7% are fabricated using a low thermal budget process. GeSn pMOSFETs show enhancement in hole mobility over control Ge devices by 85% in high inversion charge density regime. Hole mobility improvement observed in GeSn channel pMOSFETs compared with Ge control is due to the biaxial compressive strain in GeSn resulting from epitaxial growth of GeSn thin films on relaxed Ge buffer layers.

This paper reports fabrication of epitaxial Si/SiGe/Si-type optical waveguides with a well-controlled refractive index difference between the core and the cladding and with low transmission losses. A SiGe strip with a cross-section in the range of 0.5 μm ×0.5 μm– 5 μm ×5 μm was formed on the Si substrate. Then, a Si upper cladding layer was deposited. Some samples incorporated a compositionally graded layer between the SiGe core and the Si cladding layer. The fabricated structures show that the index contrast, Δn, increases linearly with the increasing Ge atomic concentration x in the Si1−xGex cores (Δn=αx, where α=1 at a wavelength of 0.633 μm). We determined waveguide transmission losses by measuring the ratio between the input and output optical power values through straight waveguides of different lengths. For waveguides with an index contrast (Δn/n) of 0.6% between the Si0.98Ge0.02 core and the Si cladding, the loss value for the wavelength at 1.55 μm was approximately 0.31 dB/cm. Structures with a graded layer show higher loss values than those without, which may be attributed to the asymmetric Ge grading in the horizontal and vertical directions. No measurable polarization dependence of the losses has been detected in waveguides, in agreement with the results of X-ray diffractometry that has shown relaxation of the Si0.98Ge0.02 on Si.

Highly activated n-type dopant is essential for n+/p germanium diodes which will be in use for source/drain regions in Ge n-MOSFET as the geometry scaling proceeds. This letter has investigated a combination of ion implantation of Sb in Ge and subsequent laser annealing, which resulted in highly activated Sb beyond 1020 cm-3. Well-behaved Sb-doped nv/p Ge diode I-V characteristics have been demonstrated combined with TEM, SIMS, and spreading resistance profiling characterization.

The human microbiome is one of the key factors affecting the host immune system and metabolic functions that are not encoded in the human genome. Culture-independent analysis of the human microbiome using metagenomics approach allows us to investigate the compositions and functions of the human microbiome. Computational methods analyze the microbial community by using specific marker genes or by using shotgun sequencing of the entire microbial community. Taxonomy profiling is conducted by using the reference sequences or by de novo clustering of the specific region of sequences. Functional profiling, which is mainly based on the sequence similarity, is more challenging since about half of ORFs predicted in the metagenomic data could not find homology with known protein families. This review examines computational methods that are valuable for the analysis of human microbiome, and highlights the results of several large-scale human microbiome studies. It is becoming increasingly evident that dysbiosis of the gut microbiome is strongly associated with the development of immune disorder and metabolic dysfunction.

A pseudomorphic growth of GeSn epitaxial films with [Sn] up to 16 at.% on relaxed Ge underlayer was demonstrated in a reduced pressure thermal chemical vapor deposition chamber. GeSn film resistivity can be as low as 0.3 mOhm-cm by in-situ boron doping of GeSn. Also, a GeSiSn film growth containing [Si]~24 at.% and [Sn]~4 at.% was achieved by flowing SiH 4 during GeSn growth.

On the basis of high-resolution x-ray diffraction measurements, the strain-stress analysis of GaN/(00.1)α-Al2O3 heteroepitaxial structures grown by molecular beam epitaxy is performed. The deformation state of the heteroepitaxial structures is investigated depending on the relative content of N in the Ga1-xNx buffer layer with the given thickness (=4 nm) and growth conditions. Using the extrapolating technique, the a- and c-lattice parameters, as well as the in-plane and out-of-plane strains (of the order of -10-3 and 10-4, respectively) are determined for GaN epilayers from θ-2θ x-ray diffraction spectra. For GaN epilayers, both the biaxial in-plane and in-depth strains (of the order of -10-3 and 10-3, respectively) and the hydrostatic strain component (of the order of -10-4) are extracted from the measured strains. It is supposed that the hydrostatic strain in the epilayers is caused by native point defects. The maximal level for the biaxial stress in the GaN epilayer, -1.3 GPa, is achieved for the sample with a relative content, x = 0.377, of N in the Ga1-xNx buffer layer.

The influence of the composition of the low-temperature GaN buffer layer on the structural, electrical, and optical properties of the subsequently grown GaN epilayer by molecular-beam epitaxy is investigated. It is found that decreasing the N/Ga flux ratio during the buffer layer growth yields excess Ga in the buffer layer. GaN epilayers grown on the buffer layer with excess Ga showed increased electron Hall mobility and reduced threading dislocation density. The tilt and twist disorders of the epilayer were also significantly reduced. The compressive stress in the epilayers at room temperature increased as the N/Ga flux ratio during the buffer layer growth was reduced. The improved properties of the epilayers are explained by the hypothesis that excess Ga in the buffer layer facilitates stress relaxation at the epilayer growth temperature.

Recessed Si/sub 0.8/Ge/sub 0.2/ source/drain (S/D) and a compressive contact etch-stop layer have been successfully integrated resulting in nearly 200% improvement in hole mobility. This is the largest reported process-induced hole mobility enhancement to the authors' knowledge. This letter demonstrates that a drive-current improvement from recessed Si/sub 0.8/Ge/sub 0.2/ plus the compressive nitride layer are in fact additive. Furthermore, it shows that the mobility enhancement is a superlinear function of stress, leading to larger than additive gains in the drive current when combining several stress sources.

We present a new etch chemistry that enables highly selective dry etching of germanium over its alloy with tin (Ge(1-x)Sn(x)). We address the challenges in synthesis of high-quality, defect-free Ge(1-x)Sn(x) thin films by using Ge virtual substrates as a template for Ge(1-x)Sn(x) epitaxy. The etch process is applied to selectively remove the stress-inducing Ge virtual substrate and achieve strain-free, direct band gap Ge0.92Sn0.08. The semiconductor processing technology presented in this work provides a robust method for fabrication of innovative Ge(1-x)Sn(x) nanostructures whose realization can prove to be challenging, if not impossible, otherwise.

Pseudomorphic GeSn layers with Sn atomic percentages between 4.5% and 11.3% were grown by chemical vapor deposition using digermane and SnCl4 precursors on Ge virtual substrates grown on Si. The layers were characterized by x-ray diffraction rocking curves and reciprocal space maps. Photoconductive devices were fabricated, and the dark current was found to increase with Sn concentration. The responsivity of the photoconductors was measured at a wavelength of 1.55 μm using calibrated laser illumination at room temperature and a maximum value of 2.7 mA/W was measured for a 4.5% Sn device. Moreover, the responsivity for higher Sn concentration was found to increase with decreasing temperature. Spectral photoconductivity was measured using Fourier transform infrared spectroscopy. The photoconductive absorption edge continually increased in wavelength with increasing tin percentage, out to approximately 2.4 μm for an 11.3% Sn device. The direct band gap was extracted using Tauc plots and was fit to a bandgap model accounting for layer strain and Sn concentration. This direct bandgap was attributed to absorption from the heavy-hole band to the conduction band. Higher energy absorption was also observed, which was thought to be likely from absorption in the light-hole band. The band gaps for these alloys were plotted as a function of temperature. These experiments show the promise of GeSn alloys for CMOS compatible short wave infrared detectors.

The development of a precise micromachining process for Ge1–xSnx has the potential to enable both the fabrication and optimization of Ge1−xSnx-based devices in photonics and microelectromechanical systems. We demonstrate a digital etching scheme for Ge0.922Sn0.078 based on a two-stage, highly selective CF4 plasma dry etch and HCl wet etch. Using X-Ray Reflectivity, we show consistent etch control as low as 1.5 nm per cycle, which is defined as one dry etch step followed by one wet etch step. The etch rate increases to 3.2 nm per cycle for a longer dry etch time due to physical sputtering contributions, accompanied by an increase in RMS surface roughness. By operating within a regime with minimal sputtering, we demonstrate that good digital etch depth control and surface quality can be achieved using this technique.

Strain technology has been a key enabler for improving transistor performance in the past decade. Recently a question has arisen whether stressors will maintain their effectiveness with continued reduction in stressor volume as transistor pitch scales. Also which stressors will be most effective as the industry moves from planar to FinFET transistors? In this paper we present a holistic view on scalability of strain technology. TCAD models are calibrated with experimental data to project the scalability. Figure 1 highlights the key differences in strain engineering moving from planar to FinFET devices. Depth profile of stress, additional transverse stress due to metal fills for contact and gate stack which wrap around the fin and stress response along different surface orientation becomes important (Table.1) as transport now happens along the sidewalls vs. just the top surface. In this paper we study the effect of (a) S/D epitaxy : SiGe for PMOS and Si:C for NMOS (b) Gate metal fill which wraps around the fin (e.g. TiN/W fill) (c) Metal fill for the trench contact (e.g. W) and (d) STI fill (Figure 2). Stress from etch stop liner is known to be not effective in FinFET architecture [1–2] and is not examined in this study.

Selective Epitaxy technology with phosphorous and/or carbon addition for advanced nMOS has several advantages - to enhance tensile stress, lower series resistance, and block the diffusion of phosphorous [1][2][3]. pMOS strained SiGe process is now mainstream and well characterized. However, the nMOS Epitaxy process has several challenging process requirements, especially related to resistivity (with/without Carbon), film selectivity, and defect control. Lower film deposition temperatures can help reduce film resistivity, however, selectivity, defectivity, and growth rates are compromised. Cyclic deposition and etch processes are typically required to recover film selectivity and growth rates. Cyclic process contains a non-selective deposition step to optimize the film resistivity/carbon concentration and an etch step to optimize morphology and selectivity. Various process parameters are explored in this paper to achieve in-situ phosphorus doped selective Epi with low resistivity and defect free microstructure.

Segmented-channel Si 1−x Ge x /Si pMOSFETs are fabricated using a conventional process, starting with a corrugated Si 1−x Ge x /Si substrate. As compared with control devices fabricated using the same process but starting with a non-corrugated Si 1−x Ge x /Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher I ON for I OFF =10 nA per µm layout width) due to enhanced hole mobility, and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.

The quasi-planar segmented-channel MOSFET (SegFET) design provides an evolutionary pathway for continued CMOS technology scaling, and can be fabricated using a conventional process flow starting with a corrugated substrate. It has been shown previously that the SegFET exhibits better short channel behavior compared to the conventional MOSFET. Recently, we have demonstrated further performance enhancement using mobility enhancement techniques such as using silicon-germanium as the channel material. This paper discusses the selective epitaxial growth of Si and SiGe layers to form corrugated-Si/SiGe substrates for enhanced p-channel SegFET performance.

In this study, we investigated the effects of the dimensional scaling of n-channel field-effect transistors on the channel strain. We employed nanobeam diffraction to independently determine the effects of scaling of two major transistor dimensions (gate and source/ drain length) on the channel strain. Both these parameters influenced the channel strain, but in the opposite directions: the channel strain increased with the gate length decreasing, while declining with the reduction of the source/ drain length. Using device simulation, we also considered the combined effects of all the main scaling factors, disclosing that the strain decreased with the reduction of the dimensions.

Gallium nitride epitaxial layers were grown on sapphire by molecular-beam epitaxy using nitridated gallium metal films as buffer layers. The mechanical properties of the buffer layers were investigated and correlated with their chemical composition as determined by synchrotron radiation photoelectron spectroscopy. Biaxial tension experiments were performed by bending the substrates in a pressure cell designed for simultaneous photoluminescence measurements. The shift of the excitonic luminescence peak was used to determine the stress induced in the main GaN epilayer. The fraction of stress transferred from substrate to main layer was as low as 27% for samples grown on nitridated metal buffer layers, compared to nearly 100% for samples on conventional low-temperature GaN buffer layers. The efficiency of stress relief increased in proportion to the fraction of metallic Ga in the nitridated metal buffer layers. These findings suggest GaN films containing residual metallic Ga may serve as compliant buffer layers for heteroepitaxy.

For the first time, high performance Ge nMOSFET is fabricated using laser annealing of ion-implanted antimony (Sb) dopants which provides donor activation beyond 1×1020cm−3 in germanium. Record I on /I off > 105 is demonstrated for n+/p junctions combined with significant reduction of contact resistance to 7×10−7 Ω-cm2. Performance projections for ITRS HP 22nm technology node are also discussed.

For the first time, ultra shallow junctions (x j 1×1020 cm−3) is achieved for all dopant atoms (P/As/Sb/B) using Laser Thermal Processing. We also show ultrathin (0.6nm), high quality GeO 2 interfacial layer for gate dielectric, which provides substrate orientation independent D it and mobility enhancement for Ge high-k N/P MOSFETs.

The effect of phosphorus implantation and thermal annealing on properties of Si:C epitaxial films was investigated. High resolution x-ray diffraction analysis and secondary ion mass spectroscopy indicated that spike annealing only causes slight loss of substitutional carbon. Phosphorus implantation, even with low energy, could cause surface damages and loss of substitutional carbon. Although spike annealing effectively activates implanted phosphorus, it also results in significant substitutional carbon loss (from 1.2% to less than 0.5%) within the phosphorus diffused layer. The interaction of carbon and phosphorus resulted in a junction profile as abrupt as with 3 nm/decade.