Search

Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the and directions showing different transport properties.

In this paper, we present results and discuss issues related to implementation of large scale circuits in extremely thin (ET) SOI CMOS for low power applications. We have demonstrated that we can fabricate low power (LP) CMOS with centered Vts and good Vt uniformity across wafer and wafer to wafer. Using this CMOS, we have fabricated low leakage and high performance ring oscillators (with delay ∼20% faster than the standard 28 nm LP bulk). We have also obtained perfect 2.25M SRAM arrays, functioning down to Vdd of 0.5V, and we have shown that a 10-level BEOL process has minimal impact on device stability.

This paper presents performance evaluation of high-κ/metal gate (HK/MG) process on an industry standard 45nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45nm Poly/SiON devices. No additional stress elements were used for this performance gain. The critical path circuits of this low power microprocessor built with HK/MG show dynamic performance gain over 50% at same supply voltage and 36% lower dynamic energy at same performance. Superior SRAM minimum operating voltage characteristics are achieved due to Vt variability reduction from HK/MG. Analog circuit functionality is demonstrated by a fully integrated PLL circuitry without any modification to process.

The intrinsic FinFET device structure can provide an estimated 10–20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Ω-um.

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (Csub) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced Ieff and ~15% improved Idlin against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the stress memory technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects strain transfer.

Various local stress techniques have been integrated on strained-Si directly on insulator (SSDOI) substrates, including dual stress liner (DSL), stress memory technique (SMT), and embedded SiGe (eSiGe) in source/drain. SMT shows mild drive current enhancement on nFETs. PFETs with eSiGe exhibit significant enhancement, suggesting eSiGe compatibility with SSDOI is excellent. A ring oscillator delay of 3ps is achieved at leakage current of 1 muA/mum and VDD=1.1V

CMOS devices with embedded SiGe source/drain for pFETs and tensile stressed liner for nFETs have been demonstrated for the first time on hybrid orientation substrates. Ring oscillators have also been fabricated. Significant performance improvement is observed in hybrid orientation substrates compared to (100) control substrates with embedded SiGe.

Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I/sub DSat/ at 100 nA/um I/sub OFF/ for V/sub DD/=1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from [110] silicon and an additional 8% benefit due to the compressive MOL film.

The scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported. SGOI NFET enhancement exhibits only moderate channel length dependence down to sub-50 nm regime, indicating strain-induced enhancement can be sustained in future technology nodes. This is contrary to some previous reports which suggested dramatic reduction of strain-induced NFET current enhancement with channel length scaling. A novel analysis technique was developed to account for the difference in self-heating in SGOI and SOI devices to enable intrinsic device performance comparison. Additive effects of biaxial strain from the Si/SiGe heterostructure and process-induced uniaxial stress are experimentally demonstrated for the first time.

The ultra-thin SOI (UTSOI) device is an attractive choice for sub-10 nm gate-length scaling. In this work the major issues for UTSOI are addressed. External resistance is minimized by using the raised extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel. The REX process scheme is used to demonstrate improved pFET performance and also to demonstrate the first planar single gate nFET with 8 nm gate-length. High temperature mobility measurements show that the channel thickness can be scaled further than previously predicted. UTSOI devices with tungsten gates and HfO/sub 2/ gate dielectrics having appropriate threshold voltages are presented for the first time.

Integration of strained Si and high-K gate dielectric is demonstrated for the first time. While providing a >1000/spl times/ gate leakage reduction, strained Si NMOSFETs with HfO/sub 2/ gate dielectric exhibit 60% higher mobility than the unstrained Si device with HfO/sub 2/ gate dielectrics, and 30% higher mobility than the conventional Si NMOSFETs with SiO/sub 2/ gate dielectric (universal MOSFET mobility).

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.

Planar double gate CMOS devices with thin silicon channels and electrically separate polysilicon top and bottom gates are fabricated. NFETs with L/sub design/=175 nm and 1.3 mA//spl mu/m and PFETs with L/sub design/=125 nm and 400 /spl mu/A//spl mu/m are achieved at V/sub dd/=1.2 V. To our knowledge, this is the largest current yet achieved in double gate NMOS devices. Electrical results show a high quality backgate dielectric, improvement of SCE using the backgate, and the importance of reducing external resistance in short channel devices.

Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show |V/sub t/|/spl sim/0.1 V, with off-currents less than 100 nA/um at V/sub gs/=0.