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The recent discovery of ferroelectricity in thin hafnium oxide films has led to a resurgence of interest in ferroelectric memory devices. Although both experimental and theoretical studies on this new ferroelectric system have been undertaken, much remains to be unveiled regarding its domain landscape and switching kinetics. Here we demonstrate that the switching of single domains can be directly observed in ultrascaled ferroelectric field effect transistors. Using models of ferroelectric domain nucleation we explain the time, field and temperature dependence of polarization reversal. A simple stochastic model is proposed as well, relating nucleation processes to the observed statistical switching behavior. Our results suggest novel opportunities for hafnium oxide based ferroelectrics in nonvolatile memory devices.

With the discovery of ferroelectric hafnium oxide (FE-HfO2), the ferroelectric field effect transistor (FeFET), a long-term contender for non-volatile data storage, has finally managed to scale to the 2× nm technology node. Here for the first time, we correlate the thickness dependent ferroelectric properties of Si:HfO2 with the memory characteristics of small (56 bit) FeFET arrays. First, an electrical and structural analysis of metal-ferroelectric-metal capacitors is given. Even though possessing room-temperature deposited top electrodes, TiN / Si:HfO2 (20 nm) / TiN capacitors are showing deteriorated polarization characteristics as compared to their 10 nm Si:HfO2 counterparts. This could be attributed to an increased monoclinic phase fraction, as indicated by small-signal capacitance voltage and grazing incidence X-ray diffraction measurements. Identical Si:HfO2 thin films with thicknesses of 10 nm and 20 nm respectively, were utilized in a 28 nm high-k metal-gate CMOS flow to form small FeFET ...

One of the key challenges in the development of embedded memory solutions is to ensure their compatibility to CMOS processing and to reduce the added complexity to a minimum. Especially the parallel implementation of charge based one-transistor memories in the FEoL, such as e.g. floating gate devices, together with advanced transistor technologies proves rather challenging. In contrast to that, an alternative one-transistor memory concept based on ferroelectric hafnium oxide closely resembles state of the art high-k metal gate devices and therewith promises a greatly simplified integration. Here we investigate the impact of strain, thermal budget and work function engineering, usually applied to high-k metal gate technologies, on material properties as well as on the memory performance of hafnium oxide based ferroelectric field effect transistors. Key challenges related to a modified gate etch and the integration of different hafnium oxide thicknesses will be discussed.

The discovery of ferroelectricity in HfO 2 and ZrO 2 based dielectrics enabled the introduction of these materials in highly scalable non-volatile memory devices. Typical memory cells are using a capacitor or a transistor as the storage device. These scaled devices are sensitive to the local structure of the storage material, here the granularity of the dielectric doped HfO 2 layer, varying the local ferroelectric properties. Detailed studies are conducted to correlate these structural properties to the electrical performance to further optimize the devices for future applications.

Recent discovery of ferroelectricity in HfO2 thin films paved the way for demonstration of ultra-scaled 28 nm Ferroelectric FETs (FeFET) as non-volatile memory (NVM) cells [1]. However, such small devices are inevitably sensible to the granularity of the polycrystalline gate oxide film. Here we report for the first time the evidence of single ferroelectric (FE) domain switching in such scaled devices. These properties are sensed in terms of abrupt threshold voltage (VT) shifts leading to stable intermediate VT levels. We emphasize that this feature enables multi-level cell (MLC) FeFETs and gives a new perspective on steep subthreshold devices based on ferroelectric HfO2.

Strain greatly affects the electrical properties of silicon because strain changes the energy band structure of silicon. In MOSFET devices, the terminal voltages induce electrical fields, which themselves modulate the electronic band structure and interact with strain-induced changes. Applied electrical fields are used to experimentally study different state-of-the-art local and global strain techniques and reveal the different responses of n- and p-MOSFETs to the different strain techniques. It is shown that p-MOSFETs have more low-lateral-field linear drive-current enhancement and less high-lateral-field saturation drive-current enhancement at both low and high vertical fields. The situation is similar for n-MOSFETs at low vertical fields. However, at high vertical fields, n-MOSFET low-lateral-field linear drive-current enhancement is less than the high-lateral-field saturation drive-current enhancement. The origin for this behavior can be found in the different strain effects on the electronic band structure, which results in effective mass reduction and/or scattering suppression. These, in turn, contribute differently to linear and saturation drive-current enhancements in n- and p-MOSFETs.

Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed.

We present here the substitutional carbon dependence of ClusterCarbon implant energy and dose, and anneal parameters such as solid phase epitaxial regrowth (SPER) temperature and various high temperature millisecond flash anneal conditions. With a multiple implant sequence of carbon implants one can obtain a fairly uniform carbon profile and we show that it provides better carbon substitution [C]sub when compared to a single implant. It is been established that optimizing the percentage of [C]sub requires an SPER anneal temperature 2%. For a given millisecond anneal and for implants with various energies and doses we show that the percentages of [C]sub increases linearly with the fraction of carbon dopants within the amorphous layer.

Strain engineering in MOSFETs using tensile nitride overlayer (TOL) films, compressive nitride overlayer (COL) films, and embedded-SiGe (eSiGe) is studied by extensive device experiments and numerical simulations. The scaling behavior was analyzed by gate length reduction down to 40 nm and it was found that drive current strongly depends on the device dimensions. The reduction of drain-current enhancement for short-channel devices can be attributed to two competing factors: shorter gate length devices have increased longitudinal and vertical stress components which should result in improved drain-currents. However, there is a larger degradation from external resistance as the gate length decreases, due to a larger voltage dropped across the external resistance. Adding an eSiGe stressor reduces the external resistance in the p-MOSFET, to the extent that the drive current improvement from COL continues to increase even down the shortest gate length studied. This is due to the reduced resistivity of SiGe itself and the SiGe valence band offset relative to Si, leading to a smaller silicide-active contact resistance. It demonstrates the advantage of combining eSiGe and COL, not only for increased stress, but also for parasitic resistance reduction to enable better COL drive current benefit.

In recent years, and with the discovery of ferroelectricity in hafnium oxide, it was possible to scale down ferroelectric memory cells in both transistor and capacitor configurations. This study reports the latest advances for FE-HfO 2 -based memory cells and arrays. For the 1T FeFET memory approach, retention in the range of 10 µs up to 104 seconds was measured both after 102 and 104 endurance cycles. At room temperature, memory windows of 0.8 V and 0.7 V were extrapolated to ten years respectively. Moreover, a novel operating scheme for a 1T FeFET AND architecture is presented allowing for true random access operation of the array. With respect to capacitor-based memory cells, high aspect ratio ferroelectric trench capacitors are demonstrated which show proper memory characteristics up to 105 cells in parallel. In order to bring these concepts closer to commercialization, device statistics of larger amounts of memory cells have to be provided. For the first time, the functionality of small FeFET memory arrays is shown and the statistical distribution of memory characteristics is analyzed. We provide evidence that with the proper choice of material composition, device size and operating conditions, the realization of memory products utilizing HfO 2 -based FeFET arrays seems viable in the future.

A simple and unified fundamental theory on the mechanism of stress memorization technique (SMT) is presented for the first time. This theory is based on the difference in thermal properties of the materials involved in SMT process, i.e., silicon (channel), polysilicon (gate), amorphous silicon (source/drain), SiO2 (gate oxide), as well as Si3N4 (SMT nitride stressor layer), which lead to deformations during thermal anneal and SMT. This theory accounts for all the results published to date in SMT and provides important physical insights. As a demonstration of predictive capability of this theory, a 45-nm process was modified using a novel anneal sequence which raises the stress in the channel. The experimental data after the change yield additional 5% performance boost for NFET compared to a baseline SMT process.

Ferroelectrics are very interesting materials for nonvolatile data storage due to the fact that they deliver very low power programming operation combined with nonvolatile retention. For 60 years researchers have been inspired by these fascinating possibilities and have tried to build ferroelectric memory devices that can compete with mainstream technologies in their respective time. The progress of the current concepts is limited by the low compatibility of ferroelectrics like PZT with CMOS processing. Therefore, PZT or SBT based 1T1C ferroelectric memories are not scaling below 130 nm and 1T ferroelectric FETs based on the same materials are still struggling with low retention and very thick memory stacks. Hafnium oxide, a standard material in sub 45 nm CMOS, can show ferroelectric hysteresis with promising characteristics. By adding a few percent of silicon and annealing the films in a mechanically confined manner. Boescke et al. demonstrated ferroelectric hysteresis in hafnium oxide for the first time. Recently, a large number of dopants including Y, Al, Gd and Sr have been used to induce ferroelectricity in HfO2. This paper reviews the current status of hafnium oxide based ferroelectrics, its application to field effect transistors and puts this approach into a wider context of earlier developments in the field.

Different gate stack optimizations and substrate dependent strain interactions have been studied and implemented in a cost-effective 28nm VLSI ultra low power technology. Drive current improvements for NFET ID,SAT = 870μA/μm and PFET ID,SAT = 465μA/μm at IOFF = 1nA/μm and VDS = 1V can be demonstrated by using compressive and tensile contact layers on (100)/ substrates. Work function optimizations result in a proper threshold voltage adjustment and improved reliability behavior for 28nm ultra low power technologies. SOC level test design implementations show consistent yield as well as improved performance.

This 3-D TCAD study demonstrates a new stress element by strained isolation oxide for Tri-Gate and similar FinFET structures. The simulation shows an uniform improvement of N- and PMOS drive current (10 %) by using a tensile strained isolation material between the fins processed on standard (100) bulk wafer with channel direction. Therefore it is a simple low-cost stress method for Tri-Gate and FinFET structures of 22nm technologies and beyond. The main stress direction is located along the channel width with a maximum near the pn-junctions. The stress effect can be improved further with reduced gate length which shows the compatibility of strained isolation oxide to future transistor generations.

The impact of compressive and tensile stress on CMOS performance is studied for and oriented silicon and SiGe channels. The channel direction is found to be more stress sensitive whereas the oriented transistor has a higher initial hole mobility. These results recommend to use the channel orientation for high performance application due to the high drive current gain and channel orientation for low power applications where no stress elements are included to ease the overall process complexity and to decrease costs.

For future scaling to the end of the ITRS roadmap, novel structures like FinFETs are required to improve electrostatic integrity of MOSFETs with gate lengths shorter than 35 nm [1–4]. Classic fully-depleted FinFETs with a high aspect ratio are not compatible with existing planar process flows. A Tri-Gate transistor has the advantage of being more compatible. It is even possible to produce low-profile Tri-Gates in parallel to planar MOSFETs [5], with shared Tri-Gate and planar implants and common-use of source/drain epi and dual band-edge metal gate workfunctions. This maintains the design flow, saves mask count, allows reuse of analog and high-voltage I/O designs, while exploiting Tri-Gates in high speed logic and low minimum voltage.

A hybrid Tri-Gate/planar process was investigated by 3-D process and device simulations. Electrostatics of a Tri-Gate and a planar transistor sharing the same well, halo, and S/D have been compared. The suppression of the Tri-Gate corner effect was studied by corner implantation and additional corner rounding after Tri-Gate fin formation. Corner implantation is useful for retargeting Tri-Gate threshold voltage independent of shared planar implantation settings. Corner rounding allows a reduction of electric field overlap, suppressing corner leakage path and improve I ON -I OFF performance.

A Tri-Gate structure built into a planar 22 nm bulk process was investigated by 3-D device simulations (Sentaurus D-2010). The planar process flow sequence was extended with extra Tri-Gate patterning, but otherwise all implants were shared, as could be done in simultaneous processing of planar and Tri-Gate CMOS. A comparison of planar and Tri-Gate transistors with the same planar dopant profiles shows a substantial improvement of subthreshold slope, DIBL, and V T -rolloff for Tri-Gates. The electrical behavior of the Tri-Gate transistor has been studied for various Tri-Gate heights and widths. A large space of Tri-Gate dimensions outperformed planar in terms of electrostatics and I ON -I OFF characteristics.

Biaxial tensile strained substrates offer strong electron mobility enhancements resulting in large drive current gains. For short channel n-MOSFETs, however, these improvements diminish. Root causes for this performance degradation are investigated through experiments and simulations. Elastic stress relaxation arising from shallow trench isolation (STI) is found to be negligible for current state-of-the-art transistors. On the other hand, parasitic source/drain resistance seems to be responsible for the limitation of drain current gains in deeply scaled devices. This effect is even further aggravated by an increased parasitic source/drain resistance in sSOI devices compared to standard SOI.

Due to the continuous CMOS transistor scaling requirements, millisecond annealing has been introduced in 45 nm CMOS technology to enhance dopant activation with minimal dopant diffusion. This paper considers two different ultra fast annealing technologies as alternative to the conventional rapid thermal annealing strategy for the 32 nm node. We compared a long wavelength non-melt laser spike annealing and a flash lamp annealing in terms of CMOSFET device performance. We also investigated possible temperature variations induced by shallow trench isolation density variations of these two annealing techniques by means of electrical parameters. The comparison was made without the introduction of an absorbent layer to take into account the different absorption mechanism between laser spike annealing and flash lamp annealing. The results show that both approaches despite their different annealing techniques are full comparable in terms of device performance without any concerns in pattern effects at least for SOI-CMOSFETs and therefore equal useable for the 32 nm node and beyond.

Silicon germanium (SiGe) is considered to substitute silicon (Si) as channel material of p-type MOSFET in future CMOS generations due to its higher hole mobility. In this work we investigate SiGe channels with a germanium concentration of 23 at% and 30 at%, even though the mobility is expected to be higher with even more germanium in the alloy. Low pressure chemical vapor deposition was used for SiGe deposition. A state of the art CMOS process including high-k dielectric and metal gate electrode was applied for fabrication of sub 50 nm gate length devices. As expected from the SiGe channel conduction and valence band offset the threshold voltage of the devices is influenced. The gate stack was directly deposited onto the SiGe layer consisting of a chemically grown base oxide, hafnium-based dielectric and titanium nitride gate electrode. C-V and I-V measurements show comparable CET and leakage values for the high-k metal gate stack on Si and SiGe channels. The trap density at the channel dielectric interface was determined using the charge pumping technique. The device characteristics of n- and p-MOSFETs with SiGe channels are compared to conventional Si channel devices. Short channel mobility was extracted with the gM,LIN-Method.

System on chip (SoC) embedded memory solutions promise small form factors and high operating speed, as well as a high energy and cost efficiency. Single cell scalability and basic memory parameters such as data retention, cycling endurance and disturb characteristics on array level are important aspects in stand-alone memory development and can serve as a guideline for embedded solutions. However, one of the key aspects in embedded memory development is compatibility of the memory technology to its underlying complementary metal oxide semiconductor (CMOS) platform. This includes the voltage requirements for logic and memory operation, the need for additional lithographic steps and minimally CMOS invasive integration efforts, as well as the introduction of new materials and related contamination concerns. Especially in state of the art high-k metal gate (HKMG) CMOS technologies at minimum feature size (F) these aspects proof rather challenging when searching for a suitable embedded memory solution. As a consequence most approaches result in large memory cells of multiple F2 or leave a BEoL integration of the memory cell as the only viable option. With the introduction of ferroelectric hafnium oxide, however, a scalable one-transistor (1T) memory solution derived from the conventional HKMG transistor was presented for the 2X nm node. The therewith close resemblance of the memory and logic transistor appears ideally suited for combining nonvolatile data storage and logic circuitry on the same chip. Nevertheless, in order to fulfill these expectations and to ease manufacturing issues this resemblance has to be as close as possible. In the context of a minimally invasive memory integration strategy this means that ideally the ferroelectric hafnium oxide based memory transistor has to adapt to the HKMG transistor in terms of thermal budget and post treatments, vertical and lateral dimensions, the use of stress engineering, as well as metal gate and work function engineering. Based on experimental gate first transistor and metal insulator metal (MIM) capacitor data these aspects together with embedded memory requirements will be analyzed and critically discussed.

This article shows the importance of source/drain extension dopant species on the performance of embedded silicon-germanium strained silicon on insulator p-metal oxide semiconductor field effect transistor (MOSFET) devices, in which the activation was done using only high temperature ultrafast annealing technologies. BF2 and boron were investigated as source/drain extension dopant species. In contrast to unstrained silicon p-MOSFETs, boron source/drain extension implantations enhance device performance significantly compared to devices with BF2 source/drain extension implantations. Measurements show a 30% mobility enhancement and lower external resistance for the devices with boron source/drain extension implantations. The reason for this lies in the amorphization nature of BF2 implantations. Remaining defects after implant annealing affect the stress transfer from the embedded silicon-germanium and the overall hole mobility which leads to the observed performance degradation. Furthermore, TCAD simulation...

Asymmetric halo and extension implantations are examined by simulation for their usability in 45 and 32 nm technology high performance silicon on insulator metal oxide semiconductor field effect transistors (SOI-MOSFETs). Tilted halo and extension implantations from the source side show higher saturation currents and lower drain overlap and junction capacitances, which improve the intrinsic MOSFET power delay product. Furthermore the asymmetric doping profile leads to an inverter chain speed benefit. The stronger short channel effect, present in these devices, can be reduced by a low dose drain side halo implantation simultaneously maintaining a transistor performance improvement from asymmetric doping. This optimized transistor design is successfully transferred from the 45 into the 32 nm technology.

Strained silicon techniques have become an indispensable technology feature, enabling the momentum of semiconductor scaling. Embedded silicon-germanium (eSiGe) is already widely adopted in the industry and delivers outstanding p-metal oxide semiconductor field effect transistor (MOSFET) performance improvements. The counterpart for n-MOSFET is embedded silicon-carbon (eSi:C). However, n-MOSFET performance improvement is much more difficult to achieve with eSi:C due to the challenging process integration. In this study, detailed TCAD simulations are employed to compare the efficiency of eSiGe and eSi:C stressors and to estimate their potential for performance enhancements in future nanoscaled devices with gate lengths down to 20 nm. It is found that eSiGe as a stressor is superior to eSi:C in deeply scaled and highly strained devices due to its easier process integration, reduced parasitic resistance, and nonlinear effects in the silicon band structure, favoring hole mobility enhancement at high strain levels.

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