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The influence of intercell trapped charge (ITC)-the charge trapped at the inter-cell nitride regions by fringe electric fields during program and erase operations-on vertical NAND (VNAND) flash memory is investigated. In addition to conventional degradation mechanisms such as tunnel oxide damage, ITC deteriorates the transconductance and read current of VNAND flash memory cells. The influence of ITC-induced degradation on VNAND flash memory is discussed, using both simulation and experimental results. A solution for ITC suppression is also proposed: the use of low-k intercell regions.

We report on top-gate OFETs with a bilayer gate dielectric comprising an Al2O3 /HfO2 nanolaminate layer grown by atomic layer deposition and an amorphous fluoro-polymer layer (CYTOP). Top-gate OFETs display average carrier mobility values of 0.9 ± 0.2 cm2/(V s) and threshold voltage values of −1.9 ± 0.5 V and high operational and environmental stability under different environmental conditions such as damp air at 50 °C (80% relative humidity) and prolonged immersion in water at a temperature up to 95 °C.

We report on self-forming electrode modification by mixing 2,3,4,5,6-pentafluorothiophenol (PFBT) directly into the solution of the organic semiconductor prior to film formation on top of existing metal electrodes. During the formation of the semiconductor layer from the mixed solution, PFBT chemisorbs on the underlying source/drain electrodes and modifies their electronic properties. The modification of evaporated silver, gold, or printed silver electrodes with PFBT is analyzed by X-ray photoelectron spectroscopy. The use of this self-forming electrode modification is applied to solution-processed p-channel top-gate 6,13-bis(triisopropylsilylethynyl)pentacene/poly[bis(4-phenyl) (2,4,6-trimethylphenyl) amine] organic field-effect transistors (OFETs) that comprise bare silver or gold source/drain electrodes. The proposed new method simplifies device fabrication while yielding OFETs with a performance level that is comparable to that of reference devices in which the metal electrodes are modified with PFBT prior to the fabrication of the semiconductor layer.

We report on a reverse stamping method to produce via-holes in circuits comprising acene-based top-gate organic field-effect transistors (OFETs) having a CYTOP/Al2O3 (by atomic layer deposition) bilayer gate dielectric. This method relies on the weak adhesive force that exists between a small molecule acene film and a polymer to enable easy delamination of the bilayer gate dielectric by using a PDMS stamp. We demonstrate the effectiveness of this method by fabricating simple circuits using top-gate triisopropylsilylethynyl pentacene (TIPS-pentacene)/poly (triarylamine) (PTAA) OFETs.

The use of organic field-effect transistors (OFETs) as sensors in aqueous media has gained increased attention for environmental monitoring and medical diagnostics. However, stable operation of OFETs in aqueous media is particularly challenging because of electrolytic hydrolysis of water, high ionic conduction through the analyte, and irreversible damage of organic semiconductors when exposed to water. To date, OFET sensors have shown the capability of label-free sensing of various chemical/biological species, but they could only be used once because their operational stability and lifetime while operating in aqueous environments has been poor, and their response times typically slow. Here, we report on OFETs with unprecedented water stability. These OFETs are suitable for the implementation of reusable chemical/biological sensors because they primarily respond to charged species diluted in an aqueous media by rapidly shifting their threshold voltage. These OFET sensors present stable current baselines and saturated signals which are ideal for detection of low concentration of small or large molecules that alter the pH of an aqueous environment. The overall response of these OFET sensors paves the way for the development of continuous chemical/biological nondestructive sensor applications in aqueous media.

In this talk, we will discuss recent advances in the science and engineering of organic light-emitting diodes (OLEDs). First, we will focus on materials in which light emission involves the process of thermally activated delayed fluorescence (TADF). In these materials, triplet excited states can convert into optically emissive singlet excited states by reverse intersystem crossing, allowing for nearly 100% internal quantum efficiency. This process can be used to design a new class of materials that are all organic, offering a lower cost alternative to conventional electrophosphorescent materials that contain heavy and expensive elements such as Pt and Ir. We will discuss molecular design strategies and present examples of materials that can be used as emitters or hosts in the emissive layer. In a second part of this talk, we will review recent progress in fabricating OLEDs on shape memory polymer substrates (SMPs). SMPs are mechanically active, smart materials that can exhibit a significant drop in modulus once an external stimulus such as temperature is applied. In their rubbery state upon heating, the SMP can be easily deformed by external stresses into a temporary geometric configuration that can be retained even after the stress is removed by cooling the SMP to below the glass transition temperature. Reheating the SMP causes strain relaxation within the polymer network and induces recovery of its original shape. We will discuss how these unique mechanical properties can also be extended to a new class of OLEDs.

Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

A novel three-dimensional (3D) Dual Control gate with Surrounding Floating gate (DC-SF) NAND flash cell has been successfully developed. The DC-SF cell consists of a surrounding floating gate with stacked dual control gates. With this structure, high coupling ratio, low voltage cell operation, and wide P/E window (9.2 V) can be obtained. Moreover, negligible FG–FG coupling interference (12 mV/V) is achieved due to the control-gate shield effect. As a result, DC-SF NAND flash cell can overcome the problems of SONOS-based 3D NAND flash. It is proposed that 3D DC-SF NAND flash cell is the most promising candidate for 1 Tb and beyond, with stacked multi bit FG cell (2–4 bits/cell).

We report on the reduction of contact resistance in solution-processed TIPS-pentacene (6,13-bis(triisopropylsilylethynyl)pentacene) and PTAA (poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine]) top-gate bottom-contact organic field-effect transistors (OFETs) by using different contact-modification strategies. The study compares the contact resistance values in devices that comprise Au source/drain electrodes either treated with 2,3,4,5,6-pentafluorothiophenol (PFBT), or modified with an evaporated thin layer of the metal-organic molecular dopant molybdenum tris-[1,2-bis(trifluoromethyl)ethane-1,2-dithiolene] (Mo(tfd)3), or modified with a thin layer of the oxide MoO3. An improved performance is observed in devices modified with Mo(tfd)3 or MoO3 as compared to devices in which Au electrodes are modified with PFBT. We discuss the origin of the decrease in contact resistance in terms of increase of the work function of the modified Au electrodes, Fermi-level pinning effects, and decrease of bulk resistance by electrically doping the organic semiconductor films in the vicinity of the source/drain electrodes.

Solution-based electrical doping protocols may allow more versatility in the design of organic electronic devices; yet, controlling the diffusion of dopants in organic semiconductors and their stability has proven challenging. Here we present a solution-based approach for electrical p-doping of films of donor conjugated organic semiconductors and their blends with acceptors over a limited depth with a decay constant of 10-20 nm by post-process immersion into a polyoxometalate solution (phosphomolybdic acid, PMA) in nitromethane. PMA-doped films show increased electrical conductivity and work function, reduced solubility in the processing solvent, and improved photo-oxidative stability in air. This approach is applicable to a variety of organic semiconductors used in photovoltaics and field-effect transistors. PMA doping over a limited depth of bulk heterojunction polymeric films, in which amine-containing polymers were mixed in the solution used for film formation, enables single-layer organic photovoltaic devices, processed at room temperature, with power conversion efficiencies up to 5.9 ± 0.2% and stable performance on shelf-lifetime studies at 60 °C for at least 280 h.

Active matrix organic light-emitting diode (AMOLED) displays are fabricated from polycrystalline silicon, which is formed in the single and double (overlap) scanned area during the excimer laser annealing (ELA) process. A redundant pixel line (RPL) design is proposed to remove the overlapping mura and, as a result, a 5-in AMOLED display is successfully fabricated without any non-uniform line image on the overlapping scanned area. This result indicates that the fabrication of a large-sized AMOLED panel is possible using ELA crystallization through an RPL design.

Simultaneous Emission with Active Voltage control (SEAV) is a strong candidate for crosstalk-free driving of 3D Active Matrix Organic Light Emitting Diode (AMOLED) displays. A gate driver for a SEAV 3D AMOLED panel needs two operating modes: the simultaneous switching mode and the progressive scanning mode. However, conventional gate drivers can operate in only progressive scanning mode. In this paper, a new integrated gate driver to support both of these modes is proposed and applied to a prototype 3D AMOLED display panel.

An advanced method for externally compensating the nonuniform electrical characteristics of polycrystalline silicon thin-film transistors (TFTs) and the degradation of organic light-emitting diode (OLED) devices is proposed, and the method is verified using a 14.1-in active matrix OLED (AMOLED) panel. The proposed method provides an effective solution for high-image-quality AMOLED displays by removing IR-drop and temperature effects during the sensing and displaying operations of the external compensation method. Experimental results show that the electrical characteristics of TFTs and OLEDs are successfully sensed, and that the stained image pattern due to the nonuniform luminance error and the differential aging of the OLED is removed. The luminance error range without compensation is from -6.1% to 9.0%, but it is from -1.1% to 1.2% using the external compensation at the luminance level of 120 cd/m2 in a 14.1-inch AMOLED panel.

Effects of high-pressure wet vapor annealing (HPWA) on the memory properties of Metal/Alumina/Nitride/Oxide/Silicon (MANOS)-type flash memory devices are studied. The Oxide/Nitride/Alumina (ONA) stacks were annealed in a high-pressure wet vapor ambient (N"2:D"2O=10 atm:2 atm) at 250 ^oC for 5 min. It is found that HPWA can effectively passivate the intrinsic defects of the Al"2O"3 film by oxygen species, leading to the improvement of blocking efficiency. The HPWA significantly improved the electrical and reliability characteristics of ONA stacks, such as leakage current density, saturation level of erase, charge loss rate through the blocking oxide, and memory window after the program and erase cycles. HPWA shows promise for future MANOS-type flash memory devices.

We demonstrate top-gate organic field-effect transistors (OFETs) with a bilayer gate dielectric and doped contacts fabricated on shape-memory polymer (SMP) substrates. SMPs exhibit large variations in Young’s modulus dependent on temperature and have the ability to fix two or more geometric configurations when a proper stimulus is applied. These unique properties make SMPs desirable for three-dimensional shape applications of OFETs. The electrical properties of OFETs on SMP substrates are presented and compared to those of OFETs on traditional glass substrates.

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal-glycerol (CNC/glycerol) substrates. These OFETs exhibit low operating voltage, low threshold voltage, an average field-effect mobility of 0.11 cm(2)/(V s), and good shelf and operational stability in ambient conditions. To improve the operational stability in ambient a passivation layer of Al2O3 is grown by atomic layer deposition (ALD) directly onto the CNC/glycerol substrates. This layer protects the organic semiconductor layer from moisture and other chemicals that can either permeate through or diffuse out of the substrate.

Silicon nanocrystals (Si-NCs) embedded in a silicon nitride (SiN) layer were fabricated as a charge trapping layer for nonvolatile memory (NVM) device applications. Nano-scale memory characteristics were investigated using conductive atomic force microscopy (C-AFM) and a semiconductor parameter analyzer. Nano-scale memory characteristics of Si-NCs embedded in the SiN layer were obtained from the shift of the current–voltage (I–V) curve. Charge trapping/detrapping and multi-level charge storage in Si-NCs embedded in the SiN layer were obtained at a metal–oxide–semiconductor (MOS) structure of about 100 nm2 at room temperature. The flat band voltage (VFB) shift was about 0.37 V, which is agreed well with the calculated VFB shift for one electron per nanocrystal.

For n-type metal–oxide–semiconductor (NMOS) devices, a metal gate with a very low effective work function (Φm,eff) is necessary. In this paper, we evaluate the Φm,eff values of ScNx gates on both SiO2 and atomic-layer-deposited (ALD) HfO2. The ScNx/SiO2 samples have a wide range of Φm,eff values from ~3.9 to ~4.7 eV. However, the ScNx gates on HfO2 show a relatively narrow range of Φm,eff values from ~4.5 to ~4.8 eV due to the Fermi level pinning (FLP) effect. The generation of oxygen vacancies may result in the extrinsic FLP near the ScNx/HfO2 interface. Therefore, ScNx is an NMOS-compatible electrode on SiO2 and the extrinsic FLP should be suppressed for NMOS devices with HfO2.

We report the effects of high-pressure deuterium postmetallization annealing on the reliability characteristics of silicon–oxide–nitride–oxide–silicon nonvolatile memory devices. Compared with the control samples annealed in a conventional forming gas ambient (H2∕N2=4%∕96%), the samples annealed in a high-pressure (10 atm) pure deuterium ambient show improved endurance and retention characteristics without the degradation of program/erase (P/E) speed. In addition, the high-pressure deuterium-annealed samples show a significantly reduced charge loss rate for the electron-stored state and the hole-stored state, before and after the P/E cycles. The improved reliability of the high-pressure deuterium-annealed samples can be explained by the significantly decreased interface trap density and the large kinetic isotope effect of deuterium, which reduces the generation of the interface trap density under the stress of the P/E cycles.

We investigated the electrical characteristics of metal oxynitrides such as TaOxNy and TiOxNy, which were simply prepared by low-temperature wet oxidation of TaN and TiN layers, respectively, for metal-oxide-semiconductor (MOS) gate dielectric applications. Compared with metal oxides, TaOxNy and TiOxNy showed excellent electrical characteristics such as low leakage current density, low capacitance equivalent oxide thickness and superior thermal stability. By X-ray photoelectron spectroscopy (XPS), we were able to confirm nitrogen incorporation in the oxide bulk and at the interface. The improvements of metal oxynitrides can be explained by both the naturally formed SiON underlayer and nitrogen incorporation, which can reduce the growth of the interfacial oxide layer and trap density.

Program disturbance characteristics of 3D vertical NAND Flash cell array architecture have been investigated intensively. A new 'program Y disturbance' mode peculiar to 3D NAND Flash cell is defined. Swing characteristics of poly-Si channel and increased NOP (number of program) stress have been compared with 2D planar NAND Flash cell. In this paper, new program method pertinent to 3D NAND Flash memory was proposed to obtain program disturbance characteristics for MLC.

The electrical characteristics of ZrO2 were investigated relative to its use in SiGe metal-oxide-semiconductor (MOS) gate dielectric applications. Compared to ZrO2 directly deposited on SiGe, ZrO2, when deposited on a silicon capping layer shows a significant improvement in electrical characteristics such as low leakage current, negligible hysteresis, less fixed charge density and a lower interface state density (Dit) after low-temperature wet vapor annealing. The improvement in the electrical characteristics of ZrO2, with a silicon capping layer can be attributed to the negligible Ge segregation and surface roughness at the interface. Based on an Auger electron spectroscopy (AES) depth profile of Ge, we were able to confirm that Ge is segregated at the interface.

In this paper, the conventional voltage drop compensation methods are reviewed and the novel design and driving scheme, the advanced power de-coupled (aPDC) driving method, is proposed to effectively compensate the voltage IR drop of active matrix light emitting diode (AMOLED) displays. The advanced PDC driving scheme can be applied to general AMOLED pixel circuits that have been developed with only minor modification or without requiring modification in pixel circuit. A 14-in. AMOLED panel with the aPDC driving scheme was fabricated. Long range uniformity (LRU) of the 14-in. AMOLED panel was improved from 43% without the aPDC driving scheme, to over 87% at the same brightness by using the scheme and the layout complexity of the panel with new design scheme is less than that of the panel with the conventional design scheme.

With an excimer laser annealing (ELA) process, maximum display size is limited by the laser beam length because performance variations of the transistors in the overlapped regions cannot be sufficiently compensated to remove the brightness non-uniformity. In this paper, a redundant pixel line design is proposed to remove overlap mura. A 4.82″ AMOLED was successfully fabricated in order to verify the panel design method.

TaN nanocrystals (NCs) embedded in silicon nitride were investigated as a new charge-trapping layer of a silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. After annealing at 900°C, TaN NCs with average size of 3.5nm were formed by the phase separation method. Compared with a control sample without NC, memory devices with TaN NCs exhibit superior memory characteristics, such as a larger window of capacitance-voltage hysteresis and a lower charge loss rate. The improvement can be explained by the formation of high density TaN NCs with a deeper trap energy level.

The existence of series resistance in metal–oxide–semiconductor (MOS) devices can result in both the degradation of capacitance at a high frequency and the decrease in conductance. Using a conventional conductance method that does not consider the series resistance, the interface trap density can be underestimated. We propose an improved conductance method based on an equivalent circuit model including the series resistance. Compared with the conventional method, this new method enables the accurate determination of interface trap density.

The electrical characteristics of metal–oxide–semiconductor (MOS) device with Sc gate on atomic-layer-deposited (ALD) HfO2 were evaluated, for the first time. The equivalent oxide thickness (EOT) was reduced after post-metallization annealing even at 200°C. The reduction of EOT may be attributed to the diffusion of oxygen from the interfacial layer between HfO2 and Si substrate to the Sc gate. In case of optimum annealing condition, Sc gate can reduce EOT without degradation of leakage current and interfacial quality. The estimated effective work function of Sc was ∼3.8 eV and Sc might be a candidate for the gate electrode of n-type MOS devices.

Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program∕erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level.

TiN nanocrystals formed by a co-sputtering method have been investigated as discrete charge traps for metal–oxide–nitride–oxide–silicon-type nonvolatile memory devices. The formation of isolated TiN nanocrystals embedded in Al2O3 was confirmed by transmission electron microscopy, x-ray photoelectron spectroscopy, and x-ray diffraction analyses. In addition, superior thermal stability of TiN nanocystals embedded in Al2O3 was confirmed. Compared to the control samples without TiN nanocrystals, Al2O3 layers with TiN nanocrystals exhibited wider capacitance–voltage hysteresis and this in turn showed better charge trapping characteristics due to the incorporation of TiN nanocrystals into Al2O3.

The capacitance-voltage (C-V) characteristics with and without light illumination were evaluated for a capacitor with a Pt gate on the atomic-layer-deposited HfO2 dielectric. The flat-band voltage (V fb) is conventionally determined by a C-V curve. However, the extracted values of V fb were dependent on the C-V sweep direction and the starting voltage of the sweep (V start). The increasing differences between V start and intrinsic V fb (V fb,i) results in the increasing deviations of V fb from V fb,i. Therefore, the value of V start should be close to V fb,i and different values of V start must be applied to the devices with significantly different V fb,i.

RGB adjustable gamma compensation circuit to choose one of the three different gamma characteristics for each color has been integrated by LTPS TFT for AMOLED. A timing controller to generate all timing signals for a 6-bit data driver and a scanning driver has also been integrated by the TFT on the AMOLED panel.

We have investigated a charge-trapping nonvolatile memory (NVM) device with high-k dielectrics as a charge-trapping layer (HfO2 and Dy-doped HfO2) and a blocking layer (Al2O3). Compared with a conventional SiO2/Si3N4/SiO2 stack, both SiO2/HfO2/Al2O3 and SiO2/Dy-doped HfO2/Al2O3 stacks show significantly improved program and erase (P/E) speed. The improvement in P/E speed characteristics can be explained by the larger band offset of HfO2 and the increased thickness of the blocking oxide, which are the main advantages of high-k materials. Moreover, for a SiO2/Dy-doped HfO2/Al2O3 stack with an optimum Dy concentration, the enhanced retention characteristics were observed at a measurement temperature below 150°C due to the deep energy level of the charge trap.

We have investigated a sputter-deposited Al2O3/HfO2 stack as a blocking layer of metal–oxide–nitride–oxide–silicon capacitors. Compared with a SiO2 blocking layer, the sample with Al2O3/HfO2 stack shows lower write/erase (W/E) voltage, higher speed, and longer data retention time. The improvement of electrical characteristics can be explained by lower leakage current density and less voltage drop of high-k blocking layer which in turn increase the effective thickness of tunneling oxide. After stressing the W/E voltage of ±10 V voltage for 1 ms, the flat-band voltage shift of 4 V and 10 years of retention time was obtained.