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The steam oxidation of SiGe shows a transition from Si-like to Ge-like oxidation behavior depending on Ge concentration and oxidation temperature. Ge-like oxidation is described by the generation of oxygen vacancies (VO) at the interface between the oxide and SiGe virtual substrate. [1] Due to the different oxidation behavior, the presence of a Ge-oxide-free interfacial layer (IL) can suppress SiGe oxidation. [2] Here we show how a passivating interfacial layer can be grown using low-pressure oxidation and highlight the importance of SiGe surface preparation prior to low-pressure oxidation.

This paper addresses challenges and solutions of replacement metal gate of gate-all-around nanosheet devices. The unit process and integration solutions for the metal gate patterning as well as interface dipole patterning to offer multiple threshold voltage have been developed. The challenges of long channel device integration are also discussed.

We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance–voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO2 interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.

In this work we measure the inversion charge density for short UTBB-FDSOI MOSFETs (down to 45 nm) using an accurate method for the extraction of the parasitic components which take into account the effect of the back bias. Based on these results, we propose a modification of the inversion charge density model that uses the simplified Lambert function in order to include the back bias effect. This model is then validated with the experimental data for different gate lengths (from 185 nm to 45 nm). It is shown that this inversion charge model is valid for the mobility extraction and gives very good assessment of the mobility if we know only the IV-characteristic, the threshold voltage (under back bias effect) and the inversion charge capacitance. Finally, this method is used to extract the mobility for short channel devices (down to 40 nm) and it is found that the short channel mobility suffers from degradation even for large back biases. For the shortest device, it is demonstrated that the main source of mobility degradation is caused by oxide charges and interface states located near the S/D extensions and then it is deduced that the mobility reduction for large back biases is related to neutral defects from Si-crystal close to the channel edge.

This paper discusses in detail the effects of Sub-10nm fin-width ( $\text{W}_{fin}$ ) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the trans-conductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm $\text{W}_{fin}$ regime, cannot be improved just by $\text{W}_{fin}$ scaling but by optimizing source/drain resistance, gate dielectric thickness together with the $\text{W}_{fin}$ scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.

The (doped-)hafnia-based’ ferroelectric FET (FeFET) is a promising candidate for low-power nonvolatile memories and shows potential use as a steep-slope low-power logic device. This requires accurate modeling of the metal-ferroelectric-insulator-silicon (MFIS) gate stack electrostatics. Here, we present a hardware-validated FeFET compact model that resolves three key aspects in the MFIS electrostatics pertaining to a multidomain ferroelectric (FE) layer: 1) the nonradiative multiphonon process-based charge trapping; 2) the source-to-drain channel percolation due to spatial nonuniformity of FE domain switching; and 3) the nucleation-growth domain reversal dynamics using a phenomenological formalism. The polarization charge is calculated by discretized domain switching in transient under distributed coercive fields. Based on the comparison of the model versus experimental data on Hf0.5Zr0.5O2 n-FeFET hardware, we prove that the onset of FE ${V}_{{\mathrm {TH}}}$ lowering starts with the source-to-drain percolation path formation when enough FE domains have been flipped up by the gate bias. We further demonstrate that the field-independent domain growth is the fundamental origin of the measured steep subthreshold slope during the downward ${I}_{\mathrm{D}}$ – ${V}_{\mathrm{G}}$ sweep. The model ultimately aims to lay down the groundwork for a unified FeFET compact model for both memory- and logic-oriented applications.

Unraveling the gate bias dependence of threshold voltage (V TH ) shift in hafnia-based FeFETs is a central element to device design and reliable operation. Here we present a domain-percolation-based ferroelectric (FE) V TH shift model, in which we attribute the FE-induced V TH lowering to the source-to-drain "clustering" of successively flipped-up FE domains, as the global polarization increases with the gate bias. We highlight our accurate, semi-quantitative modeling reproduction of the experimental V TH shift in our Hf 0.5 Zr 0.5 O 2 n-FeFET hardware in the presence of traps, where a turnaround of V TH shift versus gate bias is observed. We argue that the turnaround occurs because the FE V TH lowering only starts to prevail when the gate bias has flipped up enough FE domains to "cluster" from source to drain, before which V TH keeps increasing with the gate bias due to charge trapping. The trapping behavior is simulated by a two-state non-radiative multi-phonon model. We further predict that the downscaling of gate length (L g ) can facilitate the onset of percolation in FE layer, which intrinsically helps to reduce the FE programming voltage (V PGM , by ~0.8V when ideal, trap-free) in FeFETs.

Driven by concerns on climate change, resources depletion, local and global pollution, sustainability is becoming an integral component of business and of regulations. The progress of Design Technology Co- Optimization (DTCO) methodologies and tools, building transversal knowledge from manufacturing to design, provides an opportunity to develop a framework for early sustainability assessments of logic technologies. Environmental scores can be derived together with the established Power, Performance, Area, Cost (PPAC) metrics. To demonstrate this approach, we evaluate the energy and water consumption as well as the greenhouse gas emissions trends from processing logic nodes from iN28 to iN3 with different scaling scenarios.

The low-frequency noise of input-output (I/O) FinFETs with 3.5 nm and 5nm SiO 2 gate dielectric is studied for different processing conditions. For the thin dielectric a high-pressure (HP) deuterium anneal can improve the noise Power Spectral Density (PSD). There is no significant impact on n-channel devices, while a pronounced effect is observed for p-channel devices, especially for a HP anneal at 400 °C and 20 atm. Results are also presented on the use of a Si/SiGe superlattice architecture and it is shown that the same gate stack quality as for standard devices can be maintained.

This paper shows the importance of oxygen control at the SiGe fin surface and within the gate stack. Optimized SiN liners are required to protect SiGe fins from oxidation during a flowable CVD (FCVD) densification anneal. Suppression of oxygen diffusion or scavenging from GeO via metal electrode is essential to achieve a low-D IT SiGe gate stack. By replacing HfO 2 with other dielectrics offering lower oxygen diffusivity, impact of metal electrode deposition process as well as the HfO 2 nitridation is corroborated to be related to the oxygen diffusivity. Finally, when using an embedded B-doped Si 0.4 Ge 0.6 S/D, higher channel strain in Si 0. 7 Ge 0.3 than in Si p-fins is obtained as predicted by TCAD.

To compensate for expected gate pitch scaling slowdown below 42nm, several scaling boosters are needed to reduce the logic standard cell height (CH). However, limited scaling benefits can be achieved using FinFET and Gate all around (GAA) nanosheets (NSHs) due integration limits in achieving tight PMOS to NMOS (PN) separation. Therefore, a novel forksheet (FSH) device architecture is proposed achieving extremely scaled PN space using limited additional processing complexity. The FSH achieves 10% frequency increase at iso-power and 24% power reduction at iso-frequency compared to GAA nanosheet with a combined area scaling of 20%. SRAM bit cell area scaling of 30% and read delay performance increase is shown.

We present a kinetics-based analysis of the steep slope operation of ferroelectric (FE) FETs built on (i) a statistical multidomain nucleation-propagation mechanism of FE polarization switching and (ii) charge trapping in the high- K FE oxide. With a hardware-validated compact model we predict the change in hysteresis direction, the steep slope and the transient behaviors observed in our I-V measurements on Hf 0 5 Zr 0 5 O 2 -based planar n-FEFETs. We find that the proposed field-independent propagation is essential in explaining the measured reverse-sweep steep slope and transient current drift. Furthermore, the model suggests that a higher polarization and accordingly a larger I-V hysteresis are induced upon increased trapping. Finally, we show that for hafnia-based FE oxides, reliability engineering of defect band is needed for obtaining steep slope in scaled logic-FEFETs.

A self-limiting wet etching of metal thin films has been developed for the replacement metal gate patterning in advanced logic devices, which will have aggressively scaled gate length and fin pitches. A uniform and highly selective wet etching of polycrystalline TiN films is demonstrated by a diffusion-limiting oxide growth on the metal surfaces as well as a subsequent highly selective oxide removal.

High mobility channel materials like SiGe, Ge and IIIV receive lots of interest in order to enable the continuation of Moore’s path during the upcoming technology nodes. Recently Si-cap-free SiGe passivation with the number of interface states (NIT) down to 2 1011 cm-2 have been demonstrated. [1-3] A clear correlation was established between Ge-content in the SiGe-oxide and NIT. Unfortunately no process information has been provided on how the Ge-oxide-free interlayers were obtained. In a separate study the impact of HF, HCl and SC1 cleaning solution on the SiGe surface and oxide composition was reported. [4] A comparison of SiGe Gate-All-Around (GAA) and FinFET devices using a Si-cap-free SiGe 25% passivation scheme in a replacement metal gate (RMG) integration indicate the device performance is improved by a TMAH (aq) treatment prior to SiGe interlayer formation and high-k deposition. [5] Here the formation of a SiGe wet chemical oxide will be presented. The impact of dummy gate processing on the interlayer composition is reported. Also the impact of a TMAH (aq) treatment prior to chemical oxide formation has been analyzed and will be reported. Blanket strained SiGe 25% and 45% were grown by epitaxy. The SiGe-substrate and -oxide composition were measured by angle-resolved XPS using the Si2p and Ge3d peaks. The Ge3d peak is fitted with three different compounds: elemental Ge, GeO2 and Ge-suboxide. The angle dependence lets us estimate the distribution of the different components with respect to the sample top surface. An concentration increase with increasing angle (relative to the surface normal) indicates the compound is located closer to the sample surface. And reversely a concentration increase with increasing angle indicates the compound is located deeper into the sample. A native oxide was grown on SiGe 25 and 45% by exposing the wafers to the cleanroom air for approx. 1 week. The native oxide was found to be stoichiometric or nearly stoichiometric with a uniform Ge content throughout the oxide for SiGe 25 and 45% respectively. A wet chemical oxide was grown using an ‘imec clean’ [6] having a final O3/HCl (aq) rinse. The wet chemical oxide is Ge-poor compared to the SiGe substrate. No or only a small variation in Ge content of the SiGe-oxide is seen with ARXPS. However the fraction Ge-suboxide decreases with increasing angle, indicating the Ge-suboxide are located deeper within the sample, so closer to the SiGe-oxide/SiGe-substrate interface. The Ge-content of the SiGe-substrate after wet chemical oxidation shows a weak incident-angle-dependence, indicative a limited Ge enrichment of the SiGe substrate towards the SiGe-oxide/-substrate interface. The low Ge content of the SiGe-oxide is attributed to the water solubility of GeO2. The increase in Ge-content towards the SiGe-oxide/-substrate can be (at least partially) attributed to the poor water solubility of Ge-suboxide. The small increase in Ge content of the SiGe substrate can be attributed to the thermodynamically preferred oxidation of Si over Ge. The combined impact of dummy gate deposition, spike anneal and dummy gate removal prior to SiGe interlayer formation was investigated by AR-XPS and SIMS. The temperature used during spike anneal was found to have a significant impact on the Ge-content of the SiGe-oxide formed during an O3-last imec clean. The results will be reported in detail at the conference. The impact of TMAH (aq) on the chemical oxide composition and surface roughness will also be reported. TMAH (aq) was found to improve SiGe device performance. [5] Also the interaction with the subsequent HfO2 deposition will be reported. In summary SiGe is found to behave as a non-linear combination of Si and Ge. In HF-free aqueous solutions, the SiGe oxide composition is a combination of (1) thermodynamically preferred oxidation of Si versus Ge; (2) poor water-solubility of SiO2 and/or its low solubilization rate; and (3) fast dissolution of GeO2 but slow dissolution of Ge-suboxides. [1] CH Lee et al. VLSI 2016. [2] S. Siddiqui et al. presented MRS Spring Meeting 2016. [3] CH Lee et al. IEDM 2016. [4] S.L. Heslop et al. ECS Trans 69 (2015) 287. [5] H. Mertens et al VLSI 2015. [6] M. Meuris et al. Solid State Phenom, July 1995, p. 109. Figure 1

Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaining low off-state leakage [1]. Besides, horizontally oriented nanowires are an evolutionary extension of FinFETs, as opposed to vertical nanowires which require more disruptive technology and design changes [2]. Finally, stacking of nanowires is relevant for enhancing the drive current per footprint. Based on these considerations, GAA transistors made of vertically stacked horizontal nanowires have been included in the ITRS roadmap to reduce the contacted gate pitch, which is a key figure of merit for CMOS device density, to below ~40 nm in 2019-2021 [3]. In the context of the industrial relevance described above, we present the fabrication of Si GAA devices on bulk Si substrates. Multiple processing aspects that are relevant for bulk CMOS technology definition are addressed, including stacking of 8-nm-diameter Si wires at 45-nm lateral pitch and 20-nm vertical pitch [4], and nanowire-compatible replacement metal gate processing in combination with threshold voltage tuning by dual work function metal integration [5]. Temperature restrictions for the formation of shallow trench isolation, and the interaction between N- and P-type junction formation on one hand and nanowire release processes on the other hand are discussed as well. [1] K. J. Kuhn, IEEE Trans. Electron Devices, vol. 59 (7), p.1813, (2012). [2] L. Liebmann et al., VLSI Tech. Dig., p.112 (2016). [3] The International Roadmap for Semiconductors (ITRS) 2.0, http://www.itrs2.net/ (2015). [4] H. Mertens et al., VLSI Tech. Dig., p.158 (2016). [5] H. Mertens et al., IEDM Tech. Dig., p.524 (2016). Figure 1

Response of a metal\ferroelectric Hf 0.5 Zr 0.5 O 2 \metal capacitor to an arbitrary excitation is investigated by polarization reversal curves and switching speed characterization. Results are explained in a steady-state Preisach as well as a modified transient NLS model framework. Applicability and limitations of each model are discussed. Switching speed measurements are found to be sensitive to parasitics. Separation of the intrinsic behavior from parasitics indicates the upper bound of the characteristic time constant of polarization switching speed is around 80ns in our sample.

IEEE We investigate BTI charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals. Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work function. However, experimental data on capacitors show enhanced or reduced charge trapping at constant oxide electric field for different work function metal stacks. We ascribe this to a different chemical interaction of the metals with the dielectric, which yields different defect profiles depending on the process thermal budget, and not to the gate work function per se. This observation is confirmed by comparing BTI degradation in nMOS and pMOS Replacement Gate planar transistors with three selected work function metal stacks (representative of high-, standard, and low-Vth device flavors), and two different process thermal budgets. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy”, we also show that, on top of the unavoidable chemical interaction of different metals with the underlying SiO2/HfO2 dielectric stack, different gate work functions within a typical range of relevance (4.35-4.75eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs. ispartof: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY vol:19 issue:2 pages:268-274 ispartof: location:CA, Tahoe status: published

This work experimentally investigates the effect of fm-width $(W_{fin})$ scaling in sub-10nm regime on the analog performance of nFinFETs. It is shown that the device trans-conductance $(g_{m})$ degrades and output conductance $(g_{ds})$ improves with reduction in $W_{fin}.$ Various sources affecting the variability of $g_{m}$ and gds in sub-10nm $W_{fin}$ regime are also explored. Through different analog performance metrics, it is shown that the analog performance of thinner fin FinFETs can be further increased by properly optimizing the S/D resistance and gate dielectric.

Low thermal budget gate stacks will be required for novel integration schemes, such as 3D sequential stacking of CMOS tiers. We study the impact of a reduced thermal budget on BTI reliability, and we demonstrate two strategies to tolerate the inherently large high-k defect densities: i) replacing inversion mode devices with highly doped junction-less transistors, or ii) engineering dipoles at the interface between SiO 2 and HfO 2 to suppress the carrier-defect interaction. The latter approach is demonstrated for nMOS PBTI and, for the first time here, also for pMOS NBTI, as even this aging mechanism is controlled by high-k defects in ultra-thin EOT low thermal budget gate stacks.

Nanowires (NW) and nanosheets (NS) are promising channel structure for future technology nodes as they can offer better electrostatics than FinFETs. In this paper, we show another advantage of strained Ge NW pFET over strained Ge FinFET, which lies in the preservation of Strain-Relaxed-Buffer (SRB)-induced strain through fin cut and S/D recess. This benefit comes from the presence of the sacrificial SiGe layers. Lowering the Ge concentration in the SiGe sacrificial layer is a way to further suppress the strain loss. Furthermore, a comparison of Ge NW pFETs integrated on Ge SRB and SiGe SRB reveals that SiGe SRB provides a huge advantage not only in the strain engineering but also in I OFF control. These are key enablers in maximizing the performance while minimizing the I OFF of strained Ge NW pFETs.

3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(\mathrm{T}\leq 525^{\circ}\mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature.

We investigate BTI charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals. Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the metal work function. However, experimental data show enhanced or reduced charge trapping at constant oxide electric field for different work function metal stacks. We ascribe this to a different chemical interaction of the metal stack with the dielectric, yielding different defect profiles depending on the process thermal budget. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy”, we also show that different metal work functions within a typical range of relevance (4.35-4.75eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs.

N-channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope. The hysteresis vs. subthreshold slope tradeoff, performance dependence on the bias voltage and the competition between trapping and FE behavior are reported and discussed. A transient Id-Vg measurement technique assisting in differentiating between trapping and FE behavior is introduced.

A flow, module steps and key structural elements enabling a surrounding gate transistor (SGT) based 6T-SRAM with 50nm pillar pitch and 0.0205 um2 are presented, with emphasis on process challenges and innovations. A new DTCO/TCAD methodology is used to explore the design space, demonstrate the bit cell functionality and optimize the process. In particular, it is shown that vertical SGT are extremely sensitive to gate misalignment and that buried bottom contact makes the process immune to doping variations and misalignments.

This work presents Si/SiGe superlattice finFETs (FF) for 1.8V/2.5V I/O applications in vertically-stacked Gate-All-Around horizontal nanowire technology (hNW) technology. Superlattice FF have a higher ION than I/O hNW reference devices and can be more easily integrated into a GAA hNW technology than Si I/O FF. These novel I/O FET structures exhibit competitive analog performance and are superior as ESD protection devices.

In the manufacturing of multi-Vt FinFET transistors, the gate material deposited in the nano-spaces left by the removed dummy gate must be etched back in mask-defined wafer areas. Etch conformality is a necessary condition for the control of under-etch at the boundary between areas defined by masking. We studied the feasibility of TiN etching by APM (ammonia peroxide mixture, also known as SC1) in nano-confined volumes representative of FinFET transistors of the 7 nm node and below, namely nanotrenches with 1-D confinement and nanoholes with 2-D confinement. TiN etching was characterized for rate and conformality using different electron microscopy techniques. Etching in closed nanotrenches was conformal, starting and progressing all along the 2-D seam, with a rate that was 38% higher compared to a planar film. Etching in closed nanoholes proved also to be conformal and faster than planar films, but with a delay to open the 1-D seam that seemed to depend strongly on small variations in the hole diameter. However, holes between the fins at the bottom of the removed dummy gate, are not circular and do present 2-D seams that should lend themselves for an easier start of conformal etching as compared to the circular nanoholes used in this study. Finally, to explain the higher etch rate observed in nano-confined features, concentrations of ions in nanoholes were calculated taking the overlap of electrostatic double layers (EDL) into account. With negatively charged TiN walls, as measured by streaming potential on planar films, ammonium was the dominant ion in nanoholes. As no chemical reaction proposed in the literature for TiN etching matched with this finding, we proposed that the formation of ammine complexes, dissolving the formed Ti oxide, was the rate-determining step.

This paper discusses SRAM scaling beyond the 5nm technology node and highlights the fundamental scaling limits due to FinFET and Gate all-around (GAA) technology. To compensate for expected gate pitch scaling slowdown below 42nm, several scaling boosters are needed to reduce the cell height. However, limited scaling benefits can be achieved in FinFET and GAA technology. Therefore, a novel vertically stacked lateral nanosheet architecture using a forked gate structure is proposed showing superior performance and area scaling compared to FinFET and GAA devices. Moreover, limited additional processing complexity can be achieved. The Fork architecture allows 20% SRAM area scaling at isoperformance and 30% performance increase at iso-area compared to FinFET beyond 5nm technology node.

This paper shows high-pressure anneal (HPA) as a performance booster for Si-passivated strained Ge (sGe) p-channel FinFET and gate-all-around (GAA) devices. Improved interface quality and hole mobility (∼600 cm2/Vs) are obtained on FinFET after HPA at 450°C. While V th is tuned by ∼400 mV using TiAl work function metal (WFM), HPA-induced increases in J g and NBTI are suppressed by barrier layer engineering under the TiAl. Finally, the optimized HPA is also shown to improve the electrostatics and overall performance of GAA devices, reaching SS lin of 65 mV/dec at L g =60 nm and a Q factor of 15 with low I off of ∼3×10−9 A/μm.

Instabilities in MOS-based devices with various substrates ranging from Si, SiGe, IIIV to 2D channel materials, can be explained by defect levels in the dielectrics and non-radiative multi-phonon (NMP) barriers. However, recent results obtained on single defects have demonstrated that they can show a highly complex behaviour since they can transform between various states. As a consequence, detailed physical models are complicated and computationally expensive. As will be shown here, as long as only lifetime predictions for an ensemble of defects is needed, considerable simplifications are possible. We present and validate an oxide defect model that captures the essence of full physical models while reducing the complexity substantially. We apply this model to investigate the improvement in positive bias temperature instabilities due to a reliability anneal. Furthermore, we corroborate the simulated defect bands with prior defect-centric studies and perform lifetime projections.

3D Sequential integration has been envisioned to stack transistors in the same front-end process. A crucial challenge is the management of the thermal budget. This work focuses on Si nMOS gate stack challenges, specifically: for a top tier device, by inserting a thin LaSiO x interlayer between SiO 2 and HfO 2 a sufficient PBTI reliability is demonstrated without resorting to unsuitable high temperature anneals. This gate stack also offers good thermal stability for a pMOS over nMOS scenario.

1.8V I/O transistors were fabricated in a 14-nm bulk finFET technology, using 2–3nm Atomic Layer Deposition (ALD) SiO 2 in a high-k/metal gate stack. PBTI characterization showed negligible degradation at the operating V dd , with nFET VOV max exceeding 2.2V. The pFET counterparts however, showed poor reliability, ascribed to a high defect density in the ALD SiO2 as compared to standard chemical or thermal oxide. To boost the NBTI reliability, we propose the use of a Ge channel for the I/O pfinFET to reduce the interaction of channel holes with the ALD SiO 2 defects. This allows to demonstrate pFET BTI reliability on-par with the Si-channel nFET counterpart.

Channel hot-carrier (CHC) reliability in p-FinFET devices is studied related to the postdeposition anneal (PDA) process. Clearly reduced CHC degradation is observed with N2-PDA at the VG = VD stress condition. The interface defect density degradation calculated from the subthreshold slope is similar in the reference and PDA devices. However, the pre-existing high- k bulk defect is lower in the PDA-treated device as observed by the low-frequency-noise measurement. This leads to less hot/cold-carrier injection into the bulk defects at the high field under the VG = VD condition, where a higher charge trapping component is expected than under the classical VG ~ VD/2 condition. The responsible bulk defect is pre-existing, not generated during the CHC stress as proven by the stress-induced leakage current analysis.

We demonstrate a Si-passivated Ge nMOS gate stack with Dit of ∼5×1010 cm−2eV−1 around midgap and unnoticeable C-V hysteresis at an operating condition (oxide trap density of ∼1×108 cm−2 at V ov /CET=3.5 MV/cm). Insertion of a 3D-compatible thin ALD LaOx, MgOx and LaSiO layer at the interface between HfO2 and SiO2/Si/Ge improves PBTI reliability thanks to the interface dipole-induced band engineering. The high DIT of Si-passivated Ge nFET is dramatically reduced by ∼40x around midgap using a combination of the LaSiO insertion and a H2 high-pressure anneal (HPA). These key gate stack technologies realize further improvements in mobility (∼50% at peak) and PBTI reliability (V ov =0.32 V for 10 years) of Si-passivated Ge nFETs.

We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.

The crystalline orientation effect is investigated for post-treatments of a replacement metal gate (RMG) p-type bulk fin field effect transistor (FinFET). After post-deposition annealing (PDA) and SF6 plasma treatment, the hole mobility is improved. From low-frequency noise analysis, reduction of the trap density and noise level is observed in PDA- and SF6-plasma-treated devices. (100) sidewall-oriented FinFETs show a lower noise level because of fewer interface traps compared to (110) sidewall-oriented devices. SF6 plasma affects the interface traps, whereas PDA relatively more affects bulk oxide traps for RMG high-k last FinFET.

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

We report extensive experimental results on the Negative Bias Temperature Instability (NBTI) of SiGe channel pMOSFETs as a function of the main gate stack parameters. These results clearly show that this high-mobility channel technology offers a significantly improved NBTI robustness compared to Si-channel devices, which can virtually eliminate this critical reliability issue for sub-1 nm EOT devices. The intrinsically superior NBTI robustness is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. Thanks to this effect, both a significantly reduced time-dependent variability in nanoscaled SiGe devices and a reduced low-frequency noise are also observed. Other reliability mechanisms, such as Channel Hot Carriers and Time-Dependent Dielectric Breakdown are shown not to be showstoppers. All these aspects underscore the SiGe channel technology as a very promising alternative to Si pMOSFETs for future CMOS technology nodes.

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), focusing on the scalability challenges faced by: 1) effective work function (EWF) engineering targeting logic high-performance and low-power applications; 2) low-resistance fill-gate metallization for extremely scaled gates with high aspect-ratios; and 3) ultra-thin EOT gate dielectrics with controlled JG, reliability and variability. Also addressed is the need for, and exploration of options compatible with 3D-architecture devices (FinFETs). Key results include controlled TiN/TiAl-alloying and conformal ALD-TiN/TaSiAl for low-threshold voltage (VT) scaled NMOS, W vs. Co-Al alloy evaluation as fill-metal, and cubic-phase HfO2 with higher k-value (k=30) showing improved performance and reliability when normalized to JG. Reduction of the bulk high-k dielectric defects, by implementation of an optimized post high-k deposition anneal (PDA), is shown to play a key and dominant role to enable substantial NBTI lifetime improvement in the (sub-)1nm EOT regime.

We have shown that the poor PBTI reliability of IIIV/high-k gate stacks is universally related to process thermal budget limitations. Low temperature anneal optimization and high-k nitridation reduce oxide defect density. In contrast to a wide distribution of defect levels in Al 2 O 3 , HfO 2 on InGaAs shows a minimum defect density ∼0.2eV below the channel E C . By introducing an interface dipole, a significant reliability boost was demonstrated. While low thermal budget high-k quality and IIIV interface thermal stability constitute challenges, our results show that a reliable IIIV/high-k gate stack can be fabricated.

Sub-30nm L G Fin-replacement strained-Germanium pFinFETs at state-of-art device dimensions are reported with optimized S/D junctions and RMG stack. Competitive performance is shown for the first time when comparing the sGe devices with counterparts from the same 14–16nm R&D platform (Ge vs Si channel, FinFET vs lateral Gate All around). Improvement in channel passivation efficiency at scaled device features is seen to be an important knob to further boost the performance of scaled Ge channel FINFETs.

A novel multi work function process is used to demonstrate up to 250 mV effective work function shifts of nMOS devices. The process use SiH 4 -soak of ALD TiN to change its barrier properties with ALD TiAl. FinFET devices are demonstrated with ∼100 mV V T -shift for 24-nm-L G devices resulting in 20× reduction in off-state leakage at unaffected sub threshold slope and improved mismatch behavior. A patterning scheme using an nMOS first RMG process is proposed and demonstrated.