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The Cuk inverter operating in continuous conduction mode (CCM) is susceptible to grid disturbances and its transfer function has two right-half plane zeros, which cause a large phase lag. To improve the output-tracking precision in the grid-connected environment, a repetitive controller with linear phase-lead compensation has been developed for the Cuk inverter. However, this controller requires heavy computational burden and memory space; these problems become more severe as the converter operates at a higher switching frequency. This paper proposes to use a down-sampled repetitive controller (DRC) for Cuk CCM inverter to alleviate these problems. The down-sampling technique itself can significantly reduce the computational burden and memory space of RC. On the contrary, its control accuracy becomes very low, particularly for the Cuk CCM inverter. Unlike conventional module integrated inverters (MIIs), the Cuk CCM inverter must adopt a fractional-order phase-lead compensation algorithm to compensate for the effect of the large phase lag in the down-sampled environment. To clarify the inevitable usage of DRC with a fractional-order phase-lead compensation for Cuk CCM inverter, the DRC is classified into four types, this paper provides its detailed design guideline based on stability analysis of the overall control system and also presents design examples for representative MIIs. Experiments using a 300-W prototype Cuk inverter validate that the proposed control approach achieves acceptable output-tracking accuracy. The total computation time and memory space with the DRC decrease by 76.0% and 80.0% compared to those with the conventional RC while the output-tracking accuracy with the DRC decreases by 0.42%.

A robust optimized active disturbance rejection control (ADRC) based grid voltage sensorless current controller is developed for an LCL -filtered grid-connected inverter (GCI) via a predictive control approach under various sources of disturbance, including the model uncertainties, the LCL inherent resonance phenomenon, and nonideal grid environment. Aiming to improve the sinusoidal reference tracking performance as well as to reject lumped sinusoidal disturbances in the control practice, a resonant extended state observer is integrated into the ADRC structure, which guarantees a rigorous stable operation of inverter for bounded filter parameter uncertainties and adverse grid voltage conditions. The grid frequency adaptability is thoroughly considered in the controller design process and synchronization technique, offering an extra capability for GCI to operate under different grid voltage frequency levels or even the frequency deviation caused by grid fault events. Robustness against parameter uncertainty and system stability is analyzed through the discrete-time frequency analysis and pole-zero map approaches. The simulation and hardware experiments are conducted for GCI with LCL filter parameters designed for two typical regions (i.e., the resonance frequency is less and greater than one-sixth of switching frequency) to validate the theoretical analysis and the effectiveness of the proposed control method.

Series resonant converter-unfolding inverter (SRCUI), a pseudo-dc-link inverter based on series resonant converter, is a promising topology featuring high efficiency and high step-up operation capabilities, which are important for many applications interfacing with renewable energy systems. Out of the existing modulation methods for SRCUI, variable-frequency modulation (VFM) tends to be the most efficient due to complete zero voltage switching (ZVS), but it suffers from limited modulation range. This limitation leads to distortion in the output waveform near zero crossing points. To extend the effective range of VFM and reduce the distortion, a technique termed sequential waveform synthesis (SWS) is proposed in this article. SWS is specifically created for input-parallel-output-series multimodular inverter based on SCRUIs. It activates/deactivates each module sequentially, so the remaining active modules have higher individual output voltage and power that assist in ZVS. The total output voltage waveform synthesized by individual output voltages has lower distortion and retains soft-switching function. The principle of SWS is explained in this article by using total harmonic distortion as a performance indicator. In addition, the modeling and controller design of variable-frequency-modulated SRCUI are also addressed since they were hardly studied before. The controller and the concept of SWS are implemented on a multimodular inverter prototype formed by three SRCUIs and verified by the experimental results.

This article presents a novel space vector pulsewidth modulation (SVPWM) for a three-phase binary-cascaded multilevel inverter (BCMLI). The SVPWM could become impractical in multilevel inverters (MLIs) because of its increasing complexity with a larger number of levels. The gh coordinate system can ease the digital implementation, but to generate the inverter's abc states from the nearest three vectors (NTVs), iterative computations are required every sampling instant. This article proposes a further reduction of computations by directly generating the abc state with minimum common-mode voltage (CMV) from a gh vector. Subsequently, only one vector among the NTVs is required for implementing the proposed SVPWM. The reduced CMV profile within the NTVs further permits the reduction of commutations by clamping one phase during a sampling period. The presented technique exhibits full dc bus utilization capability and can be implemented in the BCMLI and further applied to any M-level MLI. Also, if M is considerably large or if switching losses and electromagnetic interference emissions must be minimized, nearest vector modulation with reduced CMV along with the line-frequency operation of high-voltage cells can be implemented to reduce the switching losses. Experimental results of a BCMLI are presented to verify the effectiveness of the proposed technique. Published version

Accurate estimation of the switching loss for power MOSFETs is critical to predict the device junction temperature and the efficiency in power converters. In recent power electronics design, wide bandgap (WBG) devices are adopted with zero-voltage switching (ZVS) to achieve higher efficiency. For devices with ZVS, the only switching loss will be channel turn-off loss, and on the contrary to hard switching, the energy stored in $C_{\text {oss}}$ will be recycled. The models for the estimation of total turn-off energy have been discussed in the literature, whereas the model of channel turn-off energy is absent. In this article, a behavioral model of channel turn-off energy using a simple $\alpha $ – $\beta $ equation for curve fitting is proposed, which can be applied to an entire current and voltage range. The proposed model is verified by different GaN HEMTs and SiC MOSFETs with a double-pulse test circuit in simulation and experiment.

Discontinuous conduction mode (DCM) and critical conduction mode (CRM) have held dominant positions in low-power boost power factor correction (PFC) control. Typically, two-level DCM and CRM suffer from high peak current and variable frequency at several-hundred kilohertz, respectively. The two factors can cause secondary effects such as high electromagnetic interference, current stresses, input filter design difficulty, and switching losses. Only to take merits of DCM and CRM that are fixed frequency and lower peak current, this article utilizes three-level boost (TLB) and its three-level current-slope options. This article proposes a hybrid conduction mode (HCM) control, which adopts adaptive single-switch on -time to achieve fixed-frequency quadrangular CRM operation. At lower input voltage, low inductor current enters DCM so that TLB PFC experiences hybrid operation modes depending on varying ac input. Analyses and experiment results in this article confirm that the proposed HCM control can achieve huge reductions of switching losses and peak current stress, improving efficiency in wide-range input voltage and load at the cost of acceptable PF drop. Moreover, a simple voltage-balancing scheme is implemented to the proposed control and verified effective to resolve the inherent topology issue.

In this article, we present a bridgeless hybrid-mode Zeta inverter for distributed energy systems. We integrate the secondary diode of the conventional unfolding-type Zeta inverter into one of diagonal pairs of the secondary-side switches in a bridgeless Zeta inverter. This structure decreases the number of active power components and provides naturally well distributed loss at the body diodes of the secondary-side switches over one cycle of grid voltage, and as a result, increases both output power transfer and reliability. To attain medium-high power capacity with appropriate size of magnetic components, the bridgeless Zeta inverter operates in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM). However, control of the proposed inverter is difficult because of the distinct system dynamics caused by the operations in DCM and CCM. To deal with this control problem, we first identify the mode boundaries and, corresponding to each mode, develop a dynamic model to design a controller. Then, we propose to use a feedback controller plus a feedforward controller supplemented with a repetitive controller that uses a phase-lead compensator. Experimental results using a 300-W prototype demonstrate the feasibility and effectiveness of the proposed modeling and control approach.

This article proposes an average periodic delay-based repetitive controller for power factor correction (PFC) converters undergoing grid frequency variations. When the grid frequency is changed, a conventional repetitive controller requires an interpolation method or additional memory to achieve frequency adaptability. Furthermore, frequency adaptability can also be realized using a variable sampling frequency; however, this requires additional computation effort and a multirate digital control system. In this article, with a fixed sampling frequency and memory length, the proposed repetitive controller, which generates the average periodic delay unit, maintains its harmonic compensation performance under grid frequency variations. In the proposed method, the control variables are updated depending on the phase of the grid voltage to reflect the grid frequency deviations in the average period delay unit. Because no complicated software modification is necessary, the proposed scheme can be easily plugged in the existing control algorithm. The theoretical analysis and stability issues of the proposed scheme have been discussed in detail to ensure stable operation and disturbance rejection. Both the simulations and the experiments on a 1.5-kW PFC converter have been carried out to verify the effectiveness of the proposed repetitive control.

Discontinuous conduction mode controlled boosting power-factor-correction (PFC) converters suffer from high differential-mode electromagnetic interference (EMI) and require a large input filter due to high inductor current ripples at a single switching frequency. To remedy the shortcomings, a downward spread-spectrum frequency modulation (SSFM) is proposed in this letter. The SSFM can be used by boosting PFC converters for reduced EMI and improved efficiency. On top of the frequency modulation, a novel adaptive three-level current (ATC) scheme is devised with three-level boost PFC using multilevel capability to obtain further reductions of peak current and EMI amplitude. Analyses and experiments validate that the proposed SSFM and ATC scheme can bring improvements of EMI and efficiency at the cost of increased output-voltage ripple.

This article presents a single-sourced hybrid binary-cascaded multilevel inverter (BCMLI) with front-end high-frequency-link (HFL) converters. The purpose of HFL converters is to boost a dc-source voltage to three bus voltages in a binary ratio. In this article, one of the HFL converters is removed from the system and the voltage of the floating capacitor caused by the removal is controlled by a newly proposed floating-capacitor-voltage (FCV) control. Compared with the conventional BCMLI, the system size and cost can be significantly reduced while maintaining promising features, including 15-level output, high voltage gain, galvanic isolation, and reactive-power capability remain unchanged. The proposed FCV control utilizes one of the switching angles at the voltage-level transitions as the control variable in a single-loop design, which facilitates control simplicity in the proposed system. The hybrid BCMLI with the proposed FCV control shows relative advantages of voltage gain, isolation capability, reactive supply, and simple control system over the state-of-the-art hybrid inverter topologies with FCV control methods. The details of the hybrid BCMLI, modulation schemes, proposed FCV control design, and comparative assessment are included in this article. In order to validate the proposed system and FCV control, a set of experiments with a 1-kW BCMLI prototype has been conducted for wide-range load levels and power factors.

Solid-state transformer has been a major area of research in recent years because of its multifunctionality as compared to conventional low-frequency transformers. Bidirectional isolated dual-activ...

This brief presents a unified voltage balancing feedforward (UVBFF) for three-level boost (TLB) power-factor-correction (PFC) circuit in discontinuous and critical conduction modes. In general, the topology in both modes puts emphasis on low-cost system. Thus, electrolytic capacitors with wide-tolerance are commonly used at outputs and voltage unbalance is inevitable even under symmetric operations of two boost cells. In this brief, three-level switching capability of TLB PFC is introduced and asymmetric on-time feedforward for main switches is proposed. The proposed UVBFF can be realized by a single equation and harmonized with conventional feedback voltage-loop so that easy implementation is the key merit. The effectiveness of UVBFF is proven by analyses and experimental results.

In this paper, a 1-kW DC-DC buck converter with a four-phase interleaved matrix inductor is proposed for battery charging applications. It is well-known that the DC bias on the inductor will cause high core loss as it changes the B-H characteristic. Typically, the transient conduction mode employed in high voltage applications for zero-voltage-switching of devices would cause higher inductor current ripple. The conventional approach to reduce the effect of DC bias and inductor current ripple is employing multi-phases. However, the cost and size of the converter will increase significantly. This paper proposes the matrix inductor which has a small volume and reduces the effect of the DC bias by flux sharing and flux cancellation at the same time, results in low inductor core loss. With the interleaved operations the output current ripple can be lower which is suitable for battery charging application. Besides, the comparison of the synchronous and interleaved operation is presented. A 1-kW prototype is built and the experimental results show that the peak efficiency is 99.1% and 99.2% for synchronous and interleaved control, respectively. Additionally, the output current ripple of the interleaved operation is reduced by 85% in comparison with the synchronous operation. Office of Energy Efficiency and Renewable Energy (EERE), U.S. Department of EnergyUnited States Department of Energy (DOE) [DE-EE0008347] The information, data or work presented herein was funded in part by the Office of Energy Efficiency and Renewable Energy (EERE), U.S. Department of Energy, under Award Number DE-EE0008347. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

Traditionally, standalone closed-loop drain–source sensed synchronous rectification (SR) implementation has been limited by the voltage limits of commercial IC controllers. Commercially available SR controllers have low maximum voltage limits, necessitating a high-voltage blocking mechanism for use in higher voltage rectifiers. Therefore, in this article, a board-level blocking method to protect drain–source voltage sensed SR controllers from high voltage and currents at the board level is presented. This method allows for the high-voltage operation of drain–source SR controllers. This method is self-biasing and allows for SR controller operation far beyond the datasheet voltage limits (kV+). The mechanisms of operation are analyzed, and design criteria created for selecting an optimal clamp is proposed. The proposed solution is simple and low in cost and component count, making closed-loop, cyclically adaptive SR a practical solution for high-voltage rectifiers. The blocking circuit is presented, analyzed, and tested for use with commercially available drain–source SR controller integrated circuits (ICs). Hardware SR testing is completed on two LLC-DCX (dc-transformer) modules with 300 V, and over 1-kV output voltages to demonstrate the voltage blocking capabilities.

Drain-source voltage-sensed synchronous rectification (SR) is a technique that can be used to reduce the secondary-side diode conduction loss of an LLC converter. In drain-source SR, an early SR-switch turn off issue is observed due to parasitics present in the path of the SR drain-source sensing loop. In rectifiers with parallel switches which is common in higher current applications, a new sequential turn-off method named “sequential parallel switching” (SPS) is proposed to extend the SR conduction period. By increasing the drain-source voltage signal near the turn-off moment, the effect of the parasitic inductance on the SR signal can be minimized, extending the total SR conduction time. This results in a net increase in total converter efficiency, despite a small increase in the SR switch channel conduction. A SPS-based rectifier is built with an FPGA based on a commercial SR controller and tested on a 300- $\text{V}_{\mathrm{ in}}$ , 1-kW LLC converter.

In this brief, a 400-W Gallium Nitride device based DC-DC boost converter with a four phase matrix inductor is proposed. It is well-known that there is a significant influence of the DC bias on inductor core losses and the simplest solution is to employ multiphase structures. However, the size of the converter will also increase as the number of phases increases. Therefore, in order to achieve both high efficiency and high power density, a matrix inductor is proposed for four phases boost converter. The proposed matrix inductor retains the flux sharing advantages of conventional inductors with E-cores and thus greatly increases the power density and utilization rate, by integrating the inductors through flux cancellation. Therefore, both the size and the core loss are reduced when compared with four conventional inductors. Moreover, since the four phases are operated in parallel, the phase error, which is a critical problem in the interleaved structure, may not affect the proposed converter, removing the current balance issue. Critical operation mode is utilized to achieve zero-voltage switching (ZVS) for all switches. Finally, the proposed four phase DC-DC boost converter and matrix inductor is built and tested to verify its feasibility. The peak and CEC efficiency is tested to be 99.3% and 99.1%, respectively.

The low-voltage ride through condition (LVRT) attracts wider attention with the increased power of central grid-connected photovoltaic (PV) systems. The conventional double-loop-based control strategy designed for the nominal voltage is slow and potentially unstable under the LVRT operation. In this article, a novel sliding-mode control-based feedback linearization is proposed to improve response speed of the PV system under LVRT condition. To increase the robustness of the control to parameter variations, sliding-mode control is combined with the feedback linearization in this article. Further, the complete linearization of the PV system can be achieved over the whole operating range. Moreover, the dc-link voltage operating point of the PV panel can be dynamically adjusted based on the drop depth of the grid voltage, which will reduce the load changes during the LVRT and subsequently ensure the ac current levels to stay within the design limits in any fault situation and enhance the LVRT capability of the central grid-connected PV system. Finally, a 100-kW PV inverter is built to validate the feasibility and effectiveness of the proposed strategy for LVRT.

In a magnetic bearing system, the levitation coils or electromagnets must be driven by an amplifier in order to control their currents for levitation stability. This amplifier typically drives every coil individually with hard-switching H-bridges. However, the inherent high dv/dt of hard-switching in conjunction with the large parasitic capacitance of magnetic bearing coils typically results in high current spikes and severe ringing in the switching process, which may interfere with position sensors and system communication. Furthermore, driving each coil individually requires a large number of switches. In this brief, a switch sharing zero-voltage-switching (ZVS) multichannel switching amplifier topology is proposed, which not only reduces the number of switches needed when driving multiple coils, but also eliminates current spikes and reduces the switching loss of the magnetic bearing amplifier. The proposed topology is experimentally tested to validate expected benefits.

In inductive power transfer systems, impedance matching is critical in obtaining high efficiency. However, since the load impedance is subject to variations in most applications, especially wireless charging, maintaining impedance matching is a challenge. One valid solution is to maintain the equivalent load impedance at the optimal value against load variations by controlling a load-side power converter. Nonetheless, the system overall cost, size, and complexity can be increased. In this article, based on a proper selection between full-bridge and half-bridge modes of the inverter and rectifier, an operation mode selection method is proposed that can achieve semi-impedance-matching with large load variations. In general, with the proposed method, high overall efficiency can be obtained while neither additional power converters nor complicated control is required. A 1-kW prototype has been developed and the experimental results have verified the proposed method.

The power loop stray inductances of the silicon carbide (SiC) half-bridge power module (HBPM) must be included in the circuit simulation model to predict the power device switching characteristics and the power bus noise caused by the power converter. Instead of a full equivalent circuit model of the SiC HBPM, a simplified but accurate three-terminal equivalent circuit model is presented in this article. Based on the simplified model, a novel frequency-domain impedance measurement method based on the two-port network technique is proposed to extract the power loop inductances through direct measurement. By using the extracted power loop inductances of a 1.2-kV 300-A SiC HBPM, a three-terminal equivalent model of the HBPM is obtained, and its accuracy is validated by the finite element method and experiments.

Conventional critical conduction mode (CRM) control for many boost-derived power factor correction (PFC) circuits forms triangular inductor current. For three-level boost (TLB) converter, the conventional method is unattractive because losses increase but waveform quality remains unchanged, compared to other topologies. In order to obtain higher efficiency and improved waveform qualities, this article focuses on the distinctive structure of TLB and its inherent degree-of-freedom (DOF) in current-slope shaping. Based on the DOF, a new CRM control for TLB PFC is proposed and analyzed. Detailed design and digital implementation method are also provided. Different from conventional methods, the proposed CRM control divides each switching cycle into three parts including common on -time of two switches, additional on -time of one switch and common off -time. Accordingly, TLB inductor current is synthesized in quadrangular forms. The analyses and experimental results confirm that switching frequency and peak input current of TLB can be reduced by the proposed control. Due to the reductions, efficiency, total harmonic distortion, and quality of input current are improved with practically unchanged power factor.

Magnetic characteristics of a switched reluctance motor (SRM) determine the modeling accuracy, the performance of a position sensorless control, and the torque ripple reduction control. Due to double saliency structure and core saturation, the magnetic characteristics of SRM is dependent on both the rotor position and the winding current amplitude, which makes it difficult to measure the actual incremental inductance or flux linkage. This article presents the magnetic characteristics identification method. A quad current sampling technique is proposed to capture the derivative of the winding current at a specific rotor position and current amplitude. The flux linkage, co-energy, and torque are calculated from the obtained incremental inductance profile. The proposed method can be easily implemented on digital signal processor–based SRM drive without any extra circuit. The LCR meter and torque sensor measurements are provided to validate the proposed incremental inductance measurement method.

In this article, an optimal design procedure of shunt RC damped LCL filter is discussed. The proposed design procedure finds the minimum damping resistance to guarantee the stability of the grid-current controller without affecting the effectiveness of the filter. This minimum value is derived using the factorized filter input admittance and filter forward transadmittance. The proposed factorization procedure allows us to have an analytical expression of system poles and zeros. Moreover, the minimum damping resistor is determined upon the desired crossover frequency and the desired phase margin of the grid-current controller. After that, an objective function is assumed, and an optimization problem is formulated to minimize the physical size of the filter by minimizing the total capacitance and inductance and by minimizing the filter ripple content as well. Accordingly, the proposed objective function minimizes the filter physical size and filter power losses and, hence, enhances filter's efficiency. A prototype demonstrates and validates the proposed filter design and analysis experimentally.

Pseudo-dc-link inverters are promising due to the single-stage configuration. The inverters can be isolated by high-frequency transformers, which also provide the freedom of step-up/down through winding turns ratio. Conventionally, a pseudo-dc-link inverter is based upon a pulsewidth modulation converter like flyback converter, but the accompanying switching losses can degrade efficiency and overall system performance. Alternatively, resonant converters (e.g., series resonant converter) seem to fit the need as they typically display soft-switching characteristics. However, the relevant research results are scarce because of two main reasons: high resonant current and limited soft-switching range. To overcome the difficulties, a hybrid modulation method is proposed in this article for a pseudo-dc-link inverter based on series resonant converter. In high-line region, the inverter operates with variable-frequency modulation, which leads to zero-voltage switching and relatively low-resonant current. In low-line region, the inverter operates with a short-pulse density modulation so that switching losses are greatly curtailed without excessive resonant current. The merits in both regions together contribute toward the high efficiency of the inverter. This article presents the operational principle of the proposed modulation as well as a comparison with other modulation methods. In addition, a 400 V–230 V ac, 2-kW prototype was built to verify the proposed modulation and the peak efficiency reaches 98.0%.

Pad misalignments are almost inevitable in most inductive power transfer (IPT) systems. It tends to cause parameter variations and, thus, significantly affects the performance of the IPT system. In this article, a hybrid IPT system with misalignment tolerance using the quadruple-D quadrature pads (QDQPs) is proposed to tolerate the x , y , z , and diagonal misalignments with load-independent output voltage, simplifying or even canceling control schemes. Besides, the proposed approach can restrict the increase of the primary current when the secondary side moves out of the operating region. Moreover, a new parametric design method is presented according to the misalignment characteristics of QDQPs. The method can limit the output voltage fluctuation to a certain range, given a predetermined misalignment distance. A 3.5-kW prototype was built to verify the proposed hybrid IPT system. The primary and secondary coil sizes are 400 mm × 400 mm, and the air gap is 150 mm. Experimental results demonstrate that the proposed hybrid system can tolerate −150 to +150 mm x -misalignment, −150 to +150 mm y -misalignment, −20 to +35 mm z -misalignment, and −100 to +100 mm diagonal misalignment with load-independent output voltage. Within the predetermined misalignment range, the output voltage fluctuation is less than 5%.

This paper presents a bridgeless Cuk-derived single power conversion inverter with reduced number of power components, which has reactive-power capability. The secondary diode of the conventional unfolding-type Cuk inverter is integrated into one of the secondary-side switches in the bridgeless Cuk-derived configuration, which reduces the number of active-power components. A modulation technique is developed to provide a current path during reverse power flow; this technique enables operations under unity and nonunity power factors. A repetitive controller coupled with a linear feedback controller and a feed-forward controller are used to achieve accurate output current tracking under the harsh control environment. Driving the diode-integrated switch in synchronous rectification mode provides higher power conversion efficiency than that under diode-based secondary side rectification. Circuit operation and design guidelines of the bridgeless Cuk inverter are presented in detail. A 500-VA prototype inverter was fabricated to demonstrate the desirable performance of the bridgeless Cuk-derived inverter.

In the no-load condition, LLC converter usually fails to regulate its output voltage although it operates at a high switching frequency. Till now, it is hard to obtain the exact relationship between design parameters and the maximum switching frequency for no-load regulation capability. In this paper, a specific criterion for no-load regulation of LLC converter is provided, without using active components or other modulation schemes. By analyzing the macroscopic switching period and microscopic switching transition in the no-load condition, it is shown that not only the peaking resonant current during the switching transition, but also the resonant tank design affect the no-load regulation of the LLC converter, which affects the no-load regulation capability. Furthermore, the relationship among design parameters is analyzed and the design guideline is also provided to achieve no-load regulation at the specified maximum switching frequency. To verify the effectiveness of the proposed design, 400 V input and 50 V/200 W output prototype is built and tested.

In photovoltaic applications, many previous research works have focused on pulsewidth modulation (PWM) resonant converters in order to achieve a high efficiency with a wide input voltage range. Conventional approaches utilized symmetric boosting modulation at the secondary side rectifier to obtain a symmetric operation, and they utilized two boosting modes in a switching period. Among various rectifier structures, the voltage doubler structure has a strong advantage due to a small number of components. However, it suffers from serious hard switching losses in the secondary side rectifier. In this paper, a new converter with a novel asymmetrical modulation is proposed and verified. The strong point of the proposed converter is that it eliminates hard switching turn- on losses from the rectifier, while maintaining the minimized number of components. Although the proposed converter adopts an asymmetric modulation, the offset current on the transformer becomes zero inherently. Furthermore, a “forced half resonance” operation of the proposed converter keeps rms current stresses at the same level as conventional converter although it has a higher peak current. Accordingly, the proposed converter achieves a superior efficiency with the minimum number of components at 35–25 V input and 380 V/300 W output specification.

The increasing usage of LLC-type dc-dc converters in utility, automotive, and power distribution applications has led to a push for a further increase in the converter's operating load range and efficiency. The secondary-side rectifier remains one of the lossiest areas in the converter, alluring designers to synchronous rectification (SR). One method is drain-source SR for cyclically adaptive, closed loop SR. However, when utilized, a severe current oscillation can be observed. An increase in SR duty cycle results in an increase in conduction time of the SR channel over the body diode. This issue becomes increasingly prevalent due to the usage of wide band-gap MOSFETs with high reverse drops and low sensed signal strength. This results in a current oscillation effect, leading to inconsistent SR operation, output ripple, and high EMI. In this paper, the issue is root caused analyzed. A method of improving drain-source SR for light-load SR operation is proposed. The method is prototyped on an FPGA to alleviate the issue on a $600\text{-}V_{in}/ 340\text{-}V_{out}$ 2.5-kW LLC-DCX (DC transformer) power converter.

This paper presents modeling, control, and system design of three-level boost (TLB) rectifier based medium-voltage (MV) solid-state transformer (SST) for dc fast charger application. In order to operate at MV with 1.2-kV SiC devices, the target system is configured by input-series output-parallel (ISOP) multimodule structure. Each module adopts TLB to front-end rectifier and stacked half-bridge LLCs to back-end isolated dc–dc converters. Operation principles of TLB rectifier and LLC converters are analyzed to derive an equivalent model of the entire system. Based on the detailed derivation, this paper aims to achieve three performance criteria, including bus voltage regulation, input current regulation, and voltage balancing. Basic feedback control loops are designed to control TLB’s output voltage and input current in an average manner, based on the derived system model. Then, ideal TLB duty-ratios in both continuous/discontinuous conduction modes are analyzed and duty-ratio feedforward control is proposed to improve the low quality of input current due to inherent feedback control limitations. For voltage balancing, system design approaches are used in the SST prototype. With the proposed control and system design, a prototype of four-module-stacked TLB SST was built and tested up to 3.8-kVrms and 16-kW conditions.

LLC resonant converter can achieve zero voltage switching (ZVS) for primary-side devices and zero current switching (ZCS) for secondary-side rectifiers. However, the reverse recovery and junction capacitance ( Cj ) of secondary-side diode critically affect the ZVS condition of primary-side switches. The effect of Cj has been discussed in literature, but not the reverse recovery. In this paper, the reverse recovery charge ( Q rr) is converted to an equivalent capacitance $(C_{{\rm rr}\_{\rm eq}})$ for the study of primary-side ZVS performance. An accurate model during deadtime is derived and further applied to characterize ZVS performance with different reverse recovery charges in different regions. The concept of establishing parameter C total to consider both Cj and $C_{{\rm rr}\_{\rm eq}}$ is proposed to evaluate the effect of the secondary-side rectifiers. This concept provides the guideline for diode and synchronous rectification mosfet selection to ensure ZVS condition for LLC converters. To verify the concept and the derived model, a 200/400 V 400 W LLC resonant converter prototype operating from 200 to 700 kHz is built and its ZVS performances with different diodes are compared. Two issues caused by Q rr effect, including $V_{\rm ds}$ reverse charging and asymmetrical waveform during deadtime, are explained thoroughly as well.