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A four-element multi-input multi-output (MIMO) switched capacitor power amplifier (SCPA) in 22-nm fully depleted silicon-on-insulator (FD-SOI) is presented as a software-defined radio. To omit the digital predistortion (DPD) and digital quadrature correction power consumption of this wide modulation bandwidth MIMO transmitter, constant-conductance SCPA drivers and a wideband low-impedance power supply are used for linearization. dtc-based clock calibration is used for quadrature imbalance correction, improving image rejection to > 53 dB. This allows for up to 80-MHz DPD-less single carrier 1024-quadrature amplitude modulation (QAM) transmission, with an error vector magnitude (EVM) < − 39.4 dB. RF bandwidths up to 160 MHz are demonstrated for multicarrier 1024 QAM signals, supporting data rates up to 1.18 GBps. A second-order Chebyshev bandpass filter using bondwires as inductors is used as a matching network, supporting carrier frequencies from 1.64 to 3.28 GHz, while omitting the required chip area for integrated inductors. mimo experiments demonstrate the beamforming capabilities for single and multibeam communication.

Voice Activity Detection (VAD) is a technique used to identify the presence of human voice in an audio signal. It is implemented as an always-on component in most speech processing applications. As speech is absent most of the time, this component typically dominates the overall average power consumption of the system (excluding microphone). The widespread usage in speech applications and the need for ultra low power VAD have led to a plethora of algorithms and implementations in the hardware domain, necessitating a comprehensive study and analysis to understand (real-time) requirements, different design parameters, testing strategies, but also to identify design trends, challenges and guidelines for future implementations and testing of VAD devices. A scoping review was conducted to identify the articles for hardware implementations of VAD from January 2010 -December 2021, the results of which are presented in this article. The results highlight a big design space being used for VAD along with a lack of standard testing methodology and usage of application-dependent performance metrics. An increased usage of filter-based feature extractors along with neural-network-based classifiers is observed. Due to lack of standardisation, no other trends can be established from the results. A set of rules and guidelines are therefore provided to facilitate the future development and benchmarking of VADs.

This article presents a frequency reference system that combines high frequency accuracy and low power consumption using a single-point temperature trim and batch calibration. The system is intended as a low-cost fully integrated crystal oscillator replacement. In this system, the oscillation frequency of a power-efficient, but process, voltage, temperature (PVT) and lifetime (L)-sensitive current-controlled ring oscillator (CCO) is periodically (re)calibrated by the well-behaved frequency stability of an untuned LC –based Colpitts oscillator (LCO), which is optimized for stability over PVT variations and lifetime (PVTL). During the single-point room temperature factory trim, the frequency of the LCO is determined and the result is digitally stored. An on-chip calibration engine tunes the CCO to the target frequency based on the LCO frequency, temperature sensor information, and digitally stored trimming information, thus effectively improving the frequency stability of the ring oscillator. The relatively high-power LCO is heavily duty-cycled to minimize the overall power consumption. A prototype fabricated in a 0.13- μ m CMOS SOI process and assembled in a plastic package demonstrates an inaccuracy lower than ± 93 ppm over a temperature range from − 63 ∘ C to 165 ∘ C across samples. The presented frequency reference system, including on-chip voltage regulators and a temperature sensor, occupies a chip area of 0.69 mm 2 and consumes about 64 μ A from a single 3.3-V supply. The frequency error due to supply variation is roughly 92 ppm/V. The mean frequency shift due to aging, measured before and after a six-day storage bake at 175 ∘ C, is only 52 ppm.

Large-scale multibeam phased array systems suffer from interbeam interference (IBI) that should be canceled either in the analog or digital domain. In wideband systems such as fifth generation (5G), interference rejection over a wide bandwidth is challenging to achieve, not only due to nonidealities of the receiver chain but also due to the properties of the radio channel. This article presents a scalable IBI cancellation (IBIC) scheme at intermediate frequency (IF) using an IF receiver (IF-RX) chip. The IF-RX provides the flexibility of not just interference rejection between the subarrays but also wideband signal combining over multiple subarrays. It also provides wideband filtering before the analog-to-digital converter (ADC) to support 5G channel bandwidths of up to 800 MHz, high linearity, and low noise figure. A calibration method is proposed to find the cancellation coefficients for the IF-RX in measurements. Furthermore, a simplified over-the-air (OTA) IBIC model for analyzing rejection bandwidth limitations is presented. Interference rejection performance is demonstrated through the OTA measurements using 5G new radio (5G NR) signals. In the OTA measurements, 34–37-dB rejection was achieved for 50–100-MHz signals, while error vector magnitude (EVM) requirements of the 5G standards were met with good margins. Finally, the interference rejection over Undefined control sequence \ttimes MHz carrier aggregated 5G NR waveform was demonstrated.

This thesis focuses on reducing the latency and energy consumption associated with the start-up of crystal oscillators in (duty-cycled) low-power wireless systems. A comparison of the state-of-the-art in crystal oscillator start-up shows that energy injection (EI) systems start up faster than negative resistance boosted (NRB) circuits, but do not improve in terms of energy consumption. The main challenge in Energy Injection is the generation of a precise injection signal, which is required to ensure that the injection signal is in-phase with the crystal resonance over the entire injection duration. This thesis proposes a self-timed injection technique that derives the injection waveform timing from the crystal oscillation itself, eliminating the need for an auxiliary injection oscillator. A prototype demonstrates a start-up time of only 6 µs and a start-up energy of 3.7 nJ for a 50 MHz crystal. This research also addresses one of the main energy consumption issues in energy injection circuits by introducing step-wise charging, which reduces energy consumption by 2-4 times. The start-up time and energy are further reduced by combining this with further refinements to the self-timed injection technique. A second prototype starts up in only 2.8 µs, consuming only 1.9 nJ in the process when using the same crystal and using identical measurement conditions as for the first prototype. This work also gives an overview of the design space and limitations in energy injection circuits, aiding in tailoring them to the application and giving insight toward a fair comparison of different techniques. The comparison of various circuits and methods highlights the importance of equal or similar measurement conditions for a fair evaluation. Overall, this thesis aims to achieve fast start-up times, and minimize energy consumption in crystal oscillators. It introduces self-timed injection, as well the application of step-wise charging to crystal oscillators. Compared to other energy injection methods, the proposed techniques offer competitive start-up times while significantly reducing energy consumption.

Hij wist van niets, maar werd deze donderdag de trotse eigenaar van de eerste Dutch Innovation Award. Hoogleraar Bram Nauta - wereldberoemd in chipdesign - ontving die prijs in Theater Concordia uit handen van burgemeester Roelof Bleker. „Zonder hem was Wifi en Bluetooth nooit uitgevonden.’

The University of Twente is backing the decision of IC design professor Bram Nauta to refuse a research collaboration with Nexperia. Nauta and his employer are wary of the chipmaker’s Chinese owner. “A few years ago, a collaboration with Nexperia wouldn’t have been an issue, just like we could also work with Huawei. That’s no longer possible,” Nauta

Universiteit Twente heeft een onderzoek laten schieten uit vrees dat China er met de uitkomsten vandoor zou gaan. Recent bedankte ze voor een samenwerking met de Nijmeegse multinational Nexperia na onderzoek naar diens investeerders.

De Universiteit Twente (UT) haalt zes miljoen euro aan subsidies op voor de nog te bouwen fabriek New Origin. Daar worden zogenoemde fotonische chips gemaakt. Microchips van de volgende generatie, aangedreven door licht.

This thesis is focused on reducing the electromagnetic interference (EMI) due to the residual power after the output filter at the pulse-width modulation (PWM) frequency, the so called ripple. To reduce the ripple current through the speaker leads, it is possible to use a higher order filter, use a multi-phase or multi-level output stage or to inject a cancellation signal after the output filter. First the disturbance is sensed and processed and afterwards a cancellation signal is synthesized and injected into the circuit. A development board utilizing the AX5689 digital amplifier controller IC was used as a design vehicle to realize a prototype bridge-tied-load (BTL) Class-D amplifier with ripple reduction. The built-in analog-to-digital converters (ADCs) were used to measure the output signals of both bridge halves. A selective digital band-pass loop filter was designed in the digital-signal-processing (DSP) core of the AX5689 to only provide high loop-gain around the PWM frequency without affecting the audio band. A ripple reduction of 28 dB for the common-mode (CM) and 18 dB for the differential-mode (DM) was achieved across all signal frequencies and output powers up to 10 W. The Class-A drivers used to inject the anti-ripple have a negative impact on the total system efficiency, which drops from 84% without ripple reduction to 79% with ripple reduction enabled. The technique has virtually no impact on THD+N performance and could be used as an add-on to any Class-D amplifier with a fixed (PWM) frequency. In summary, this thesis shows a feedback technique to reduce the ripple current after the output filter. Thereby the amount of EMI that can be radiated off the speaker leads decreases. The effect of unit delays in the feedback loop has been mitigated by applying a special filter design method to obtain a more stable system. A prototype has been made around an existing amplifier to show the effectiveness of the proposed feedback ripple reduction solution.

ASML mag nu ook niet langer oudere chipmachines naar China experteren, omdat het Westen bang is voor verregaande militaire toepassingen. Waarom moet Beijing worden gestopt? "Het hangt van de kok af, wat je ermee kunt maken"

Fearing overly inflated stories with unverifiable facts, Bram Nauta takes issue with the narrative CV for grant candidates.

A novel algorithm is presented that can resolve frequency ambiguity that arises from sampling a set of signals spanning more than a single Nyquist zone. The method uses two samplers, each sampling the same input signal with different (non-integer multiple) sampling rates. The algorithm is able to resolve frequency ambiguity and reconstruct signals with an orthogonal frequency basis spanning multiple Nyquist zones, provided that the aggregate information-bearing bandwidth of the signals is less than half the cumulative data converter sampling rates. This manuscript describes the theoretical background for the algorithm and validates it through measurements performed on a test-board comprising of two 10 bit analog-to-digital converters clocked at two different (non-integer multiple) sample rates. Measurements show that even in the presence of aliasing, an orthogonal signal spanning multiple Nyquist zones can be fully reconstructed.

If you’re a fan of technology, you may already be familiar with chip design. For those unfamiliar, chip design is the process of creating integrated circuits (ICs) that are used in computers, phones and other electronic devices. It’s a complex process and requires a lot of expertise and experience to get it right.

We present a simple and useful figure of merit (FoM) with which to evaluate the performance of simultaneous-multi-beam (SMB) transmit (TX) antenna arrays. The FoM builds upon the power-aperture product and effective isotropic radiated power for single-beam arrays and extends it to SMB arrays. The FoM is the product of radiated power, antenna aperture efficiency and the amplifiers power added efficiency. We compute the FoM for three different two-beam TX systems to highlight their differences. This will enable systematic comparison and proper system design for modern and future multi-beam radar and communications.

Voor de welvaart van Europa is het cruciaal dat het snel minder afhankelijk wordt van chips uit Azië en Amerika.

Bluetooth Low Energy (BLE) is one of the primary wireless communication protocols for Internet of Things (IoT) devices due to its inherently low energy consumption. BLE’s duty-cycled scheme reduces energy consumption, but at the cost of latency. Wake-Up Receivers (WuRXs) have been proposed to mitigate this trade-off, but most attention seems to have been paid to the circuit design rather than assessing exactly how beneficial a WuRX could be. In this paper, we analyze the power consumption and latency impact of a 200μW WuRX added to a state-of-the-art commercial BLE transceiver for relevant IoT scenarios. The results show that the latency/power trade-off can be significantly relaxed for both peripheral and central devices in initiating a connection. Furthermore, if the role of central and peripherals can be changed (peripherals scan instead of advertise), the power consumption of the most energy-constrained devices can be further reduced in scenarios that require less than 200ms latency to initiate a connection. Also, for a maximum latency of 4s, a duty-cycled WuRX enables equal 60μW average power consumption for both the central and peripheral devices. This is extremely useful when both ends of the link face similar battery constraints, as would be the case in many IoT scenarios.

Exposed to strong cochannel/adjacent-channel interference, digital multiple-input–multiple-output (MIMO) receivers require high-dynamic-range analog-to-digital converters (ADCs). Hybrid beamforming featuring spatial filtering before the ADCs can adaptively mitigate interference in both the analog and digital domains; hence relaxing the required dynamic ranges of the ADCs. This article demonstrates the effectiveness of hybrid beamforming in this mitigation utilizing adaptive minimum mean square error (MMSE) and error vector magnitude (EVM) as an optimization criterion. Extensive EVM measurements are carried out with a conductive setup using a four-element 22-nm FD-SOI CMOS prototype MIMO receiver chip to verify the performance of the adaptive MMSE algorithm. Over-the-air (OTA) measurements with a linear four-element dipole antenna array with half-wavelength spacing in the 2.4-GHz industrial scientific and medical (ISM) band quantify the improvement for real-world scenarios, e.g., having a multipath propagation channel and mutual coupling between the antenna array elements. OTA results show that a rejection of 22.5 and 24.5 dB can be achieved on average in an in-door laboratory environment utilizing vector modulator (VM) constellations with 16 and 64 points, respectively.

The CMOS silicon avalanche-mode light-emitting diode (AMLED) has emerged as a potential light source for monolithic optical interconnects. Earlier we presented a superjunction light-emitting diode (SJLED) that offers a higher electroluminescent intensity compared to a conventional AMLED because of its more uniform field distribution. However, for reducing power consumption low-voltage (< 15V) SJLEDs are desired, not explored before. In this work we present a TCAD simulation feasibility study of the low-voltage SJLED for various doping concentrations and device dimensions. The results show that for obtaining a constant field, approximately a ten-fold more aggressive charge balance condition in the SJLED is estimated than traditionally reported. This is important for establishing a guideline to realize optimized RESURF and SJLEDs in the ever-shrinking advanced CMOS nodes.

Crystal oscillators can be started up quickly by using energy injection techniques. However, the generation of the injection waveform, as well as driving the large capacitive load formed by the crystal, costs a large amount of energy. This article applies the concept of stepwise charging to reduce the energy required to drive the crystal. The energy required to generate the injection waveform by self-timed injection is reduced by using a discrete-time dynamic-bias comparator which uses a simple offset calibration method. Furthermore, the bridge switch resistance is varied dynamically through self-timed control logic to alleviate the accuracy-speed tradeoff. A prototype was manufactured in a 65-nm (triple-well) CMOS technology, which was tested with various crystals ranging from 24 to 50 MHz, improving upon the state of the art in energy consumption.

—A novel application utilizing the load-modulated balanced amplifier (LMBA) principle to actively absorb individual out-of-band intermodulation components at the output of a power amplifier operating in high compression is presented. The system requires nearly the same amount of additional power as the IMD power it absorbs, making it very efficient. It retains the power conservation properties of the LMBA and achieves linearization at a very low power and complexity penalty.

Bram Nauta reunites with a former flame in need of some repairs.

This thesis presents wideband linearization techniques for RF receiver front-ends. The thesis is divided into two parts. The first part proposes a wideband-IF, linear, down-conversion-based receiver front-end mainly for cognitive radio applications. The second part presents a wideband, linear active balun capable of driving gigahertz ADCs up to their full-scale input voltage for direct RF-sampling applications. Driven by Moore's law, transistors have become faster and more compact, increasing the digital capability of a system significantly. The performance of the RF front-ends succeeding or preceding the digital blocks also needs to be increased to match the advances in the digital domain. Data acquisition and communication are examples of such systems where a significant increase in the performance of the RF front ends is paramount. RF receiver front-ends are one of the main constituents of these systems and this thesis focuses on increasing their linearity and bandwidth. RF receivers can be realized primarily either as down-conversion-based or as direct RF-sampling-based. This thesis contributes to increase the linearity and bandwidth in the applications involving both types of receivers. A traditional down-conversion-based receiver architecture has evolved over the decades. Several outcomes of this evolution have benefited a receiver's linearity and bandwidth. An example is a mixer-first receiver, the evolution of which has increased a receiver's achievable linearity to an extent that many recent works target to remove the pre-select filter in the receiver's signal chain. Nevertheless, while targeting high in-band linearity, existing mixer-first receiver architectures show various trade-offs with other performances. This thesis analyses a trade-off that exists between the in-band linearity and NF of the mixer-first receivers in detail, including deriving corresponding symbolic expressions and graphical illustrations. The trade-off that exists between the linearity and RF frequency range of an LNTA operating at RF frequencies is also analysed with detailed simulations. A baseband-matching-resistor noise-cancelling receiver architecture is proposed in this thesis which breaks these trade-offs. Furthermore, to achieve high linearity over a wide TIA bandwidth, a three-stage inverter-only OpAmp with 7.6GHz UGB is designed. The inverter-only design favours its redesign and reuse with the scaling of the technology. The proposed receiver realized on-chip in an FDX 22nm CMOS process measures >9dBm IIP3 over 175MHz TIA bandwidth. The measured NF varies between 2.5 to 5dB in the frequency range between 1 and 6GHz. With the recent advances, gigahertz ADCs support >8bit resolution over >4GHz. Besides the gigahertz ADC, realizing a high-performance balun preceding it is challenging. This balun needs to deliver high voltage swings to the input of the ADC with high linearity over a wide bandwidth. Existing baluns do not favour CMOS integration as they are either off-chip and passive or are fabricated using exotic non-CMOS processes. Existing CMOS active baluns mainly focus on down-conversion-based receivers and are not capable of delivering high voltage swings. A wideband CMOS active balun achieving high linearity up to high voltage swings is proposed in the second part of this thesis. The circuit consists of an LNA at the input followed by an actual balun and the driver blocks. Since the driver blocks experience higher i/o voltage swings compared to other blocks, a PVT robust pre-distorter circuit is used to reduce their distortion. All the circuits are derived from a common highly linear building block (HLBB). The HLBB is evolved from an inverter with strong source degeneration whose dominant nonlinearity mechanisms are analysed in detail. The derived symbolic expressions and simulation results show that there is a limit to increase the strength of source degeneration, after which the linearity benefits are not obtained. A bootstrapping technique is employed in the HLBB to extend this limit and continue to obtain the linearity benefits of the source degeneration. The CMOS active balun fabricated on-chip in an FDX 22nm CMOS process measures < −44dBc HD3 up to 1.5Vp-p over 0.01-5.4GHz. The measured CP1dB corresponds to 2.8Vp-p. The measurement results confirm that all the linearization techniques proposed are robust to PVT variations.

This paper introduces a novel sensor application for online monitoring of the withering condition of leaves. The proposed system is based on the millimeter-wave radar sensitivity and its signal variations that correlate with the water content in a leaf. To validate the experimental prototype, a 60 GHz pulsed coherent radar (PCR) coupled with a dielectric lens was configured. The data obtained by means of the radar sensor is correlated with the data of the conventional gravimetric using a modelling approach based on Beer-Lambert’s law. To the best of our knowledge this is the first proof-of-concept demonstrating the relation between the received signal amplitude from the millimeter-wave radar sensor and plant leaf mass loss.

This work presents an analytical method to design a stable loop filter for a noise shaper with parasitic delays or poles in the loop. This method does not require an increase in the order of the loop or extra feedback paths and keeps the original poles and zeros of the noise-transfer function at the same location. The method has been applied to a low-pass loop filter with a parasitic unit delay and a band-pass loop filter with either three unit delays or a high-frequency pole, obtaining stable loop filters in all three cases.

In this article, we propose a baseband noise-canceling receiver architecture to increase in-band linearity. A key feature of the architecture is that all active circuits are in baseband, including the low-noise transconductance amplifier (LNTA). The LNTA operating at baseband frequencies allows the use of feedback to increase the linearity. This article analyzes a tradeoff that exists between in-band linearity and noise in mixer-first receivers and shows how the proposed architecture breaks such tradeoff. The receiver targets high IF bandwidths, enabled by a transimpedance amplifier (TIA) composed of an OpAmp using only inverters. This article describes the stabilization mechanism of this OpAmp with a unity-gain bandwidth (UGB) of 7.6 GHz. The receiver is fabricated in 22-nm FDSOI CMOS. The measured results show an in-band IIP3 of > 9 dBm for an IF bandwidth of 175 MHz with sub-5-dB noise figure (NF) across 1-6-GHz local oscillator (LO) frequencies.

Hard-switched mixers have attractive linearity and noise properties, but are plagued by spurious responses due to the harmonic content of square-wave local oscillator (LO) signals. Harmonic rejection mixers (HRMs) reject (some of) these responses and can be constructed combining polyphase mixing and amplitude weighting. This brief presents a generalized model for the analysis of the harmonic rejection (HR) of such HRMs, based on circular convolution. We show that the effective LO signal can be modeled as a periodic Dirac impulse filtered by a time-discrete filter. For a multi-stage HR system, this filter consists of multiple stages as well, and the coefficients of each stage can be found simply by inspection. The total HR is shown to be the sum (in dB) of the rejection of the individual filtering stages, highly simplifying analysis and design of HRMs.

The ambition plan ChipTech Twente shows the mission to make an important contribution to the European Commission’s ambition to be less dependent on Asia and the US for chip production. By strengthening the current chip design cluster, investing in research for heterogeneous systems, and realizing a heterogeneous chip factory in Twente, the cluster wants to contribute to solving the global chip shortage, as stated in the press release. Bram Nauta, Professor of Integrated Circuit Design at the University of Twente, and Timo Meinders, Director of the MESA+ Institute, today presented the plans to MEP Bart Groothuis

After an impeccable educational career with the highest of marks in obfuscation and embellishment, a poor graduate asks headhunter Bram Nauta why no company wants to hire him.

In this article, we propose a CMOS active balun targeting high linearity up to high voltage swing and over wide bandwidth for direct RF sampling applications. All the blocks of this active balun are derived using a common highly linear building block (HLBB). The HLBB is designed using an inverter with strong source degeneration. To increase the linearity of this HLBB further, its nonlinearity mechanisms are analyzed in detail. A bootstrapping technique is included in the HLBB to reduce the dominant nonlinearity. Furthermore, a pre-distortion technique cancels most of the non-linearity of the output driving stages. All the linearization techniques proposed are robust to process, voltage, and temperature (PVT) changes. The measured results of the active balun realized on-chip in a 22-nm FDSOI CMOS shows < - 44-dBc third harmonic distortion (HD3) up to 1.5- V p-p output swing over 0.01-5.4 GHz. The measured gain and phase errors of the balun action are less than 0.5 dB and ± 5, respectively. The chip is powered from a 5-V supply and dissipates 925 mW.

Multiple-input multiple-output (MIMO) beamforming array gain can make multi-antenna transmitters (TXs) more power efficient. However, these MIMO TXs require more complex digital predistortion (DPD). In this work, analytical expressions are derived for the power consumption of both MIMO power amplifier (PA) arrays and their respective DPD, taking into account the effects of precoding on PA output power and peak-toaverage power ratio (PAPR). It is shown that for complex DPD algorithms such as cross-over DPD (CO-DPD) in combination with wide bandwidths, the overall DPD power consumption can exceed the overall PA power consumption already for TXs for scenarios with more than two antennas.

Switched capacitor power amplifiers (SCPAs) are a class of digital transmitters which have shown promising results for high linearity with good drain efficiency (DE). Their linearity is limited by AM-PM distortion, caused by a difference in output conductance in switching and nonswitching driver cells. Often, digital predistortion (DPD) is required to transmit higher-order modulation schemes. In this letter, a driver cell implementation as an inverter with drain resistors is proposed which has equal output conductance in both cases, aiming to eliminate AM-PM distortion. An SCPA with these driver cells is implemented in a 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS process which demonstrates excellent DPD-less linearity with an adjacent channel leakage ratio (ACLR) of -50 dB and an error vector magnitude (EVM) of -45.5 dB for 5-MHz 1024 QAM signals at a DE of 8.8%. A matching network exploiting bondwires as high-Q inductors removes on-chip inductors and significantly reduces chip area.

Title: Mixer arrangement with reduced power lower frequency LO, suitable for wake-up receivers Apparatus is disclosed comprising a mixer and a local oscillator (LO) with an oscillation frequency. The apparatus generates a set of LO signals to drive the mixer. Each LO drive signal has a frequency equal to the oscillation frequency multiplied by a first integer multiplication factor m, where m ≥ 2. Each LO drive signal is separated from adjacent LO signals by a phase difference of 360/n°, where n is an integer ≥ 2. In an embodiment, the oscillation frequency is that of a ring oscillator 402. The frequency multiplication is carried out by logic cells 408 which combine square waves from stages of the ring oscillator (figure 5 a & b). In contrast to prior art where a 9-stage ring oscillator operates at fRF/3, the present disclosure provides a 9-stage ring oscillator that operates at fRF/9. The lower oscillator frequency reduces power consumption, which is important in `wake-up' receivers.

Comparators are the core of analog-to-digital converters (ADC), used as sense amplifiers in on-chip data-communication links and memories. The time taken by a clocked comparator to resolve analog inputs near its input-referred noise level into digital output (called CLK-OUT delay, Fig. 3.3.1) often dictates the system's throughput for a given SNR. For SAR ADCs where each bit is determined sequentially, CLK-OUT delay presents a bottleneck in realizing high-speed operation, e.g. beyond 1 00MS/s in 5G/6G baseband application. For a 12-bit 100MS/s SAR ADC at 1 V, e.g., the comparator should resolve signals below 0.5mV within 500ps. Time-interleaving increases ADC throughput but at the cost of increased clock power. Therefore, low-noise energy-efficient GS/s comparators with sub-500ps CLK-OUT delay are indispensable not only for multi-Gb/s serial communication, but also in 5G/6G baseband ADCs. By eliminating static current, dynamic comparators (e.g. Elzakker [1], dynamic bias [2], inverter-amplifier [3]) perform comparisons with high energy efficiency for a given noise level. However, the energy-efficiency of these techniques [1]–[3] has been demonstrated only at low comparator speeds (below 100MS/s) with CLK-OUT delay in the range of a few ns [2] to tens of ns [3]. High-speed (GS/s) comparators [4]–[7] have been demonstrated at only medium noise level (a few mVRMS ) and are energy-inefficient. This work presents an energy-efficient GS/s comparator targeting low-power and low-noise applications in high-speed ADCs and serial communication. The proposed comparator's CLK-OUT delay and input-referred noise remain well within 500ps and 0.5mVRMS over wide input-common-mode voltage, VCM (0.3 to 0.6V) while still maintaining

This brief examines the theoretical interdependence of low-noise-amplifier (LNA) performance parameters to identify four figures of merit (FoMs) that enable the comparison of LNAs. FoM limits are also estimated to identify performance limitations and to quantify room for theoretical improvement. Finally, the results of a regression analysis on nearly 500 CMOS LNAs, published over the past 20 years, are compared to the identified trends, with the findings showing reasonable agreement despite the adoption of some simplifying assumptions.

Instead of paying some company for a fab that will manufacture chips for US companies, Europe should build a chip ecosystem of its own. As we all know, there’s a shortage of chips in the world. Building additional production capacity will take several years due to the long chain of industrial players involved. The fab needs a clean building, inside we need wafer steppers and other machines. Moreover, these machines must be built from parts that are in short supply. In addition, the world needs to keep innovating toward more advanced CMOS nodes and develop even more advanced machines. All this is a complex process that’s hard to accelerate.

Analog finite-impulse-response (AFIR) filtering is proposed to realize low-power channel selection filters for the Internet-of-Things receivers. High selectivity is achieved using an architecture based on only a single—time-varying—transconductance and integration capacitor. The transconductance is implemented as a digital-to-analog converter and is programmable by an on-chip memory. The AFIR operating principle is shown step by step, including its complete transfer function with aliasing. The filter bandwidth and transfer function are highly programmable through the transconductance coefficients and clock frequency. Moreover, the transconductance programmability allows an almost ideal filter response to be realized by careful analysis and compensation of the parasitic circuit impairments. The filter, manufactured in 22-nm FDSOI, has an active area of 0.09 mm 2. Its bandwidth can be accurately tuned from 0.06 to 3.4 MHz. The filter consumes 92 $\mu \text{W}$ from a 700-mV supply. This low power consumption is combined with a high selectivity: $\text{f}_{-60\,\text {dB}}/\text{f}_{-3\,\text {dB}}\,\,=$ 3.8. The filter has 31.5-dB gain and 12-nV/ $\sqrt {\text {Hz}}$ input-referred noise for a 0.43-MHz bandwidth. The OIP3 is 28 dBm, independent of the frequency offset. The output-referred 1-dB-compression point is 3.7 dBm, and the in-band gain compresses by 1 dB for an −3.7-dBm out-of-band input signal while still providing >60 dB of filtering.

The ever increasing demand for wireless connectivity is leading to congested radio spectrum especially in the sub-6 GHz. This makes the interference problem a major challenge for wireless systems. This thesis targets hybrid analog digital beamforming receiver architectures to exploit the potential of spatial filtering for interference mitigation. We propose a new reconfigurable multi-beam architecture supporting both digital MIMO and analog spatial filtering. Spatial interference rejection is achieved using a set of flexible orthogonal beams with a programmable spatial-direction. RF/analog beamforming is realized by an improved constant-Gm vector modulator (VM). A 4-element 22-nm FD-SOI CMOS prototype MIMO Rx achieves widely tunable RF operating frequency range, covering much of the sub-6GHz bands (0.7-5.7 GHz). The Rx front-end also achieves a highly blocker tolerant performance with B1dB of -11.5 dBm, a high in-band linearity (in-notch IIP3 of +20 dBm), and a wide notch suppression bandwidth. A single-element noise figure of 5.5-7 dB is achieved on the vector modulator constellation corners. The chip of 0.52 mm2 active area consumes 77-139mW at an LO-frequency of 0.7-5.7 GHz from a 0.8V supply. We propose to characterize the interference robustness of MIMO receivers featuring hybrid analog-digital beamforming using EVM. This thesis also demonstrates the effectiveness of hybrid beamforming in interference mitigation utilizing adaptive Minimum Mean Square Error (MMSE) and Error Vector Magnitude (EVM) as an optimization criterion. Extensive EVM measurements carried out with a conductive set-up using a 4-element 22nm FD-SOI CMOS prototype MIMO receiver chip verify the performance of the adaptive MMSE algorithm. Over-the-Air (OTA) measurements with a linear 4-element dipole antenna array with half-wavelength spacing in the 2.4 GHz ISM-band quantify the improvement for real world scenarios, e.g., having a multipath propagation channel and mutual coupling between the antenna array elements. OTA results show that a rejection of 22.5 dB and 24.5 dB can be achieved on average in an in-door laboratory environment utilizing Vector Modulator (VM) constellations with 16 and 64 points, respectively.

A FIR filter that is arranged to receive an analog input signal and sample the analog input signal at a plurality of discrete points in time k with a sampling frequency fS to obtain a sampled analog input signal having a continuous signal value. The FIR filter is further arranged to generate a scaled analog input signal having a continuous signal value by scaling the sampled 5 analog input signal on the basis of a plurality of scaling coefficients. The FIR filter further arranged to provide, by integration over a timed window, an integrated signal which is the sum of L scaled analog signal samples, L being an integer value, and to provide the integrated signal as an output signal from the integrator at an output rate.

The introduction of the internet of things (IoT) resulted in a significant increase in the demand for low-cost battery powered wireless transceivers. To decrease the cost of wireless transceivers, a full implementation on a single die or package, in a modern CMOS technology is preferred. However, with newer CMOS technologies both the maximum supply voltage and the breakdown voltage decrease, reducing the maximum achievable output power that the RF-PA can achieve from the nominal power-supply for a fixed load impedance. Switched mode class-E PAs are promising candidates for battery powered wireless devices, since they can ideally achieve 100% power efficiency and can be integrated in modern CMOS technologies. The performance and reliability of class-E PAs strongly depends on the load impedance, where load variations can reduce the performance and even permanently damage the RF-PA. To enable tuning and improving the performance and reliability of RF-PAs accurate information about its current operating conditions are required, which can be acquired from the internal nodes of the RF-PA. The focus of this work is on integrated measurement techniques, reliability improvements and linearisation for RF-PAs to enable efficient, robust and high-performance RF-PAs for use in modern wireless transceivers. A sampling technique to measure relevant internal RF-waveforms is presented. The acquired waveform information is later used to improve reliability and performance of a class-E PA. To improve the reliability of class-E PAs, a technique to self-protect the class-E PA by decreasing the PAs sensitivity to load variations is introduced. An on-chip switched-capacitor bank is used to tune the relative-resonance frequency of the switch-LC tank, minimizing the stress on the switch transistor over load variations, improving the reliability. A polar class-E PA with adaptive digital pre-distortion (ADPD) is presented, resulting in a reduction of the effect of load variations on the polar modulated class-E PA. The on-chip waveform characterizer is used to measure the internal drain voltage of the PA, after which the measured waveform is used to adaptively tune the DPD coefficients such that the RF-PA can maintain its performance over an VSWR up to 9:1.

Terwijl Nederland zo’n 230 miljoen euro wil gaan uittrekken om de chipindustrie in Europa te stimuleren, pompen de Chinezen en Amerikanen samen honderden miljarden in de industrie. Bram Nauta, als hoogleraar bij de Universiteit Twente gespecialiseerd in chipdesign, noemt het een lachertje. Toch is het volgens hem voor Europa nog niet te laat om er serieus mee aan de slag te gaan.

Het is klein, voor iets dat aan de basis heeft gestaan van de wereld waarin we nu leven. Een soort hoekig mechanisch insect van zo’n anderhalve centimeter lang met twee rijen van acht metalen poten. Zonder deze uitvinding zou een lange lijst aan apparaten niet bestaan of anders werken: laptops, wasmachines, magnetrons, ovens, thermostaten, auto’s, smartphones.

We propose a fast and simple method to accurately determine the compressing stage in a two-stage amplifier system based on reverse intermodulation and hot S-parameter measurements. The method uses no specialized hardware and needs little reconfiguration, simplifying the measurements. We demonstrate its validity over a broad range of amplifiers designed in various semiconductor technologies. This method is a very useful tool in understanding or debugging amplifier designs.

A single-trim, highly accurate Colpitts-based frequency reference is presented. Our analysis shows that the Colpitts-topology outperforms the cross-coupled LC -topology in terms of temperature stability. Measurements on prototypes in a 0.13- $\mu \text{m}$ high-voltage CMOS silicon on insulator (SOI) process were carried out from −50 °C to 170 °C. Based on sample-specific single room temperature trim and batch calibration, our frequency reference achieves an accuracy of ±120 ppm for 16 samples from a single wafer utilized for extracting the batch-calibration polynomial and ±300 ppm for 48 samples across three wafers from the same batch. This is a 4 $\times $ improvement over related single-trim state-of-the-art solutions. Frequency drift due to aging, tested after a six-day 175 °C storage, is below 100 ppm. The oscillator core dissipates 3.5 mW from a 2.5-V supply and has 220-ppm/V supply sensitivity without supply regulation.

The conspiracy theories are true: the corona pandemic was engineered to inject the world’s population with 5G chips. One brave scientist who helped develop the technology steps forward.

Europa moet de komende jaren tientallen miljarden euro’s in een eigen chipindustrie steken om geen vazalstaat van China te worden. Dat is de les die beleidsmakers zo snel mogelijk moeten trekken uit het huidige chiptekort. Volgens hoogleraar Integrated Circuit Design Bram Nauta (Universiteit Twente) is het daarvoor belangrijk dat politici begrijpen dat innovatie in micro-elektronica nog lang de motor van technisch vooruitgang zal blijven.

This article presents a multi-receiver cross-correlation technique for (B)FSK receivers, targeting wireless sensor network applications. Here, multiple receiver outputs are pair-wise cross-correlated and the correlated output samples are averaged to lower the noise floor at the receiver output. Compared to a two-receiver cross-correlation, multi-receiver cross-correlation generates more cross-correlated output samples in a given time. Hence it requires a shorter measurement time for a desired noise floor reduction and facilitates a higher data rate for (B)FSK operation. Compared to a single receiver, it improves the linearity and the harmonic interferer tolerance using passive splitters and different LO frequencies in the receiver paths respectively. These theoretical insights are verified with measurements for the first time using a 2- and 3-receiver cross-correlation in a BFSK receiver. Operating at 1GHz and with a data rate of 200kbps, the demonstrator, using sub-mW mixer-first receiver front-ends for power efficiency, achieves −102dBm sensitivity and >40 dB rejection for both narrow and wideband harmonic interferers without any RF filters.