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A data acquisition system for processing signals produced by direct photon conversion sensors, primarily for applications in digital X-ray imaging, has been developed. The system comprises a custom-made PCI card, a front-end readout ASIC, and a digital counting ASIC. The operation of the readout ASIC is optimized for input capacitance of 2 pF per strip, which includes both the detector and the interconnection capacitance. The dynamic range of the system is extended from 30 up to 250 keV. Since the readout chip also includes a polarity select circuit, the system is suitable for applications with electron or hole collecting detectors. Due to the adopted readout architecture the counting rate achieved is extremely high, up to 3 MHz, while the measured noise was around 1200 electrons for 2 pF detector capacitance. The real-time imaging system is under evaluation in combination with CdTe detectors as front-end of a luggage inspection system. In this paper, the architecture and the performance of the two ASICs of the system are presented. Index Terms--Author, please supply your own keywords or send a blank e-mail to keywords@ieee.org to receive a list of suggested keywords.

An ultra fast current amplifier with a novel active feedback loop has been designed. A prototype has been manufactured in 1.2[[micro]meter] CMOS technology. The peaking time measured is 7ns with a gain of 2.5mV/fC. The circuit recovers to baseline within 20ns. With a silicon area of 0.05[mm.sup.2] and a power consumption of 3mW at a power supply of [+ or -]2V, it is an attractive solution for multichannel IC's used in readout systems. Typical applications include imaging systems, particle detection and solid state detector interfacing where very high counting rate is encountered.

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-µm CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8° rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm². [ABSTRACT FROM AUTHOR]