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In this paper, a new method for evaluating hot-electron degradation in p-GaN gate AlGaN/GaN power HEMTs is proposed. The method exploits a commercial parameter analyzer to study VTH and RON drifts induced by on-state stress at VDS = 50 V. The results show that VTH drift and part of the RON degradation induced by the on-state stress are recoverable and likely due to the ionization of C-related acceptors in the buffer. This was confirmed by a preliminary characterization of C-related buffer traps. Conversely, the remaining part of RON degradation (not recovered in 1000 s) was strongly affected by the surface treatment. The current level set during on-state stress affected the amount of non-recoverable degradation, confirming the involvement of hot electrons. Thanks to the monitoring of the parameters’ recovery, the proposed method provides important insights into the physical mechanisms governing the parameters’ degradation. This extends the capabilities of state-of-the art systems, without the need for custom setup development.

In this article, we propose a set of new expressions of four noise parameters for InP high electron mobility transistor (HEMT) devices based on PRC noise equivalent circuit model. The effects of gate‐to‐drain capacitance, drain‐to‐source conductance as well as extrinsic resistances have been taken into account. High consistency between measured and modeled noise parameters for 70 nm HEMT with 2 × 30 μm gate width in the frequency range 8–50 GHz are given by the expressions. Great usability is demonstrated for determination of small signal and noise model parameters extraction. [ABSTRACT FROM AUTHOR]

In this paper, a new method for evaluating hot-electron degradation in p-GaN gate AlGaN/GaN power HEMTs is proposed. The method exploits a commercial parameter analyzer to study VTH and RON drifts induced by on-state stress at VDS = 50 V. The results show that VTH drift and part of the RON degradation induced by the on-state stress are recoverable and likely due to the ionization of C-related acceptors in the buffer. This was confirmed by a preliminary characterization of C-related buffer traps. Conversely, the remaining part of RON degradation (not recovered in 1000 s) was strongly affected by the surface treatment. The current level set during on-state stress affected the amount of non-recoverable degradation, confirming the involvement of hot electrons. Thanks to the monitoring of the parameters' recovery, the proposed method provides important insights into the physical mechanisms governing the parameters' degradation. This extends the capabilities of state-of-the art systems, without the need for custom setup development. [ABSTRACT FROM AUTHOR]

Various high-k dielectrics have been proposed for AlGaN/GaN MOSHEMTs for gate leakage and drain-current collapse suppression. Hafnium oxide (HfO2) is particularly interesting because of its large bandgap, high dielectric constant, and ferroelectricity under specific phase and doping conditions. However, defects and surface scattering caused by HfO2 dissimilarity and degraded HfO2/GaN interface quality still leave the challenge of reducing the SS and Ron. In this study, we investigated the effects of the first spike-annealed HfO2 (6 nm) layer, compared with the conventional ALD-HfO2 (6 nm) layer in the HfO2 bilayer gate dielectric structure on AlGaN/GaN HEMTs. Both devices exhibit negligible hysteresis and near-ideal (~60 mV/dec) subthreshold slopes of more than three orders of magnitude. The device with the first annealed HfO2 layer exhibited a reduced Ron with notably less gate bias dependency and enhanced output current. On the other hand, the capacitance–voltage and conductance methods revealed that the border and interface trap densities of the device were inferior to those of the conventional HfO2 layer. The trade-off between enhanced electrical performance and oxide traps is discussed based on these results. [ABSTRACT FROM AUTHOR]

Recently, crack-free GaN-on-Si growth technology has become increasingly important due to the high demand for power semiconductor devices with high performances. In this paper, we have experimentally optimized the buffer structures such as the AlN nucleation layer and step-graded AlGaN layer for AlGaN/GaN HEMTs on Si (111) substrate by varying growth conditions and thickness, which is very crucial for achieving crack-free GaN-on-Si epitaxial growth. Moreover, an AlGaN back barrier was inserted to reduce the buffer trapping effects, resulting in the enhancement of carrier confinement and suppression of current dispersion. Firstly, the AlN nucleation layer was optimized with a thickness of 285 nm, providing the smoothest surface confirmed by SEM image. On the AlN nucleation layer, four step-graded AlGaN layers were sequentially grown by increasing the Al composition from undermost layer to uppermost layer, meaning that the undermost one was close to AlN, and the uppermost was close to GaN, to reduce the stress and strain in the epitaxial layer gradually. It was also verified that the thicker step-graded AlGaN buffer layer is suitable for better crystalline quality and surface morphology and lower buffer leakage current, as expected. On these optimized buffer structures, the AlGaN back barrier was introduced, and the effects of the back barrier were clearly observed in the device characteristics of the AlGaN/GaN HEMTs on Si (111) substrate such as the transfer characteristics, output characteristics and pulsed I-V characteristics. [ABSTRACT FROM AUTHOR]

We prepared AlGaN/GaN high electron mobility transistors (HEMTs) with GaN cap thicknesses of 0, 1, 3, and 5 nm and compared the material characteristics and device performances. It was found that the surface morphology of the epitaxial layer was effectively improved after the introduction of the GaN cap layer. With the increase of the GaN cap thickness, the carrier concentration (ns) decreased and the carrier mobility (μH) increased. Although the drain saturation current (IdSat) of the device decreased with the increasing GaN cap thickness, the excessively thin GaN layer was not suitable for the cap layer. The thicker GaN layer not only improved the surface topography of the epitaxial layer but also effectively improved the off-state characteristics of the device. The optimal cap thickness was determined to be 3 nm. With the introduction of the 3 nm GaN cap, the IdSat was not significantly reduced. However, both the off-state gate leakage current (IgLeak) and the off-state leakage current (IdLeak) decreased by about two orders of magnitude, and the breakdown voltage (BV) increased by about 70 V. [ABSTRACT FROM AUTHOR]

In this paper, we propose an improved method for extracting the four noise parameters of InP HEMT devices based on a 50- $\Omega $ noise measurement system. The noise equivalent circuit and noise correlation matrix technique is combined with 50- $\Omega $ noise measurement to determine the noise parameters. This method eliminates expensive tuners and obtains accurate initial parameter values. The reduction in the fitting factors that need to be optimized simplifies the optimization process of traditional methods. High consistency between measured and modeled noise parameters up to 50 GHz for InP HEMT with 70 nm gatelength and $2\times 50\,\,\mu \text{m}$ gatewidth are given by this method. These are providing a simple and fast way for the measurement process of noise parameters.

In this paper, AlGaN/GaN high-electron-mobility transistors (HEMTs) with ohmic etching patterns (OEPs) "fabricated to improve device radio frequency (RF) performance for Ka-band applications" are reported. The fabricated AlGaN/GaN HEMTs with OEP structures were used to reduce the source and drain resistances (Rs and Rd) for RF performance improvements. Within the proposed study using 1 μm hole, 3 μm hole, 1 μm line, and 3 μm line OEP HEMTs with 2 × 25 μm gate widths, the small signal performance, large signal performance, and minimum noise figure (NFmin) with optimized values were measured for 1 μm line OEP HEMTs. The cut-off frequency (fT) and maximum oscillation frequency (fmax) value of the 1 μm line OEP device exhibited optimized values of 36.4 GHz and 158.29 GHz, respectively. The load–pull results show that the 1 μm line OEP HEMTs exhibited an optimized maximum output power density (Pout, max) of 1.94 W/mm at 28 GHz. The 1 μm line OEP HEMTs also exhibited an optimized NFmin of 1.75 dB at 28 GHz. The increase in the contact area between the ohmic metal and the AlGaN barrier layer was used to reduce the contact resistance of the OEP HEMTs, and the results show that the 1 μm line OEP HEMT could be fabricated, producing the best improvement in RF performance for Ka-band applications. [ABSTRACT FROM AUTHOR]

We prepared AlGaN/GaN high electron mobility transistors (HEMTs) with GaN cap thicknesses of 0, 1, 3, and 5 nm and compared the material characteristics and device performances. It was found that the surface morphology of the epitaxial layer was effectively improved after the introduction of the GaN cap layer. With the increase of the GaN cap thickness, the carrier concentration (ns) decreased and the carrier mobility (μH) increased. Although the drain saturation current (IdSat) of the device decreased with the increasing GaN cap thickness, the excessively thin GaN layer was not suitable for the cap layer. The thicker GaN layer not only improved the surface topography of the epitaxial layer but also effectively improved the off-state characteristics of the device. The optimal cap thickness was determined to be 3 nm. With the introduction of the 3 nm GaN cap, the IdSat was not significantly reduced. However, both the off-state gate leakage current (IgLeak) and the off-state leakage current (IdLeak) decreased by about two orders of magnitude, and the breakdown voltage (BV) increased by about 70 V.

DC-DC converters exist in virtually every application of modern power electronics. Due to small die size, low on-resistance, and low parasitic capacitance, GaN power devices offer superior conversion efficiency and record-setting power density. In this paper, test-to-fail methodology is adopted to investigate the intrinsic wear-out mechanisms such as would be experienced in common DC-DC converters. Devices are stressed under gate bias, drain bias, and temperature cycling individually. The lifetime of each stressor is therefore projected based on the physics-based model developed from test-to-fail and an understanding of the unique stress conditions in DC-DC converters.

In this article, an enhancement mode (E-mode) p-GaN gate AlGaN/GaN high electron mobility transistor (HEMT) with the novel strain technology (NST) has been proposed. The NST consists of GaN/AlGaN/GaN and AlN/AlGaN/GaN heterojunctions laterally from the gate to drain side. By utilizing the different polarization effect of these two heterojunctions, it laterally forms different density of two-dimensional electron gas (2DEG). Accordingly, it decreases the electric field around the gate and introduces an extra electric field peak far away from the gate edge to improve the breakdown voltage (BV) effectively. The experimental BV of the proposed NST-HEMT is increased by 52 % to 1185 V from 780 V of the conventional HEMT. Meanwhile, the output current of NST-HEMT is almost consistent with the conventional HEMT. Moreover, the NST-HEMT realizes better hot electrons mitigation than conventional HMET, and its Vth and Ron degradations are only 1.38 % and 10.72 % after 8 h stress time.

A three-phase GaN-based motor inverter IC with three integrated phase current mirror sensors (sense-FETs or sense-HEMTs, 1200:1 ratio), a temperature sensor, and an amplifier is presented and experimentally operated. The three low-side currents are read out by virtual grounding transimpedance amplifiers. A modified summed DC current readout circuit using only one amplifier is also discussed. During continuous 24 V motor operation with space-vector pulse width modulation (SVPWM), the sensor signal is measured and a bidirectional measurement capability is verified. The measured risetime of the sensor signal is 51 ns, indicating around 7 MHz bandwidth (without intentional optimization for high bandwidth). The IC is operated up to 32 V on DC-biased semi-floating substrate to limit negative static back-gating of the high-side transistors to around −7% of the DC-link voltage. Analysis of the capacitive coupling from the three switch-nodes to the substrate is calculated for SVPWM based on capacitance measurement, resulting in four discrete semi-floating substrate voltage levels, which is experimentally verified. Integrated advanced power converter topologies with sensors improve the power density of power electronics applications, such as for low-voltage motor drive. [ABSTRACT FROM AUTHOR]

Herein, we report the design and implementation of planar and circular aluminium gallium nitride/Gallium nitride high electron mobility transistor (AlGaN/GaN HEMT) designs for pH sensing applications along with the insights into pH sensing to elucidate the underlying mechanism. The planar and circular devices were fabricated on the same wafer where the sensing membrane and passivation is realized by $\rm Al_{2}O_{3}$. The devices were encapsulated with photoresist and small openings are created for source/drain electrode contact pads and the sensing region where pH solution is confined to test the device response. The response of sensors is compared after normalizing circular HEMT output for a width of 100 $\mu{\rm m}$. The output current sensitivity is in the range of 75 (0.5 V) to 222.5 (2 V) $\mu {\rm A}$ /pH for planar HEMT device, whereas sensitivity values for circular HEMT is in the range of 0.152 (0.5 V) to 0.5 (2 V) mA/pH, respectively between pH 2 to 10. The circular HEMT device design depicted higher sensitivity and better linearity in response to pH due to the conduction throughout its circumference. The transient response is also studied and the results suggest a stable pH resolution and good linearity for both acidic and basic phosphate buffer saline (PBS). The higher current values are obtained, which is an advantage in terms of signal processing and conditioning unit for proper measurement that will help in reducing complexities in the integrated circuit (IC) and, therefore ease in point-of-care diagnosis. [ABSTRACT FROM AUTHOR]

In this work, for the first time, we have investigated an analytical model for β-MIS-(AlGa)2O3/Ga2O3 ion-sensitive FET by using commercial Silvaco and MATLAB tools for non-ideality behavior around the isoelectric point. Gouy-Chapman-Stern theory is used to analyze the electrical double layer with the electrolyte. Al2O3 is used as a dielectric between (AlGa)2O3 and electrolyte. The pH sensor detects the variation in hydrogen ion concentration in the aqueous solution. Different electrolyte concentrations (1 mM, 0.01 M, 0.1 M) are used in aqueous solution to find sensitive parameters such as surface potential, charge density, Alpha, βint, Cdiff and CDL for different pH values. Changes in surface potential and other sensitive parameters affect the intensity of 2DEG at the interface of (AlGa)2O3 and Ga2O3 in β-MIS-(AlGa)2O3/Ga2O3 HEMT. The behavior of pH- sensitive parameters are also discussed before and after the isoelectric point. Variation in electrolyte concentration shows that lower electrolyte concentration has high sensitivity. Effects of variation of pH on potential, H+ and OH− concentration with bulk distance have also been discussed. Transfer characteristics, threshold voltage, ION/IOFF of β-MIS-(AlGa)2O3/Ga2O3 HEMT have been investigated for different pH values. Threshold voltage increases with pH when pH moves from acidic to basic medium. [ABSTRACT FROM AUTHOR]

The lateral GaN power semiconductor technology enables monolithic integration of complete power converter topologies such as half-bridges, multi-phase and multi-level converters. Fabrication on Si substrates enables low-cost and mass production. However, the operation of monolithic GaN power converters on a common conductive silicon (Si) substrate is limited compared to discrete GaN HEMTs, especially at high-voltage operation, due to substrate-biasing effects such as back-gated or trap-related static and dynamic on-resistance increase, and changed effective device capacitances. To circumvent the Si substrate related effects but still using a low-cost large-diameter Si substrate, this paper reviews isolation approaches for GaN ICs such as Si p-n junction isolation or floating Si substrates (GaN-on-Si) and buried oxide isolation using Silicon-on-Insulator substrates (GaN-on-SOI). Published GaN power converter ICs are reviewed. The effect of the isolation approaches on increased output and input transistor capacitances, influencing the switching behavior and switching loss, is calculated and compared for different voltage classes (below 100 V to 600 V-class). Finally, design guidelines for local substrate termination using the Si-based isolation approaches are discussed exemplary for a monolithic half-bridge with driver circuit. Monolithic GaN power converter integration combined with functional integration will result in a new class of advanced power converter ICs, and enable efficient, compact and low-cost power conversion applications.

AlGaN/GaN‐based high electron mobility transistors (HEMTs) are ideal candidates for power electronics in consumer, industrial, and space applications. Attributed to their excellent performance in electrical output and chemical stability, AlGaN/GaN HEMTs enable tolerant neutron irradiation in harsh environments. Different from high‐fluence irradiation‐induced device failure, the investigation of low‐fluence neutron irradiation is of great significance to understand the early damage mechanism of HEMTs. Here, the modulated electrical properties are presented of AlGaN/GaN HEMTs under low‐fluence neutron irradiations of 4.5 × 1013 and 6.0 × 1013 cm−2. After irradiation, the electrical characteristics of the samples are carefully measured, the output performance of different irradiated devices shows a similar change trend, i.e., almost no changes or only decreased slightly (≤14%) near the knee voltage. For leakage current, the samples irradiated with different fluences show different characteristics, including a slight decrease with the fluence of 4.5 × 1013 cm−2, and a slight increase with the fluence of 6.0 × 1013 cm−2. To further investigate the internal mechanisms, the performance changes are also simulated of the device by using Crosslight software. According to the measurements, it is concluded that the low‐fluence neutron irradiation will initially affect the 2DEG mobility and the surface states of the HEMTs. [ABSTRACT FROM AUTHOR]

A study of 1.7 kV normally-off p-GaN gate high-electron-mobility transistors (HEMTs) on SiC substrates is presented. The fabricated p-GaN HEMT with a gate-drain spacing LGD = 5 µm exhibited a threshold voltage of 1.10 V, a maximum drain current of 235 mA/mm, an ON/OFF ratio of 108, and a breakdown voltage of 440 V. Benefiting from the semi-insulating and high-critical-electric-field substrate, the p-GaN HEMT with LGD = 23 µm achieved the remarkably high breakdown voltage of 1740 V with substrate grounded. This breakdown voltage is very high compared with the reported values for p-GaN HEMTs on silicon substrates with substrate grounded. The vertical breakdown voltage for the p-GaN-on-SiC material exceeded 3 kV with substrate grounded. In addition, the maximum drain current at 500 K was 48% of that at 300 K with a negligible threshold voltage shift. These results indicate the substantial potential of p-GaN gate HEMTs on SiC substrates for high-voltage power applications. [ABSTRACT FROM AUTHOR]

For gallium nitride (GaN) based triangular current mode (TCM) applications, the dead-time has a significant effect on the switching loss. However, previous GaN high electron mobility transistor (HEMT) models focus on the turn-on/off process without fully considering the effect of the dead-time. Hence, this article analyzes the switching transients under the superfluous and insufficient dead-time and evaluates the dead-time loss with an improved GaN HEMT model. The proposed model improves an existing GaN HEMT model by adding the voltage rising/falling time of the gate driver, the dynamic threshold voltage of Schottky-type GaN HEMTs, and an equivalent gate-drain capacitance obtained from the datasheet. Verified by a GaN-based double-pulse test, the proposed model can more accurately calculate the gate-source voltage and the self-commutated reverse conduction voltage. Verified by a GaN-based TCM Buck converter, the proposed model can predict the dead-time loss well and has higher simulation accuracy for the turn-on process induced by the inappropriate dead-time. [ABSTRACT FROM AUTHOR]

A switching power amplifier (SPA) provides the driving current for an active magnetic bearing (AMB) to achieve magnetic suspension (MS) control. The performances of the current bandwidth and current ripple should be significantly considered in the SPA of the AMB. The SPA can obtain a wide bandwidth by increasing the dc-link voltage. However, a high dc-link voltage will cause a high current ripple. To achieve a wide bandwidth and low current ripple, a new GaN-device-based SPA for the AMB of a flywheel energy storage system (FESS) is proposed in this article. The GaN SPA can operate at a high switching frequency and high dc-link voltage. Thus, the GaN SPA can improve the performance of the current bandwidth and current ripple compared to the conventional SPA. According to the characteristics of the GaN SPA, a low-loss PWM method and an optimal dead time strategy is proposed to increase the efficiency of the SPA. Furthermore, a high-response control approach of dead-beat model predictive control is proposed to further improve the current bandwidth. The proposed GaN SPA is applied in a 500-kW MS FESS prototype. The effectiveness of the SPA is verified experimentally. [ABSTRACT FROM AUTHOR]

This article presents two techniques to address the reliability issues caused by dv/dt under fast switching conditions of gallium nitride high electron mobility transistors. The first technique called active overdrive voltage control is proposed to adjust the gate driving strength according to the rising speed of the switching node (dv/dt) adaptively and, thus, decrease the dv/dt without increasing too much switching loss. The second technique is three-branch high-voltage level shifter (TBLS), which can improve the dv/dt immunity without compromising the signal transmission speed. The common mode current caused by dv/dt can be copied and then compensated by a transient current provided by the auxiliary branch. Combining the above techniques, a 400 V half bridge gate driver IC is fabricated by silicon-on-insulator BCD process. Compared with the gate driver IC utilizing the conventional open-loop output stage, the proposed gate driver IC reduces the turn-on switching loss by 16.2% for the same level of peak dv/dt at 400 V 10 A application. In addition, the proposed TBLS can achieve the dv/dt immunity up to 100 V/ns meanwhile the propagation delay less than 14 ns, enabling megahertz operation frequency. [ABSTRACT FROM AUTHOR]

Because of their fast-switching speed and small die size, gallium-nitride high electron mobility transistors are challenging to package for low parasitic inductance and high heat dissipation in power electronics applications. In this article, a packaging technique was developed for making half-bridge modules of a 650 V, 150 A enhancement-mode gallium-nitride power transistor. The package consists of the device chips interconnected between a printed circuit board and an aluminum-nitride direct-bonded copper substrate. The dice are bonded on the insulated ceramic substrate by silver-sintering to ensure high thermal performance and joint reliability. The source, drain, and gate pads are connected by silver-sintering gold-plated pins or silver rods, which are aligned by holes or grooves in the circuit board. For electrical insulation and mechanical robustness, the space surrounding the device is filled by injecting and curing an underfill polymer. Electrical and thermal simulations of the package show that the half-bridge module has a 1.122 nH power-loop inductance, and 0.099 °C/W junction-to-case thermal resistance. Packages of the half-bridge module were fabricated, and their static and dynamic performances were characterized. [ABSTRACT FROM AUTHOR]

GaN high electron mobility transistors (HEMTs) have limited avalanche capability and usually fail catastrophically in voltage overshoot up to their dynamic breakdown voltage (BVdyn). This article presents the first comparative study of the parametric shift and recovery of three mainstream GaN HEMTs in repetitive overvoltage switching near their BVdyn. In each switching cycle, a voltage overshoot up to 90% of BVdyn was applied during the turn-off process. As the switching prolongs, all devices showed shifts in threshold voltage and saturation current, and these shifts saturated in less than 1-million cycles. These shifts are believed to be induced by the trapping of the holes generated in the impact ionization (I. I.). The device's poststress recovery was found to be dominated by the hole detrapping and through-gate removal, which highly depends on the gate stack. The gate injection transistor showed a fast natural recovery benefitted from the efficient hole removal through the Ohmic gate. The hole detrapping in the Schottky-type p-gate HEMT can be described by the Poole–Frenkel emission, allowing for the accelerated recoveries at negative gate bias and high temperatures. The hole removal in the metal-insulator-semiconductor (MIS) HEMT is blocked by the gate insulator, preventing a natural recovery. The MIS-HEMT can be recovered by applying positive gate and substrate biases, which facilitate the hole recombination in the channel. This article shows the good overvoltage robustness of all three GaN HEMTs and unveils effective methods for their poststress recovery, as well as suggests the significant impacts of I. I. and hole dynamics on the overvoltage ruggedness of GaN HEMTs near BVdyn. [ABSTRACT FROM AUTHOR]

In this paper, AlGaN/GaN high-electron-mobility transistors (HEMTs) with ohmic etching patterns (OEPs) “fabricated to improve device radio frequency (RF) performance for Ka-band applications” are reported. The fabricated AlGaN/GaN HEMTs with OEP structures were used to reduce the source and drain resistances (Rs and Rd) for RF performance improvements. Within the proposed study using 1 μm hole, 3 μm hole, 1 μm line, and 3 μm line OEP HEMTs with 2 × 25 μm gate widths, the small signal performance, large signal performance, and minimum noise figure (NFmin) with optimized values were measured for 1 μm line OEP HEMTs. The cut-off frequency (fT) and maximum oscillation frequency (fmax) value of the 1 μm line OEP device exhibited optimized values of 36.4 GHz and 158.29 GHz, respectively. The load–pull results show that the 1 μm line OEP HEMTs exhibited an optimized maximum output power density (Pout, max) of 1.94 W/mm at 28 GHz. The 1 μm line OEP HEMTs also exhibited an optimized NFmin of 1.75 dB at 28 GHz. The increase in the contact area between the ohmic metal and the AlGaN barrier layer was used to reduce the contact resistance of the OEP HEMTs, and the results show that the 1 μm line OEP HEMT could be fabricated, producing the best improvement in RF performance for Ka-band applications.

The paper proposes a new analytical model of the drain current in AlGaN-GaN high-electron-mobility transistors (HEMT) on the basis of a polynomial expression for the Fermi level as a function of the concentration of charge carriers. The study investigated the influence of parasitic resistances (source and drain sides), high-speed saturation, the amount of aluminum in the AlGaN barrier, and low field mobility. To isolate the output characteristics, cut-off frequency and steepness, the parameters of the hyper frequency signal were developed. Comparison of analytical calculations with experimental measurements confirmed the validity of the proposed model.

Herein, the results are reviewed concerning reliability of high‐electron mobility transistors (HEMTs) based on GaN, which currently represent the technology of choice for high‐efficiency microwave and millimeter‐wave power amplifiers. Several failure mechanisms of these devices are extensively studied, including converse piezoelectric effects, formation of conductive percolation paths at the edge of gate toward the drain, surface oxidation of GaN, time‐dependent breakdown of GaN buffer, and of field‐plate dielectric. For GaN HEMTs with scaled gate length, the simultaneous control of short‐channel effects, deep‐level dispersion, and hot‐electron‐induced degradation requires a careful optimization of epitaxial material quality and device design. [ABSTRACT FROM AUTHOR]

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

The current limiting function enables the solid-state circuit breaker (SSCB) to have proper protection coordination. It allows sustained overcurrent for a certain period while preventing the fast fault current increase in dc systems. For the conventional method of using switches alone to limit the current, the high loss results in a short withstand time and low current limiting capability of the SSCBs. In this letter, a control strategy is proposed to utilize the energy absorption component to handle the major part of the energy during the current limiting stage to increase the current limiting capability for series-connected SSCB switching cells. The proposed method is experimentally verified to have more than 3X current limiting withstand time compared to the conventional control strategy in a case study. [ABSTRACT FROM AUTHOR]

The goal of this manuscript is to use the Silvaco Atlas TCAD simulator to investigate the effect of some parameters on the current-voltage characteristics of a high-electron-mobility transistors devices based on AlxGay1-xN/GaN, Advanced AlxGay1-xN/AlN/GaN heterostructures with GaN channel layer and AlN spacer layer. It is demonstrated that numerical simulation can be used effectively in the development of HEMTs. We looked into the effect of the GaN thickness layer on the current-voltage characteristics, as well as the effect of the δ -doped layer within AlxGa1-xN barrier layer, the effect of the spacer thickness is also considered. Among the sample structures we used for our computations, our calculations reveal a low threshold voltage value and the maximum transconductance. Our structure with GaN channel layer thickness of 200 nm, Al content of x = 0.2 with a δ -doped layer of n = 5 x 1018 cm-3, we find that the maximum saturation current. [ABSTRACT FROM AUTHOR]

In this article, the proposed monolithic gallium nitride (GaN)-based driver uses the diode-emulated technique to reduce reverse conduction through a meta-stable fast (MSF) comparator with sub-0.2-ns deadtime. In addition, an active bootstrap controller with a fast discharge loop is used to reduce parasitic effects to improve the driving capability, thereby increasing the switching frequency. Furthermore, the proposed gate driver with dual $dv/dt$ control can reduce the gate-ringing during turn-on/turn-off. Experimental results show that the GaN-based monolithic driver can achieve an operating frequency of 50 MHz and a slew rate of 120 V/ns. At 50 MHz, the conversion of 48-to-5 V can achieve a peak efficiency of 95.4% at the load current of 3.5 A. [ABSTRACT FROM AUTHOR]

This work investigates the impacts of structural parameters on the performances of p-GaN/AlGaN/GaN HEMT-based ultraviolet (UV) phototransistors (PTs) using Silvaco Atlas. The simulation results show that a larger Al content or greater thickness for the AlGaN barrier layer can induce a higher two-dimensional electron gas (2DEG) density and produce a larger photocurrent. However, they may also lead to a larger dark current due to the incomplete depletion of the GaN channel layer. The depletion conditions with various Al contents and thicknesses of the AlGaN layer are investigated in detail, and a borderline between full depletion and incomplete depletion was drawn. An optimized structure with an Al content of 0.23 and a thickness of 14 nm is achieved for UV-PT, which exhibits a high photocurrent density of 92.11 mA/mm, a low dark current density of 7.68 × 10−10 mA/mm, and a large photo-to-dark-current ratio of over 1011 at a drain voltage of 5 V. In addition, the effects of other structural parameters, such as the thickness and hole concentration of the p-GaN layer as well as the thickness of the GaN channel layer, on the performances of the UV-PTs are also studied in this work. [ABSTRACT FROM AUTHOR]

The emergence of gallium nitride high-electron-mobility transistor (GaN HEMT) devices has the potential to deliver high power and high frequency with performances surpassing mainstream silicon and other advanced semiconductor field-effect transistor (FET) technologies. Nevertheless, HEMT devices suffer from certain parasitic and reliability concerns that limit their performance. This paper aims to review the latest experimental evidence regarding HEMT technologies on the parasitic issues that affect aluminum gallium nitride (AlGaN)/GaN HEMTs. The first part of this review provides a brief introduction to AlGaN/GaN HEMT technologies, and the second part outlines the challenges often faced during HEMT fabrication, such as normally-on operation, self-heating effects, current collapse, peak electric field distribution, gate leakages, and high ohmic contact resistance. Finally, a number of effective approaches to enhancing the device's performance are addressed. [ABSTRACT FROM AUTHOR]

This letter analyzes the velocity-field relationship of AlGaN/GaN HFETs via Monte Carlo simulation. This method is based on complete scattering mechanisms such as polarized coulomb field scattering (PCF scattering), polar optical phonon scattering, acoustic deformation potential scattering, inter-valley phonon scattering, and piezoelectric scattering. It is found that the gate bias voltage affects the PCF scattering intensity and the PCF scattering intensity influences the drift velocity under a high electric field. A decrease in peak steady-state drift velocity is observed for our fabricated AlGaN/GaN HFETs from ${1.335}\times {10}^{{5}}$ m/s at $\text{V}_{\text {gs}} =$ 0 V to ${1.23}\times {10}^{{5}}$ m/s at $\text{V}_{\text {gs}} =-3$ V as the gate voltage becomes more negative. When combined with the velocity-field relationship obtained from Monte Carlo simulations, the calculated current-voltage characteristics of AlGaN/GaN HFET devices are in good agreement with our experiment results. The electron saturation drift velocity deviation of AlGaN/GaN HFETs from the Monte Carlo simulation of the GaN material is attributed to the presence of PCF scattering in AlGaN/GaN HFETs. In the study, we provide strong support for the accurate modeling of AlGaN/GaN HFETs. [ABSTRACT FROM AUTHOR]

This letter reports a novel method for fabricating Schottky/ohmic drain for GaN high electron mobility transistors (HEMTs). Without secondary photolithography or secondary metal evaporation, the Schottky/ohmic drain can be obtained by adjusting the direction of the electron beam evaporation. Besides, different metal/semiconductor interfaces can be simultaneously formed at this state, which are beneficial to enhance the shielding effect of the rough ohmic-drain metal morphology and modulate the electric field distribution on the drain side. By using Schottky/ohmic drain technology, the average breakdown voltage calculated from 50 devices each is improved from 895 V (ohmic drain device) to 1205 V for $\text{L}_{\text {GD}} = 18\,\,\mu \text{m}$ , indicating enhanced off-state reliability characteristics for GaN HEMTs. [ABSTRACT FROM AUTHOR]

A neural network (NN)-based hybrid physical model for gallium nitride high-electron-mobility transistors (GaN HEMTs) is proposed. In this model, the artificial NN (ANN) is used to construct the terminal charge densities, which is linked with device model’s RF and dc performance using the MIT Virtual Source (MVS) theory. A detailed parameter extraction and optimization method for this hybrid model is proposed as well. The parameter extraction starts from S-parameters with the consideration of access region resistances. The particle swarm optimization (PSO) is used to optimize extraction results. After that, a two-hidden-layer ANN is constructed to model the obtained source-end terminal charge density ($q_{\mathrm {is}}$) and drain-end terminal charge density ($q_{\mathrm {id}}$). Then, the ANN-based $q_{\mathrm {is}}$ and $q_{\mathrm {id}}$ are used to construct the hybrid model under the framework of the MVS theory. The trapping effects and self-heating effects are also considered in this hybrid model. This hybrid model is built and verified in the Advanced Design System (ADS). The proposed hybrid model has better scalability than the traditional ANN-based models. It is also more accurate than the traditional MVS-based physical model. This hybrid model presents satisfactory agreement between measured and simulated current–voltage (IV), S-parameters, load—pulls, and power sweeps. [ABSTRACT FROM AUTHOR]

Class-E power amplifiers are widely used in megahertz frequency power conversion systems due to their high efficiency, which can further be enhanced by virtue of wide-bandgap devices such as GaN high-electron-mobility transistors. Here, a GaN-based cross-quadrant mode Class-E amplifier is proposed, which addresses one of the major challenges for such amplifiers, i.e., to achieve both high power and high efficiency with low-voltage-rating devices. By utilizing the reverse conduction of GaN transistors, a cross-quadrant mode Class-E amplifier with small dc-feed inductance is constructed, whose circuit model is derived by virtue of the Laplace transform technique. We demonstrate an experimental prototype operating at 3.11 MHz with a 100-V GaN transistor, achieving an output power of about 6 W with the efficiency being almost 90% when the input voltage is 10 V and the load resistance is 28 $\mathrm{\Omega }$. Compared with conventional Class-E amplifiers, the power conversion capability of the proposed amplifier is increased up to three times from 0.49 to 1.69 with a slight reduction in efficiency. Such cross-quadrant mode amplifiers can be used to improve the power conversion capability and to reduce the peak switch voltage at the same output power level. [ABSTRACT FROM AUTHOR]

The recently proposed independently controlled multiple output flyback converter (ICMOFC) scheme improves cross-regulation by utilizing gallium nitride (GaN) switches with negative gate turn-off voltage. The highly inefficient reverse conduction (RC) of negative gate biased GaN devices leads to significant RC loss in the existing ICMOFC scheme. To mitigate this problem, this letter proposes a new pulsewidth modulation (PWM) scheme. The RC loss reduction is achieved by reducing the RC duration and RC current. The effectiveness of the proposed PWM strategy is analytically and experimentally verified using a 40-W dual output flyback converter. The results demonstrate a peak efficiency improvement of 1.26% over the existing ICMOFC scheme. Furthermore, the scheme also achieves high power density (51 W/in $^{3}$) and excellent cross-regulation (0.2%). [ABSTRACT FROM AUTHOR]

A GaN on engineered bulk silicon (GaN-on-EBUS) power IC platform featuring an industry-standard 200-V GaN power HEMT epi-structure has been recently demonstrated, showing effective isolation and crosstalk suppression between the high-side (HS) and low-side (LS) GaN transistors in half-bridge configuration. In this work, we scale up the vertical breakdown voltage (BV) of the GaN film on the EBUS substrate to be over 600 V. Meanwhile, the built-in back-to-back PN junctions along the trench created in the Si substrate are employed to provide an overvoltage-protection scheme through their intrinsic avalanche capability for the overlaying GaN half-bridge circuit. [ABSTRACT FROM AUTHOR]

In this letter, a linearity enhancement AlGaN/ GaN high electron mobility transistor (HEMT) with high power density and high efficiency has been achieved by selective-area charge implantation (SCI) for X-band application. Device-level transconductance compensation is realized by an under-gate SCI technique, which greatly improves the linearity of the device. The device presents a maximum drain current of 1390 mA/mm and a peak transconductance of 230 mS/mm. The gate voltage swing is up to 5.2 V, which is double of the conventional devices. At 12 GHz with a drain voltage of 25 V, the SCI device exhibits a peak power added efficiency of 47 % and a saturated output power density of 6.7 W/mm. In addition, the two-tone measurement results at 12 GHz show that the SCI device manifest an excellent linearity figure of merit OIP3/ $\text{P}_{\text {DC}}$ of 11.2 dB, whereas that of the conventional HEMTs is only 5.5 dB. These results suggest SCI HEMTs have immense potential for microwave power amplifiers requiring high linearity. [ABSTRACT FROM AUTHOR]

In this letter, we present an extensive analysis on the role of both switching frequency (ranging from 100 kHz to 1 MHz) and duty cycle (from 10% to 90%) on the time-dependent gate breakdown of high electron mobility transistors (HEMTs) with Schottky metal to p-GaN gate. More specifically, results show how the gate lifetime of GaN HEMTs increases by reducing the frequency and the duty cycle of the stressing gate signal (VG). Such behavior is ascribed to the OFF-time, which is responsible to alter the electrostatic potential in the p-GaN layer during the rising phases of VG (from OFF- to ON-state). Findings of this analysis are useful both for further technology improvement and for GaN-based power circuit designers. [ABSTRACT FROM AUTHOR]

${p}$ -channel GaN field-effect transistors (FETs) with a SiNx/GaON gate stack have been demonstrated with enhanced stability within a wide range of voltage bias and temperature. In this letter, the gate leakage characteristics and reliability of this unconventional staggered gate stack are investigated. At relatively low gate voltages, the gate current is suppressed owing to the buried-channel structure and the presence of GaON that presents an effective hole barrier. With more negative gate biases, the gate leakage was found to be dominated by the transport of holes that spillover from the ${p}$ -channel through the SiNx via Poole-Frenkel emission. Based on this gate leakage mechanism at large gate bias, $\sqrt {{\mathrm {E}}} $ model was used for gate lifetime prediction. The maximum applicable ON-state gate voltage of −7.3 V is obtained for a 10-year lifetime with a 1% gate failure rate. [ABSTRACT FROM AUTHOR]

A research of total ionizing dose and annealing effects on Schottky type p-GaN gate Al0.2Ga0.8N/GaN high electron mobility transistors (HEMTs) has been carried out. Devices with breakdown voltages of 100V/200V/650V were irradiated under Co-60 X-rays. Radiation doses reach to a total amount of 500 krad (Si) with dose rate of 50 rad(Si)/s under gate biases of ${V}_{GS}=0\text{V}$ /+3V/+5V. Negative threshold voltage shifts were observed, especially under positive gate biases. It is found out that the threshold voltage shifts are due to the accumulation of positive charges (holes) trapped in the interface of p-GaN/AlGaN. Therefore, the shift amount is proportional to the gate bias and the radiation amount, while not related to the breakdown voltage. After the total ionizing dose experiments, both high temperature and room temperature annealing processes were taken. During the annealing processes, the shifted threshold voltage recovered, and high temperature accelerated the recovery process. Experiment results indicate that the total ionizing dose effect is recoverable. [ABSTRACT FROM AUTHOR]

A study of GaN for high temperature (HT, up to 500 °C) digital circuits was conducted. A HT-robust GaN-on-Si technology based on enhancement-mode p-GaN-gate AlGaN/GaN high electron mobility transistors (HEMTs) and depletion-mode AlGaN/GaN HEMTs was proposed and used to implement different digital circuit configurations, namely E/D-mode and E/E-mode (E: enhancement, D: depletion). The E/D-mode inverter was found to offer significantly better performance in terms of voltage swing, noise margin, and gain, across temperature and ${V}_{\textit {DD}}$ scaling. As calculated from E/D-mode ring oscillators (ROs) with ${L}_{G}=2\,\,\mu \text{m}$ , a RO exhibited a propagation delay (${t}_{p}$) of < 1.48 ns/stage at 500 °C. The best RO achieved ${t}_{p} < 0.18$ ns/stage at 25 °C. To the best of the authors’ knowledge, the proposed technology sets a new boundary of ${t}_{p}$ vs. ${L}_{G}$ in wide band gap digital logic, and is operational at the highest reported temperature (500 °C) of a GaN digital circuit. The results reflect the promising potential of the proposed technology for emerging HT applications at 500 °C and beyond. [ABSTRACT FROM AUTHOR]

Mechanical stress wave characteristic parameters are important for analyzing the health of power devices and are the basis of power cycling experiments to establish the connection between the device’s health status and its mechanical stress wave. Based on acoustic emission detection technology, this article analyzes the generation principle of the mechanical stress wave in cascode gallium nitride (GaN) HEMT first and then designs repeatability tests to analyze the stress wave characteristics at different locations of the device and the variation law of stress wave characteristic parameters. We found that the stress wave acoustic emission source is at the bottom middle of the device. Stress waves in the 60–90 and 150–180 kHz frequency bands are generated when the device is turned on or off. It is positively correlated with the drain–source voltage and has a good peak parameter fitting curve on the package surface, while the stress wave has no relationship with the gate–source voltage. [ABSTRACT FROM AUTHOR]

In this letter, the unclamped-inductive-switching (UIS) behaviors of GaN-based high-electron-mobility transistors with p-type GaN gate (p-GaN HEMTs) at cryogenic temperature (CT) are first revealed. Unlike the temperature-dependent avalanche-induced failure for SiC devices during UIS process, the withstanding behaviors and final critical breakdown voltage of p-GaN HEMT during UIS process at CT are completely consistent with the results at room temperature. As proved, the resonant circuit formed by device output capacitance and load inductor is the key factor influencing UIS waveforms, and such state is temperature insensitive. Furthermore, the inverse-piezoelectric effect induced by high electric field during UIS process is demonstrated to be the original cause that makes this temperature-independent failure phenomenon. In conclusion, the UIS withstanding capability of p-GaN HEMT will not be degraded in such an extremely low temperature scene, indicating a superiority of p-GaN HEMT for special applications compared with traditional devices. [ABSTRACT FROM AUTHOR]